)]}'
{
  "log": [
    {
      "commit": "4dcc29e1574d88f4465ba865ed82800032f76418",
      "tree": "5579a225a6782f0f5014cbbe6938847b7f3cd53f",
      "parents": [
        "e490517a039a99d692cb3a5561941b0a5f576172"
      ],
      "author": {
        "name": "Tony Luck",
        "email": "tony.luck@intel.com",
        "time": "Tue May 27 13:23:16 2008 -0700"
      },
      "committer": {
        "name": "Tony Luck",
        "email": "tony.luck@intel.com",
        "time": "Tue May 27 13:24:39 2008 -0700"
      },
      "message": "[IA64] Workaround for RSE issue\n\nProblem: An application violating the architectural rules regarding\noperation dependencies and having specific Register Stack Engine (RSE)\nstate at the time of the violation, may result in an illegal operation\nfault and invalid RSE state.  Such faults may initiate a cascade of\nrepeated illegal operation faults within OS interruption handlers.\nThe specific behavior is OS dependent.\n\nImplication: An application causing an illegal operation fault with\nspecific RSE state may result in a series of illegal operation faults\nand an eventual OS stack overflow condition.\n\nWorkaround: OS interruption handlers that switch to kernel backing\nstore implement a check for invalid RSE state to avoid the series\nof illegal operation faults.\n\nThe core of the workaround is the RSE_WORKAROUND code sequence\ninserted into each invocation of the SAVE_MIN_WITH_COVER and\nSAVE_MIN_WITH_COVER_R19 macros.  This sequence includes hard-coded\nconstants that depend on the number of stacked physical registers\nbeing 96.  The rest of this patch consists of code to disable this\nworkaround should this not be the case (with the presumption that\nif a future Itanium processor increases the number of registers, it\nwould also remove the need for this patch).\n\nMove the start of the RBS up to a mod32 boundary to avoid some\ncorner cases.\n\nThe dispatch_illegal_op_fault code outgrew the spot it was\nsquatting in when built with this patch and CONFIG_VIRT_CPU_ACCOUNTING\u003dy\nMove it out to the end of the ivt.\n\nSigned-off-by: Tony Luck \u003ctony.luck@intel.com\u003e\n"
    },
    {
      "commit": "a0776ec8e97bf109e7d973d09fc3e1814eb32bfb",
      "tree": "0c247bdd764fafc19390904d85acd8ef6a065595",
      "parents": [
        "62d0cfcb27cf755cebdc93ca95dabc83608007cd"
      ],
      "author": {
        "name": "Chen, Kenneth W",
        "email": "kenneth.w.chen@intel.com",
        "time": "Fri Oct 13 10:05:45 2006 -0700"
      },
      "committer": {
        "name": "Tony Luck",
        "email": "tony.luck@intel.com",
        "time": "Tue Feb 06 15:04:18 2007 -0800"
      },
      "message": "[IA64] remove per-cpu ia64_phys_stacked_size_p8\n\nIt\u0027s not efficient to use a per-cpu variable just to store\nhow many physical stack register a cpu has.  Ever since the\nincarnation of ia64 up till upcoming Montecito processor, that\nvariable has \"glued\" to 96. Having a variable in memory means\nthat the kernel is burning an extra cacheline access on every\nsyscall and kernel exit path.  Such \"static\" value is better\nserved with the instruction patching utility exists today.\nConvert ia64_phys_stacked_size_p8 into dynamic insn patching.\n\nThis also has a pleasant side effect of eliminating access to\nper-cpu area while psr.ic\u003d0 in the kernel exit path. (fixable\nfor per-cpu DTC work, but why bother?)\n\nThere are some concerns with the default value that the instruc-\ntion encoded in the kernel image.  It shouldn\u0027t be concerned.\nThe reasons are:\n\n(1) cpu_init() is called at CPU initialization.  In there, we\n    find out physical stack register size from PAL and patch\n    two instructions in kernel exit code.  The code in question\n    can not be executed before the patching is done.\n\n(2) current implementation stores zero in ia64_phys_stacked_size_p8,\n    and that\u0027s what the current kernel exit path loads the value with.\n    With the new code, it is equivalent that we store reg size 96\n    in ia64_phys_stacked_size_p8, thus creating a better safety net.\n    Given (1) above can never fail, having (2) is just a bonus.\n\nAll in all, this patch allow one less memory reference in the kernel\nexit path, thus reducing syscall and interrupt return latency; and\navoid polluting potential useful data in the CPU cache.\n\nSigned-off-by: Ken Chen \u003ckenneth.w.chen@intel.com\u003e\nSigned-off-by: Tony Luck \u003ctony.luck@intel.com\u003e\n"
    },
    {
      "commit": "1da177e4c3f41524e886b7f1b8a0c1fc7321cac2",
      "tree": "0bba044c4ce775e45a88a51686b5d9f90697ea9d",
      "parents": [],
      "author": {
        "name": "Linus Torvalds",
        "email": "torvalds@ppc970.osdl.org",
        "time": "Sat Apr 16 15:20:36 2005 -0700"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@ppc970.osdl.org",
        "time": "Sat Apr 16 15:20:36 2005 -0700"
      },
      "message": "Linux-2.6.12-rc2\n\nInitial git repository build. I\u0027m not bothering with the full history,\neven though we have it. We can create a separate \"historical\" git\narchive of that later if we want to, and in the meantime it\u0027s about\n3.2GB when imported into git - space that would just make the early\ngit days unnecessarily complicated, when we don\u0027t have a lot of good\ninfrastructure for it.\n\nLet it rip!\n"
    }
  ]
}