)]}' { "log": [ { "commit": "1014cfe2fb4cdd663137aafb21448cb613dd6a7d", "tree": "13b5fc4e7036b4226d94bd33aefb74a3dbb25b6a", "parents": [ "8123d8f17d8ba9d67e556688e4f025456ca97842", "4726f2a617ebd868a4fdeb5679613b897e5f1676" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue May 18 08:17:35 2010 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue May 18 08:17:35 2010 -0700" }, "message": "Merge branch \u0027core-locking-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip\n\n* \u0027core-locking-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:\n lockdep: Reduce stack_trace usage\n lockdep: No need to disable preemption in debug atomic ops\n lockdep: Actually _dec_ in debug_atomic_dec\n lockdep: Provide off case for redundant_hardirqs_on increment\n lockdep: Simplify debug atomic ops\n lockdep: Fix redundant_hardirqs_on incremented with irqs enabled\n lockstat: Make lockstat counting per cpu\n i8253: Convert i8253_lock to raw_spinlock\n" }, { "commit": "f3d46f9d3194e0329216002a8724d4c0957abc79", "tree": "6d9413e4a448d7b8d342c40297c4fbe0b9c4c2f0", "parents": [ "e40152ee1e1c7a63f4777791863215e3faa37a86" ], "author": { "name": "Anton Blanchard", "email": "anton@samba.org", "time": "Mon May 17 14:33:53 2010 +1000" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon May 17 07:57:27 2010 -0700" }, "message": "atomic_t: Cast to volatile when accessing atomic variables\n\nIn preparation for removing volatile from the atomic_t definition, this\npatch adds a volatile cast to all the atomic read functions.\n\nSigned-off-by: Anton Blanchard \u003canton@samba.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "95e8f634d7a3ea5af40ec3fa42c8a152fd3a0624", "tree": "67da92dd5fa7fc27ebd25a9b524166ef182793ae", "parents": [ "3f8bf8f0fd79410fbcbf9dd9910dbc9d4882c94f" ], "author": { "name": "Shane McDonald", "email": "mcdonald.shane@gmail.com", "time": "Thu May 06 23:26:57 2010 -0600" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat May 15 21:59:53 2010 +0100" }, "message": " MIPS FPU emulator: allow Cause bits of FCSR to be writeable by ctc1\n \n In the FPU emulator code of the MIPS, the Cause bits of the FCSR register\n are not currently writeable by the ctc1 instruction. In odd corner cases,\n this can cause problems. For example, a case existed where a divide-by-zero\n exception was generated by the FPU, and the signal handler attempted to\n restore the FPU registers to their state before the exception occurred. In\n this particular setup, writing the old value to the FCSR register would\n cause another divide-by-zero exception to occur immediately. The solution\n is to change the ctc1 instruction emulator code to allow the Cause bits of\n the FCSR register to be writeable. This is the behaviour of the hardware\n that the code is emulating.\n \n This problem was found by Shane McDonald, but the credit for the fix goes\n to Kevin Kissell. In Kevin\u0027s words:\n \n I submit that the bug is indeed in that ctc_op: case of the emulator. The\n Cause bits (17:12) are supposed to be writable by that instruction, but the\n CTC1 emulation won\u0027t let them be updated by the instruction. I think that\n actually if you just completely removed lines 387-388 [...] things would\n work a good deal better. At least, it would be a more accurate emulation of\n the architecturally defined FPU. If I wanted to be really, really pedantic\n (which I sometimes do), I\u0027d also protect the reserved bits that aren\u0027t\n necessarily writable.\n \n Signed-off-by: Shane McDonald \u003cmcdonald.shane@gmail.com\u003e\n To: anemo@mba.ocn.ne.jp\n To: kevink@paralogos.com\n To: sshtylyov@mvista.com\n Patchwork: http://patchwork.linux-mips.org/patch/1205/\n Signed-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n\n---\n" }, { "commit": "53ba4f2fa73225113a488584df0d85d3cba52943", "tree": "d85b984d9818abc3ccc0237eb53b710d9e96c39e", "parents": [ "bd6d29c25bb1a24a4c160ec5de43e0004e01f72b", "66f41d4c5c8a5deed66fdcc84509376c9a0bf9d8" ], "author": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Mon May 03 09:17:01 2010 +0200" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Mon May 03 09:17:01 2010 +0200" }, "message": "Merge commit \u0027v2.6.34-rc6\u0027 into core/locking\n" }, { "commit": "b197b6286650feb9c991826519065aac6f4399b1", "tree": "96bb05f49595948f2a7f9fbe985da59cdfa55f83", "parents": [ "8bbda428e90a2b638428fbb07abd80b9cb624a27" ], "author": { "name": "Wu Zhangjin", "email": "wuzhangjin@gmail.com", "time": "Sat Apr 10 20:07:01 2010 +0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Apr 30 20:52:58 2010 +0100" }, "message": "MIPS: Loongson-2F: Use CONFIG_CPU_JUMP_WORKAROUNDS to control workarounds.\n\nSigned-off-by: Wu Zhangjin \u003cwuzhangjin@gmail.com\u003e\nCc: linux-mips \u003clinux-mips@linux-mips.org\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/1106/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "94c26c9a66a35d4da3ab200864d1afd14c91fb71", "tree": "efb052b20d1f54be3816ada723bf581d2e367464", "parents": [ "514b6d0c06a5d751259f145d9593b4d084c1cce3" ], "author": { "name": "Arnaud Patard", "email": "apatard@mandriva.com", "time": "Thu Apr 29 11:58:51 2010 +0200" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Apr 30 20:52:51 2010 +0100" }, "message": "MIPS: Loongson: Fix LOONGSON_ADDRWIN_CFG macro.\n\nThere\u0027s a typo in the LOONGSON_ADDRWIN_CFG macro. The cpu window mmap\nregister address should contain the destination parameters not the\nsource one. This has not been noticed because the code is only using\nsource \u003d destination.\n\nSigned-off-by: Arnaud Patard \u003capatard@mandriva.com\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: http://patchwork.linux-mips.org/patch/1162/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "26b9e547e90db6b8b409084a9d4501124ff492b3", "tree": "020bfdc2f464477b032e2bc5d766a36382f7e5b4", "parents": [ "ce384d83d00ee457c3931d3fdb9fa2c38e345a3c" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Wed Apr 28 12:16:16 2010 -0700" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Apr 30 20:52:45 2010 +0100" }, "message": "MIPS: Add uasm_i_dsrl_safe() and uasm_i_dsll_safe() to uasm.\n\nThis allows us to clean up the code by not having to explicitly code\nchecks for shift amounts greater than 32.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: http://patchwork.linux-mips.org/patch/1153/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "ce384d83d00ee457c3931d3fdb9fa2c38e345a3c", "tree": "9f2a8a21236f0a270118d393e893cdc4986d229b", "parents": [ "fcf3ca4c3d6d911df8ee2b8f010ffe504d3aef71" ], "author": { "name": "Yury Polyanskiy", "email": "ypolyans@princeton.edu", "time": "Mon Apr 26 00:53:10 2010 -0400" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Apr 30 20:52:45 2010 +0100" }, "message": "MIPS: die() does not call die notifier chain\n\nThe MIPS implementation of die() forgets to call notify_die() and thus notifiers\nregistered via register_die_notifier() are not called. This results in kgdb not\nbeing activated on exceptions.\n\nThe only subtlety is that notify_die declares its regs argument w/o const, so\nthe const had to be removed from mips die() as well.\n\n[Ralf: Fixed build error for SGI IP22 and IP28 platforms.]\n\nSigned-off-by: Yury Polyanskiy \u003cypolyans@princeton.edu\u003e\nCc: linux-mips@linux-mips.org\nPatchworks: http://patchwork.linux-mips.org/patch/1142/\nAcked-by: Jason Wessel \u003cjason.wessel@windriver.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n\n---\n" }, { "commit": "9eed4124c0d56d39b06224765c65eaa35f580edf", "tree": "38ba0866b2e2a01865bd21a7ceb81ca56698b1df", "parents": [ "c8f3cc0b65af00be5f84c6d4ee45007643322713" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Wed Apr 21 11:39:07 2010 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Apr 30 20:52:41 2010 +0100" }, "message": "MIPS: cmpxchg.h: Fix excessive indentation.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "c8f3cc0b65af00be5f84c6d4ee45007643322713", "tree": "9a1159172287b7fd921c5dd9a34d4c6b970187a0", "parents": [ "b0b4ce38a535ed3de5ec6fdd4f3c34435a1c1d1e" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Mon Apr 19 11:43:10 2010 -0700" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Apr 30 20:52:41 2010 +0100" }, "message": "MIPS: Don\u0027t vmap things at address zero.\n\nIn the 64-bit kernel we use swapper_pg_dir for three different things.\n\n1) xuseg mappings for kernel threads.\n\n2) vmap mappings for all kernel-space accesses in xkseg.\n\n3) vmap mappings for kernel modules in ksseg (kseg2).\n\nDue to how the TLB refill handlers work, any mapping established in\nxkseg or ksseg will also establish a xuseg mapping that should never\nbe used by the kernel.\n\nIn order to be able to use exceptions to trap NULL pointer\ndereferences, we need to ensure that nothing is mapped at address\nzero. Since vmap mappings in xkseg are reflected in xuseg, this means\nwe need to ensure that there are no vmap mappings established at the\nstart of xkseg. So we move back VMALLOC_START to avoid establishing\nvmap mappings at the start of xkseg.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: http://patchwork.linux-mips.org/patch/1129/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "5808184f1b2fe06ef8a54a2b7fb1596d58098acf", "tree": "1ecb3addfdc3269cf55cffe112976e97a828736e", "parents": [ "8d9df29db273ab9a330828f4f4f6669d293a730a" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Mar 23 15:54:50 2010 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Apr 12 17:26:20 2010 +0100" }, "message": "MIPS: uasm: Add OR instruction.\n\nThis is needed for the fix of the M3 workaround.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "8d9df29db273ab9a330828f4f4f6669d293a730a", "tree": "7f5e9c87125d53fc2a512be150b01f6116918b3f", "parents": [ "9538ca636f2fa28ae1514327328e2869f0215981" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Mar 23 00:02:43 2010 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Apr 12 17:26:19 2010 +0100" }, "message": "MIPS: Sibyte: Apply M3 workaround only on affected chip types and versions.\n\nPreviously it was unconditionally used on all Sibyte family SOCs. The\nM3 bug has to be handled in the TLB exception handler which is extremly\nperformance sensitive, so this modification is expected to deliver around\n2-3% performance improvment. This is important as required changes to the\nM3 workaround will make it more costly.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "4fe67e44a0e0cb6281cbaaf603111187d87fce57", "tree": "d45b64fd7c9ffcfa65a79375a3b7d7d73e11b449", "parents": [ "524ef29cff593ab6635cda2a17b331bede58a396" ], "author": { "name": "Maxime Bizon", "email": "mbizon@freebox.fr", "time": "Sat Jan 30 18:34:56 2010 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Apr 12 17:26:18 2010 +0100" }, "message": "MIPS: BCM63xx: Fix typo in cpu-feature-overrides file.\n\nFix typo: CONFIG_BCMCPU_IS_63xx does not exist;\nCONFIG_BCM63XX_CPU_63xx is the valid config option.\n\nSigned-off-by: Maxime Bizon \u003cmbizon@freebox.fr\u003e\nTo: linux-mips@linux-mips.org\nCc: Maxime Bizon \u003cmbizon@freebox.fr\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/901/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "524ef29cff593ab6635cda2a17b331bede58a396", "tree": "d8d6a09c2f77e755f69f204e2467589491f5e36e", "parents": [ "97befcf4f0f42b1644b4b164ddc363685546edcd" ], "author": { "name": "Maxime Bizon", "email": "mbizon@freebox.fr", "time": "Sat Jan 30 18:34:55 2010 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Apr 12 17:26:18 2010 +0100" }, "message": "MIPS: BCM63xx: Add support for second uart.\n\nThe BCm63xx SOC has two uarts. Some boards use the second one for\nbluetooth. This patch changes platform device registration code to\nhandle this. Changes to the UART driver were already merged in\n6a2c7eabfd09ca7986bf96b8958a87ca041a19d8.\n\nSigned-off-by: Maxime Bizon \u003cmbizon@freebox.fr\u003e\nTo: linux-mips@linux-mips.org\nCc: Maxime Bizon \u003cmbizon@freebox.fr\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/900/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "d1b28758c6b46f6d04ef6017b51f614aecdb4abe", "tree": "93ccf0a33485c146687cd4e49d862d9403c05f6e", "parents": [ "b44c779ae0dedf3a6503c253954e570361b33f2b" ], "author": { "name": "Florian Fainelli", "email": "florian@openwrt.org", "time": "Mon Mar 01 23:36:32 2010 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Apr 12 17:26:16 2010 +0100" }, "message": "MIPS: BCM63xx: Fix BCM6338 and BCM6345 gpio count\n\nThe number of GPIOs on BCM6338 is 8, while BCM6345 has only 16 GPIOs\navailable.\n\nSigned-off-by: Florian Fainelli \u003cflorian@openwrt.org\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: http://patchwork.linux-mips.org/patch/1016/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "f1df323924e2fde14cbcd51209a8cbfc33e0c232", "tree": "a0f5a3c09e4a9e8ec3eb11bcc4e9d729b0af9dce", "parents": [ "d814c28ceca8f659c0012eaec8e21eee43710716" ], "author": { "name": "Wu Zhangjin", "email": "wuzhangjin@gmail.com", "time": "Sat Mar 13 12:34:15 2010 +0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Apr 12 17:26:15 2010 +0100" }, "message": "MIPS: Loongson-2F: Flush the branch target history in BTB and RAS\n\nAs per chapter 15 \"Errata: Issue of Out-of-order in loongson\"[1] to work\naround the Loongson 2F erratum we need to do:\n\n\"When switching from user mode to kernel mode, you should flush the\nbranch target history such as BTB and RAS.\"\n\n[1] Chinese version: http://www.loongson.cn/uploadfile/file/200808211\n[2] English version of chapter 15:\n http://groups.google.com.hk/group/loongson-dev/msg/e0d2e220958f10a6?dmode\u003dsource\n\nSigned-off-by: Wu Zhangjin \u003cwuzhangjin@gmail.com\u003e\nCc: linux-mips@linux-mips.org\nCc: Shinya Kuribayashi \u003cshinya.kuribayashi@necel.com\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/1066/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "d814c28ceca8f659c0012eaec8e21eee43710716", "tree": "add2c533054febaa51de021eb5b984e1b4818411", "parents": [ "c52d0d30aef84aa8893b34e5254716c8ab5c4472" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Thu Feb 18 16:13:05 2010 -0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Apr 12 17:26:15 2010 +0100" }, "message": "MIPS: Move signal trampolines off of the stack.\n\nThis is a follow on to the vdso patch.\n\nSince all processes now have signal trampolines permanently mapped, we\ncan use those instead of putting the trampoline on the stack and\ninvalidating the corresponding icache across all CPUs. We also get rid\nof a bunch of ICACHE_REFILLS_WORKAROUND_WAR code.\n\n[Ralf: GDB 7.1 which has the necessary modifications to allow backtracing\nover signal frames will supposedly be released tomorrow. The old signal\nframe format obsoleted by this patch exists in two variations, for sane\nprocessors and for those requiring ICACHE_REFILLS_WORKAROUND_WAR. So\nthere was never a GDB which did support backtracing over signal frames\non all MIPS systems. This convinved me this series should be applied and\npushed upstream as soon as possible.]\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: http://patchwork.linux-mips.org/patch/974/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "c52d0d30aef84aa8893b34e5254716c8ab5c4472", "tree": "0ba93eb7e305229ceb2ee04119dc7ab22b9fa33d", "parents": [ "58b9e2239fa63c7c470acb4a77e9da17e6a6fa4f" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Thu Feb 18 16:13:04 2010 -0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Apr 12 17:26:14 2010 +0100" }, "message": "MIPS: Preliminary VDSO\n\nThis is a preliminary patch to add a vdso to all user processes. Still\nmissing are ELF headers and .eh_frame information. But it is enough to\nallow us to move signal trampolines off of the stack. Note that emulation\nof branch delay slots in the FPU emulator still requires the stack.\n\nWe allocate a single page (the vdso) and write all possible signal\ntrampolines into it. The stack is moved down by one page and the vdso is\nmapped into this space.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: http://patchwork.linux-mips.org/patch/975/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "58b9e2239fa63c7c470acb4a77e9da17e6a6fa4f", "tree": "2f94c2146e2fe9adba511c4b66c3e3dd89d669b9", "parents": [ "847253b9483f713b3797877034e0940fd45ce375" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Thu Feb 18 16:13:03 2010 -0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Apr 12 17:26:14 2010 +0100" }, "message": "MIPS: Add SYSCALL to uasm.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: http://patchwork.linux-mips.org/patch/976/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "86f7d75eb7c43a54a7b37a2287787004f4310de6", "tree": "1a41fc905dfc6649279dc49c7a908224d1f826c6", "parents": [ "727c0075c80005e2012be113a91e5976abec4f9d" ], "author": { "name": "Florian Fainelli", "email": "florian@openwrt.org", "time": "Wed Mar 10 09:51:09 2010 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Apr 12 17:26:13 2010 +0100" }, "message": "MIPS: make CAC_ADDR and UNCAC_ADDR account for PHYS_OFFSET\n\nOn AR7, we already redefine PHYS_OFFSET to match the system specifities, it\nis however not sufficient when unsing dma_{map,unmap}_single, specifically\nin the ethernet driver, we must also adjust CAC_ADDR and UNCAC_ADDR for DMA\nto work correctly. This patch fixes the following issue, seen in cpmac_open:\n\nops[#1]:\nCpu 0\n$ 0 : 00000000 10008400 a0f5b120 00000000\n$ 4 : 94c59000 94270f64 00000020 00000010\n$ 8 : 00000010 94103ce0 0000000a 94c03400\n$12 : ffffffff 94c03408 94c03410 00000001\n$16 : a0f5ba20 00000041 94c592c0 94c59200\n$20 : 94c59000 000005ee 00002000 9438c8f0\n$24 : 00000010 00000000\n$28 : 94fac000 94fadd58 94390000 942724a8\nHi : 00000000\nLo : 00000001\nepc : 94272518 cpmac_open+0x208/0x3f8\n Not tainted\nra : 942724a8 cpmac_open+0x198/0x3f8\nStatus: 10008403 KERNEL EXL IE\nCause : 3080000c\nBadVA : 00000000\nPrId : 00018448 (MIPS 4KEc)\nModules linked in:\nProcess ifconfig (pid: 278, threadinfo\u003d94fac000, task\u003d94e79590, tls\u003d00000000)\nStack : 7f8da120 2ab05cb0 94c59000 943356f0 00000000 943d0000 94c59000 943356f0\n 94c59030 943d0000 943c27c0 94fade10 00000000 94fade20 94c59000 9428e5a4\n 00000000 94c59000 00000041 94289768 94c59000 00000041 00001002 00001043\n 00000000 9428d810 00000000 94fade10 7f8da4e8 9428e6b8 00000000 7f8da4a8\n 7f8da4e8 00008914 00000000 942f7f2c 00000000 00000008 00408000 00008913\n ...\nCall Trace:\n[\u003c94272518\u003e] cpmac_open+0x208/0x3f8\n[\u003c9428e5a4\u003e] dev_open+0x164/0x264\n[\u003c9428d810\u003e] dev_change_flags+0xd0/0x1bc\n[\u003c942f7f2c\u003e] devinet_ioctl+0x2d8/0x908\n[\u003c942771f8\u003e] sock_ioctl+0x29c/0x2fc\n[\u003c941a0fb4\u003e] vfs_ioctl+0x2c/0x7c\n[\u003c941a16ec\u003e] do_vfs_ioctl+0x5dc/0x630\n[\u003c941a1790\u003e] sys_ioctl+0x50/0x88\n[\u003c94101e10\u003e] stack_done+0x20/0x3c\n\nSigned-off-by: peter fuerst \u003cpost@pfrst.de\u003e\nSigned-off-by: Florian Fainelli \u003cflorian@openwrt.org\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: http://patchwork.linux-mips.org/patch/1050/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "d5d3102b9adec0a34eb5899324b62a4a3d34183e", "tree": "355f868f4c149ac63fbc70445e56c3ba2bde2916", "parents": [ "7ea4a6891b68fe60bf4eee41a7ef38d524b0aebd" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Mar 11 08:48:14 2010 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Apr 12 17:26:11 2010 +0100" }, "message": "MIPS: Fix elfcore.c build warning\n\nkernel/elfcore.c includes \u003clinux/elf.h\u003e which includes the \u003casm/elf.h\u003e. In\n\u003casm/elf.h\u003e, struct pt_regs is declared inside the parameter list of the\nelf_dump_regs function which causes a kernel build warning.\n\nFixed by adding a forward declaration of struct pt_regs.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "c948aca4f49d94b08c425f65acdaca1d679d6fa7", "tree": "67bd7e0857b1cfdd1d1af1431daafb730decf9dc", "parents": [ "0eddb519b9127c73d53db4bf3ec1d45b13f844d1" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Mar 08 19:38:13 2010 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Apr 12 17:26:08 2010 +0100" }, "message": "MIPS: Fix build breakage if CONFIG_DEBUG_FS is enabled.\n\nCaused by 38b7827fcdd660f591d645bd3ae6644456a4773c - no, cpu_local_* was\nnot unused.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\nCc: Christoph Lameter \u003ccl@linux-foundation.org\u003e\nAcked-by: David Daney \u003cddaney@caviumnetworks.com\u003e\n" }, { "commit": "f41b177157718abe9a93868bb76e47d4a6f3681d", "tree": "555d8608a2fe320483c8761dcb2e80cc37b5e822", "parents": [ "c7e67ac1f329fa28b6a411335787c786de618cba" ], "author": { "name": "FUJITA Tomonori", "email": "fujita.tomonori@lab.ntt.co.jp", "time": "Wed Mar 10 15:23:30 2010 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Mar 12 15:52:42 2010 -0800" }, "message": "pci-dma: add linux/pci-dma.h to linux/pci.h\n\nAll the architectures properly set NEED_DMA_MAP_STATE now so we can safely\nadd linux/pci-dma.h to linux/pci.h and remove the linux/pci-dma.h\ninclusion in arch\u0027s asm/pci.h\n\nSigned-off-by: FUJITA Tomonori \u003cfujita.tomonori@lab.ntt.co.jp\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\nCc: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "e1e02b329d64353e67af070516a9bd14caff8bb0", "tree": "67dad6845ad3175aeaad816a10edbcc459e9e1f9", "parents": [ "66ed5ef8b44374def8461a0a05d4afc34d4ad684" ], "author": { "name": "FUJITA Tomonori", "email": "fujita.tomonori@lab.ntt.co.jp", "time": "Wed Mar 10 15:23:25 2010 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Mar 12 15:52:41 2010 -0800" }, "message": "pci-dma: mips: use include/linux/pci-dma.h\n\nSigned-off-by: FUJITA Tomonori \u003cfujita.tomonori@lab.ntt.co.jp\u003e\nCc: Ralf Baechle \u003cralf@linux-mips.org\u003e\nCc: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "5cacdb4add1b1e50fe75edc50ebbb7bddd9cf5e7", "tree": "bd6595bb8c5c7e20ad01ed7ef766d873e5d26db3", "parents": [ "e28cbf22933d0c0ccaf3c4c27a1a263b41f73859" ], "author": { "name": "Christoph Hellwig", "email": "hch@lst.de", "time": "Wed Mar 10 15:21:21 2010 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Mar 12 15:52:32 2010 -0800" }, "message": "Add generic sys_olduname()\n\nAdd generic implementations of the old and really old uname system calls.\nNote that sh only implements sys_olduname but not sys_oldolduname, but I\u0027m\nnot going to bother with another ifdef for that special case.\n\nm32r implemented an old uname but never wired it up, so kill it, too.\n\nSigned-off-by: Christoph Hellwig \u003chch@lst.de\u003e\nCc: Ralf Baechle \u003cralf@linux-mips.org\u003e\nCc: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nCc: Paul Mundt \u003clethal@linux-sh.org\u003e\nCc: Jeff Dike \u003cjdike@addtoit.com\u003e\nCc: Hirokazu Takata \u003ctakata@linux-m32r.org\u003e\nCc: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: Ingo Molnar \u003cmingo@elte.hu\u003e\nCc: H. Peter Anvin \u003chpa@zytor.com\u003e\nCc: Al Viro \u003cviro@zeniv.linux.org.uk\u003e\nCc: Arnd Bergmann \u003carnd@arndb.de\u003e\nCc: Heiko Carstens \u003cheiko.carstens@de.ibm.com\u003e\nCc: Martin Schwidefsky \u003cschwidefsky@de.ibm.com\u003e\nCc: \"Luck, Tony\" \u003ctony.luck@intel.com\u003e\nCc: James Morris \u003cjmorris@namei.org\u003e\nCc: Andreas Schwab \u003cschwab@linux-m68k.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "e28cbf22933d0c0ccaf3c4c27a1a263b41f73859", "tree": "a93ff48cfd97766a23b2c4f3ea86fccfc9c51d3f", "parents": [ "baed7fc9b580bd3fb8252ff1d9b36eaf1f86b670" ], "author": { "name": "Christoph Hellwig", "email": "hch@lst.de", "time": "Wed Mar 10 15:21:19 2010 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Mar 12 15:52:32 2010 -0800" }, "message": "improve sys_newuname() for compat architectures\n\nOn an architecture that supports 32-bit compat we need to override the\nreported machine in uname with the 32-bit value. Instead of doing this\nseparately in every architecture introduce a COMPAT_UTS_MACHINE define in\n\u003casm/compat.h\u003e and apply it directly in sys_newuname().\n\nSigned-off-by: Christoph Hellwig \u003chch@lst.de\u003e\nCc: Ralf Baechle \u003cralf@linux-mips.org\u003e\nCc: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nCc: Paul Mundt \u003clethal@linux-sh.org\u003e\nCc: Jeff Dike \u003cjdike@addtoit.com\u003e\nCc: Hirokazu Takata \u003ctakata@linux-m32r.org\u003e\nCc: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: Ingo Molnar \u003cmingo@elte.hu\u003e\nCc: H. Peter Anvin \u003chpa@zytor.com\u003e\nCc: Al Viro \u003cviro@zeniv.linux.org.uk\u003e\nCc: Arnd Bergmann \u003carnd@arndb.de\u003e\nCc: Heiko Carstens \u003cheiko.carstens@de.ibm.com\u003e\nCc: Martin Schwidefsky \u003cschwidefsky@de.ibm.com\u003e\nCc: \"Luck, Tony\" \u003ctony.luck@intel.com\u003e\nCc: James Morris \u003cjmorris@namei.org\u003e\nCc: Andreas Schwab \u003cschwab@linux-m68k.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "baed7fc9b580bd3fb8252ff1d9b36eaf1f86b670", "tree": "38f23cd9888b92de3f73ed1f4ce48cd83e940e0e", "parents": [ "a4679373cf4ee0e7792dc56205365732b725c2c1" ], "author": { "name": "Christoph Hellwig", "email": "hch@lst.de", "time": "Wed Mar 10 15:21:18 2010 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Mar 12 15:52:32 2010 -0800" }, "message": "Add generic sys_ipc wrapper\n\nAdd a generic implementation of the ipc demultiplexer syscall. Except for\ns390 and sparc64 all implementations of the sys_ipc are nearly identical.\n\nThere are slight differences in the types of the parameters, where mips\nand powerpc as the only 64-bit architectures with sys_ipc use unsigned\nlong for the \"third\" argument as it gets casted to a pointer later, while\nit traditionally is an \"int\" like most other paramters. frv goes even\nfurther and uses unsigned long for all parameters execept for \"ptr\" which\nis a pointer type everywhere. The change from int to unsigned long for\n\"third\" and back to \"int\" for the others on frv should be fine due to the\nin-register calling conventions for syscalls (we already had a similar\nissue with the generic sys_ptrace), but I\u0027d prefer to have the arch\nmaintainers looks over this in details.\n\nExcept for that h8300, m68k and m68knommu lack an impplementation of the\nsemtimedop sub call which this patch adds, and various architectures have\ngets used - at least on i386 it seems superflous as the compat code on\nx86-64 and ia64 doesn\u0027t even bother to implement it.\n\n[akpm@linux-foundation.org: add sys_ipc to sys_ni.c]\nSigned-off-by: Christoph Hellwig \u003chch@lst.de\u003e\nCc: Ralf Baechle \u003cralf@linux-mips.org\u003e\nCc: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nCc: Paul Mundt \u003clethal@linux-sh.org\u003e\nCc: Jeff Dike \u003cjdike@addtoit.com\u003e\nCc: Hirokazu Takata \u003ctakata@linux-m32r.org\u003e\nCc: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: Ingo Molnar \u003cmingo@elte.hu\u003e\nReviewed-by: H. Peter Anvin \u003chpa@zytor.com\u003e\nCc: Al Viro \u003cviro@zeniv.linux.org.uk\u003e\nCc: Arnd Bergmann \u003carnd@arndb.de\u003e\nCc: Heiko Carstens \u003cheiko.carstens@de.ibm.com\u003e\nCc: Martin Schwidefsky \u003cschwidefsky@de.ibm.com\u003e\nCc: \"Luck, Tony\" \u003ctony.luck@intel.com\u003e\nCc: James Morris \u003cjmorris@namei.org\u003e\nCc: Andreas Schwab \u003cschwab@linux-m68k.org\u003e\nAcked-by: Jesper Nilsson \u003cjesper.nilsson@axis.com\u003e\nAcked-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\nAcked-by: David Howells \u003cdhowells@redhat.com\u003e\nAcked-by: Kyle McMartin \u003ckyle@mcmartin.ca\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "0a135ba14d71fb84c691a5386aff5049691fe6d7", "tree": "adb1de887dd6839d69d2fc16ffa2a10ff63298fa", "parents": [ "4850f524b2c4c8a4e9f8ef4dd9c7c4afde2f2b2c", "a29d8b8e2d811a24bbe49215a0f0c536b72ebc18" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Mar 03 07:34:18 2010 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Mar 03 07:34:18 2010 -0800" }, "message": "Merge branch \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tj/percpu\n\n* \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tj/percpu:\n percpu: add __percpu sparse annotations to what\u0027s left\n percpu: add __percpu sparse annotations to fs\n percpu: add __percpu sparse annotations to core kernel subsystems\n local_t: Remove leftover local.h\n this_cpu: Remove pageset_notifier\n this_cpu: Page allocator conversion\n percpu, x86: Generic inc / dec percpu instructions\n local_t: Move local.h include to ringbuffer.c and ring_buffer_benchmark.c\n module: Use this_cpu_xx to dynamically allocate counters\n local_t: Remove cpu_local_xx macros\n percpu: refactor the code in pcpu_[de]populate_chunk()\n percpu: remove compile warnings caused by __verify_pcpu_ptr()\n percpu: make accessors check for percpu pointer in sparse\n percpu: add __percpu for sparse.\n percpu: make access macros universal\n percpu: remove per_cpu__ prefix.\n" }, { "commit": "ced918eb748ce30b3aace549fd17540e40ffdca0", "tree": "f7c194d56e799508e090ef016bfc2dc0152a4244", "parents": [ "13dda80e48439b446d0bc9bab34b91484bc8f533" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Wed Feb 17 16:47:10 2010 +0000" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Tue Mar 02 10:28:38 2010 +0100" }, "message": "i8253: Convert i8253_lock to raw_spinlock\n\ni8253_lock needs to be a real spinlock in preempt-rt, i.e. it can\nnot be converted to a sleeping lock.\n\nConvert it to raw_spinlock and fix up all users.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nAcked-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\nAcked-by: Dmitry Torokhov \u003cdmitry.torokhov@gmail.com\u003e\nAcked-by: Takashi Iwai \u003ctiwai@suse.de\u003e\nCc: Jens Axboe \u003cjens.axboe@oracle.com\u003e\nLKML-Reference: \u003c20100217163751.030764372@linutronix.de\u003e\n\n" }, { "commit": "ac0f6f927db539e03e1f3f61bcd4ed57d5cde7a9", "tree": "816e5ac643b15c2050c64a7075f0f7e13d86ea09", "parents": [ "b1bf9368407ae7e89d8a005bb40beb70a41df539", "9f33be2c3a80bdc2cc08342dd77fac87652e0548" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Mar 01 09:15:15 2010 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Mar 01 09:15:15 2010 -0800" }, "message": "Merge branch \u0027for-linus\u0027 of master.kernel.org:/home/rmk/linux-2.6-arm\n\n* \u0027for-linus\u0027 of master.kernel.org:/home/rmk/linux-2.6-arm: (100 commits)\n ARM: Eliminate decompressor -Dstatic\u003d PIC hack\n ARM: 5958/1: ARM: U300: fix inverted clk round rate\n ARM: 5956/1: misplaced parentheses\n ARM: 5955/1: ep93xx: move timer defines into core.c and document\n ARM: 5954/1: ep93xx: move gpio interrupt support to gpio.c\n ARM: 5953/1: ep93xx: fix broken build of clock.c\n ARM: 5952/1: ARM: MM: Add ARM_L1_CACHE_SHIFT_6 for handle inside each ARCH Kconfig\n ARM: 5949/1: NUC900 add gpio virtual memory map\n ARM: 5948/1: Enable timer0 to time4 clock support for nuc910\n ARM: 5940/2: ARM: MMCI: remove custom DBG macro and printk\n ARM: make_coherent(): fix problems with highpte, part 2\n MM: Pass a PTE pointer to update_mmu_cache() rather than the PTE itself\n ARM: 5945/1: ep93xx: include correct irq.h in core.c\n ARM: 5933/1: amba-pl011: support hardware flow control\n ARM: 5930/1: Add PKMAP area description to memory.txt.\n ARM: 5929/1: Add checks to detect overlap of memory regions.\n ARM: 5928/1: Change type of VMALLOC_END to unsigned long.\n ARM: 5927/1: Make delimiters of DMA area globally visibly.\n ARM: 5926/1: Add \"Virtual kernel memory...\" printout.\n ARM: 5920/1: OMAP4: Enable L2 Cache\n ...\n\nFix up trivial conflict in arch/arm/mach-mx25/clock.c\n" }, { "commit": "d891a5399242579857701c2b1185b64d7bf7936f", "tree": "a41fb063c1bc473a96f24ae11e70b555b0825420", "parents": [ "8190471087b59ff63a8db125953ae612b7a8b8b5" ], "author": { "name": "Yoichi Yuasa", "email": "yuasa@linux-mips.org", "time": "Sat Feb 20 21:20:34 2010 +0900" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:45 2010 +0100" }, "message": "MIPS: ARC: Cleanup unused definitions from sgialib.h\n\nSigned-off-by: Yoichi Yuasa \u003cyuasa@linux-mips.org\u003e\nCc: linux-mips \u003clinux-mips@linux-mips.org\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/979/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "11b897cf84c37e6522db914793677e933ef311fb", "tree": "b9d69cea86b2c1673f30332ff9b3944dc00bfc9b", "parents": [ "b9b37787d24cca9fbd63f767663e9439fa69aa22" ], "author": { "name": "Manuel Lauss", "email": "manuel.lauss@googlemail.com", "time": "Wed Feb 24 17:40:21 2010 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:43 2010 +0100" }, "message": "MIPS: Alchemy: use 36bit addresses for PCMCIA resources.\n\nOn Alchemy the PCMCIA area lies at the end of the chips 36bit system bus\narea. Currently, addresses at the far end of the 32bit area are assumed\nto belong to the PCMCIA area and fixed up to the real 36bit address before\nbeing passed to ioremap().\n\nA previous commit enabled 64 bit physical size for the resource datatype on\nAlchemy and this allows to use the correct 36bit addresses when registering\nthe PCMCIA sockets.\n\nThis patch removes the 32-to-36bit address fixup and registers the Alchemy\ndemo board pcmcia socket with the correct 36bit physical addresses.\n\nTested on DB1200, with a CF card (ide-cs driver) and a 3c589 PCMCIA ethernet\ncard.\n\nSigned-off-by: Manuel Lauss \u003cmanuel.lauss@gmail.com\u003e\nTo: Linux-MIPS \u003clinux-mips@linux-mips.org\u003e\nCc: Manuel Lauss \u003cmanuel.lauss@gmail.com\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/994/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "500c2e1fdbcc2b273bd4c695a9b8ac8196f61614", "tree": "f24c80f609a739beed194fd5c66abf9bc48ce0d6", "parents": [ "e275ed5ee94b358964a0dae1c8b49f0bff260b60" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Thu Feb 04 11:31:49 2010 -0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:42 2010 +0100" }, "message": "MIPS: Optimize spinlocks.\n\nThe current locking mechanism uses a ll/sc sequence to release a\nspinlock. This is slower than a wmb() followed by a store to unlock.\n\nThe branching forward to .subsection 2 on sc failure slows down the\ncontended case. So we get rid of that part too.\n\nSince we are now working on naturally aligned u16 values, we can get\nrid of a masking operation as the LHU already does the right thing.\nThe ANDI are reversed for better scheduling on multi-issue CPUs\n\nOn a 12 CPU 750MHz Octeon cn5750 this patch improves ipv4 UDP packet\nforwarding rates from 3.58*10^6 PPS to 3.99*10^6 PPS, or about 11%.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: http://patchwork.linux-mips.org/patch/937/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "896508705561bea24656680cdaf3b4095c4d7473", "tree": "c02b21f167c46e6b20c60f74810121829e65a56e", "parents": [ "598c5abad7f3e162a01c87a480f8d2cd57643acb" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:38 2010 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:38 2010 +0100" }, "message": "MIPS: i8259: Convert IRQ controller lock to raw spinlock.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "4a8a738de637dc7141de5228d2d722573a329b95", "tree": "20abde39e4697d5943dd83126ead21a9f4f8de85", "parents": [ "559e25a5e3efe60a22b7f96ea4ad2eb09d996e97" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:30 2010 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:30 2010 +0100" }, "message": "MIPS: Make various locks static.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "d007f991a82ed159979b7662a4ca20e978221cdb", "tree": "580c935bb8dd838bd2c8151ad6e067610b6a7398", "parents": [ "7b012cee6173cef8598a4cf27fe80b4430e1ed7f" ], "author": { "name": "Yoichi Yuasa", "email": "yuasa@linux-mips.org", "time": "Fri Feb 12 21:35:04 2010 +0900" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:27 2010 +0100" }, "message": "MIPS: Use generic ucontext.h\n\nSigned-off-by: Yoichi Yuasa \u003cyuasa@linux-mips.org\u003e\nCc: linux-mips \u003clinux-mips@linux-mips.org\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/959/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "7b012cee6173cef8598a4cf27fe80b4430e1ed7f", "tree": "151d7b1cefb8c4024ae7f5edfb191f86ad99beb6", "parents": [ "f51e5a07728d33b7ad59a84d1a7a0a34d4f58765" ], "author": { "name": "Yoichi Yuasa", "email": "yuasa@linux-mips.org", "time": "Fri Feb 12 21:33:56 2010 +0900" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:27 2010 +0100" }, "message": "MIPS: Use generic serial.h\n\nSigned-off-by: Yoichi Yuasa \u003cyuasa@linux-mips.org\u003e\nCc: linux-mips \u003clinux-mips@linux-mips.org\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/960/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "f51e5a07728d33b7ad59a84d1a7a0a34d4f58765", "tree": "041cb7a8a2a244e2b91d8035e1d8b33af837c64a", "parents": [ "1a6e8963e07f126a7fa3e9b446f86205cd4e81fe" ], "author": { "name": "Yoichi Yuasa", "email": "yuasa@linux-mips.org", "time": "Fri Feb 12 21:29:14 2010 +0900" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:27 2010 +0100" }, "message": "MIPS: Use generic parport.h\n\nSigned-off-by: Yoichi Yuasa \u003cyuasa@linux-mips.org\u003e\nCc: linux-mips \u003clinux-mips@linux-mips.org\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/958/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "1a6e8963e07f126a7fa3e9b446f86205cd4e81fe", "tree": "61acc6c2c59310994dde1d296fc9ebb47e3e6a90", "parents": [ "27a5bd6457c8ce38151250530152e15f76b697a8" ], "author": { "name": "Yoichi Yuasa", "email": "yuasa@linux-mips.org", "time": "Fri Feb 12 21:27:59 2010 +0900" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:27 2010 +0100" }, "message": "MIPS: Use generic current.h\n\nSigned-off-by: Yoichi Yuasa \u003cyuasa@linux-mips.org\u003e\nCc: linux-mips \u003clinux-mips@linux-mips.org\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/957/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "27a5bd6457c8ce38151250530152e15f76b697a8", "tree": "97c50c1773a1ebe7604b8a8c4f046718941fc504", "parents": [ "6f329468f3086e9d8f3832930fdb09ab3769176b" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Wed Feb 10 15:12:49 2010 -0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:26 2010 +0100" }, "message": "MIPS: Enable Read Inhibit/eXecute Inhibit for Octeon+ CPUs\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: http://patchwork.linux-mips.org/patch/955/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "6f329468f3086e9d8f3832930fdb09ab3769176b", "tree": "d77b274399cf101fba59b0de01fd9491b4e28fee", "parents": [ "6dd9344cfc41bcc60a01cdc828cb278be7a10e01" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Wed Feb 10 15:12:48 2010 -0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:26 2010 +0100" }, "message": "MIPS: Give Octeon+ CPUs their own cputype.\n\nThis allows us to treat them differently at runtime.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: http://patchwork.linux-mips.org/patch/951/\nPatchwork: http://patchwork.linux-mips.org/patch/987/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "6dd9344cfc41bcc60a01cdc828cb278be7a10e01", "tree": "9c62d563eba8f3acfd1c826a63e6999261b06f5a", "parents": [ "32546f38fab839eee6f62b3f06c2774eade4188a" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Wed Feb 10 15:12:47 2010 -0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:26 2010 +0100" }, "message": "MIPS: Implement Read Inhibit/eXecute Inhibit\n\nThe SmartMIPS ASE specifies how Read Inhibit (RI) and eXecute Inhibit\n(XI) bits in the page tables work. The upper two bits of EntryLo{0,1}\nare RI and XI when the feature is enabled in the PageGrain register.\nSmartMIPS only covers 32-bit systems. Cavium Octeon+ extends this to\n64-bit systems by continuing to place the RI and XI bits in the top of\nEntryLo even when EntryLo is 64-bits wide.\n\nBecause we need to carry the RI and XI bits in the PTE, the layout of\nthe PTE is changed. There is a two instruction overhead in the TLB\nrefill hot path to get the EntryLo bits into the proper position.\nAlso the TLB load exception has to probe the TLB to check if RI or XI\ncaused the exception.\n\nAlso of note is that the layout of the PTE bits is done at compile and\nruntime rather than statically. In the 32-bit case this allows for\nthe same number of PFN bits as before the patch as the _PAGE_HUGE is\nnot supported in 32-bit kernels (we have _PAGE_NO_EXEC and\n_PAGE_NO_READ instead of _PAGE_READ and _PAGE_HUGE).\n\nThe patch is tested on Cavium Octeon+, but should also work on 32-bit\nsystems with the Smart-MIPS ASE.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: http://patchwork.linux-mips.org/patch/952/\nPatchwork: http://patchwork.linux-mips.org/patch/956/\nPatchwork: http://patchwork.linux-mips.org/patch/962/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "32546f38fab839eee6f62b3f06c2774eade4188a", "tree": "582cb9fb18c8e741d24a4a27d9c2dee46bfd977f", "parents": [ "9fe2e9d6f5390d7151a0b9d8c100f0da26eaa2b7" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Wed Feb 10 15:12:46 2010 -0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:25 2010 +0100" }, "message": "MIPS: Add TLBR and ROTR to uasm.\n\nThe soon to follow Read Inhibit/eXecute Inhibit patch needs TLBR and\nROTR support in uasm. We also add a UASM_i_ROTR macro.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: http://patchwork.linux-mips.org/patch/953/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "9fe2e9d6f5390d7151a0b9d8c100f0da26eaa2b7", "tree": "1585654ec66e83e2d56c833404ac4bc7fa3ded42", "parents": [ "9b8c38917b8e083a6343bb5a0c6bbaea78ebff7a" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Wed Feb 10 15:12:45 2010 -0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:25 2010 +0100" }, "message": "MIPS: Add accessor functions and bit definitions for c0_PageGrain\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: http://patchwork.linux-mips.org/patch/950/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "ab4ba291683d07038c7ddf1eec191d3d09e1f468", "tree": "267b4cefdfe33510ffe9eb8ea15de8ef71bc089d", "parents": [ "7084338eb8eb0cc021ba86c340157bad397f3f0b" ], "author": { "name": "Yoichi Yuasa", "email": "yuasa@linux-mips.org", "time": "Tue Feb 02 18:40:04 2010 +0900" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:22 2010 +0100" }, "message": "MIPS: TXx9: Remove forced serial console setting\n\nIt is not always used, even if it is available.\n\nSigned-off-by: Yoichi Yuasa \u003cyuasa@linux-mips.org\u003e\nCc: linux-mips \u003clinux-mips@linux-mips.org\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/933/\nAcked-by: Atsushi Nemoto \u003canemo@mba.ocn.ne.jp\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "ae7cbef5e5789e2ee6855222a3b83eb94591ef0b", "tree": "5c184ac0807eac7618c2d5717ffefcf510ce7f71", "parents": [ "c63d0cb5feedbc2cc456b6ea2105c15b563217cf" ], "author": { "name": "Yoichi Yuasa", "email": "yuasa@linux-mips.org", "time": "Mon Feb 01 22:05:57 2010 +0900" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:21 2010 +0100" }, "message": "MIPS: Alchemy: Remove prom_getcmdline()\n\nSigned-off-by: Yoichi Yuasa \u003cyuasa@linux-mips.org\u003e\nCc: linux-mips \u003clinux-mips@linux-mips.org\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/927/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "874fd3b5acc20f2a464409045aef3b2288069787", "tree": "667316d08ee5b5b4be99e75dca7bcf9ff315503a", "parents": [ "3b839070f11295735ce8d9ef580c5eb23417aabf" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Thu Jan 28 16:52:12 2010 -0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:20 2010 +0100" }, "message": "MIPS: Allow the auxv\u0027s elf_platform entry to be set.\n\nThe userspace runtime linker uses the elf_platform to find the libraries\noptimized for the current CPU archecture variant. First we need to allow it\nto be set to something other than NULL. Follow-on patches will set some\nvalues for specific CPUs.\n\nGLIBC already does the right thing. The kernel just needs to supply good\ndata.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: http://patchwork.linux-mips.org/patch/891/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "3b839070f11295735ce8d9ef580c5eb23417aabf", "tree": "f5a466669cea7e172d260c319601b9e1522d01ac", "parents": [ "92bbe1b988d3d6fa6348e3e376ff6d27e0712147" ], "author": { "name": "Manuel Lauss", "email": "manuel.lauss@googlemail.com", "time": "Wed Oct 14 09:38:06 2009 +0200" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:19 2010 +0100" }, "message": "MMC: AU1xMMC: Allow platforms to disable host capabilities\n\nAlthough the hardware supports a 4/8bit SD interface and the driver\nunconditionally advertises all hardware caps to the MMC core, not all\ndatalines may actually be wired up. This patch introduces another\nfield to au1xmmc platform data allowing platforms to disable certain\nadvanced host controller features.\n\nSigned-off-by: Manuel Lauss \u003cmanuel.lauss@gmail.com\u003e\nTo: linux-mmc@vger.kernel.org\nCC: Linux-MIPS \u003clinux-mips@linux-mips.org\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/460/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "3482d713a91befb8c96722cb8d55aed36c212d9e", "tree": "e5b8f0e779fb64e9952765694ceaaf572aa6a0fa", "parents": [ "fcf6735e9cf08343bef9ff43205d91ef102af52f" ], "author": { "name": "Florian Fainelli", "email": "florian@openwrt.org", "time": "Thu Jan 28 15:21:24 2010 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:19 2010 +0100" }, "message": "MIPS: Move arch/mips/mm/uasm.h to arch/mips/include/asm/uasm.h\n\nSigned-off-by: Florian Fainelli \u003cflorian@openwrt.org\u003e\nTo: linux-mips@linux-mips.org\nTo: David Daney \u003cddaney@caviumnetworks.com\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/887/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "60ec6571c5072cdea9e518d1dac8147b85ca93a2", "tree": "7543987848f6c00467bb5adea4ccfe096faf8835", "parents": [ "fc48c41af81b953578a54f80ad07d2f1efa81378" ], "author": { "name": "pascal@pabr.org", "email": "pascal@pabr.org", "time": "Sun Jan 03 13:39:12 2010 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:17 2010 +0100" }, "message": "MIPS: Support 36-bit iomem on 32-bit Au1x00\n\nI believe these changes are needed on Alchemy SoCs in order to\nuse iomem above 4G with the usual platform_device machinery:\n\n- Set CONFIG_ARCH_PHYS_ADDR_T_64BIT to make resource_size_t 64-bit.\n- Increase IOMEM_RESOURCE_END so that platforms can register resources.\n\nTo: linux-mips@linux-mips.org\nPatchwork: http://patchwork.linux-mips.org/patch/814/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "780019ddf02f214ad61e641b57b8ac30c837e2a7", "tree": "2d0a01efc4d508057bcfaa7b3df5b3e490c249ed", "parents": [ "5f3c909881d5deebb9a3ddc836a15937e76daefc" ], "author": { "name": "Florian Fainelli", "email": "florian@openwrt.org", "time": "Wed Jan 27 09:10:06 2010 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:16 2010 +0100" }, "message": "MIPS: AR7: Implement clock API\n\nThis patch makes the ar7 clock code implement the Linux clk API. Drivers\nusing the various clocks available in the SoC are updated accordingly.\n\nSigned-off-by: Florian Fainelli \u003cflorian@openwrt.org\u003e\nAcked-by: Wim Van Sebroeck \u003cwim@iguana.be\u003e\nTo: linux-mips@linux-mips.org\nCc: Wim Van Sebroeck \u003cwim@iguana.be\u003e\nCc: netdev@vger.kernel.org\nCc: David Miller \u003cdavem@davemloft.net\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/881/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "5f3c909881d5deebb9a3ddc836a15937e76daefc", "tree": "5306ae518c1da71bdba1814e49e75ad7cd6c2736", "parents": [ "69b427cd23b6f637763bf49e3e166c1236313f69" ], "author": { "name": "Florian Fainelli", "email": "florian@openwrt.org", "time": "Sun Jan 03 21:16:51 2010 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:16 2010 +0100" }, "message": "MIPS: AR7: Implement gpiolib\n\nThis patch implements gpiolib for the AR7 SoC.\n\nSigned-off-by: Florian Fainelli \u003cflorian@openwrt.org\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: http://patchwork.linux-mips.org/patch/816/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "69b427cd23b6f637763bf49e3e166c1236313f69", "tree": "7a174339d867e6e1e72de31ba13f8f6f086eb3f3", "parents": [ "dac2965c434b22b5f8acd5634b842cf8a77a06b3" ], "author": { "name": "Yoichi Yuasa", "email": "yuasa@linux-mips.org", "time": "Tue Jan 26 18:02:58 2010 +0900" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:15 2010 +0100" }, "message": "MIPS: msp71xx: remove unused prom_getcmdline()\n\nSigned-off-by: Yoichi Yuasa \u003cyuasa@linux-mips.org\u003e\nCc: linux-mips \u003clinux-mips@linux-mips.org\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/868/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "e0e53dee69e07e9446eb16ceabd55a1116611696", "tree": "0f46618d019bf984e86c84c2bfd31c60869ba56d", "parents": [ "2fe062608086f9b74a80f16272c5a59a3e05722f" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:14 2010 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:14 2010 +0100" }, "message": "MIPS: Nuke trailing blank lines\n\nRecent git versions now warn about those and they\u0027ve always been a bit of\nan annoyance.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "2fe062608086f9b74a80f16272c5a59a3e05722f", "tree": "d6ee7a2a40522345829b1aca0bc128d125da7d19", "parents": [ "1b362e3e350f72c6cb4b3346f6ba92a529082a09" ], "author": { "name": "Roel Kluin", "email": "roel.kluin@gmail.com", "time": "Wed Jan 20 00:59:27 2010 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:14 2010 +0100" }, "message": "MIPS: Cleanup switches with cases that can be merged\n\nSigned-off-by: Roel Kluin \u003croel.kluin@gmail.com\u003e\nTo: linux-mips@linux-mips.org\nTo: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nTo: LKML \u003clinux-kernel@vger.kernel.org\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/860/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "1b362e3e350f72c6cb4b3346f6ba92a529082a09", "tree": "de172b4853b1aaa6684e5b7afed679c88d8ab655", "parents": [ "2a880986d899f556f5a327bc77cc8760d5bb9c64" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Fri Jan 22 14:41:15 2010 -0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:13 2010 +0100" }, "message": "MIPS: Decode c0_config4 for large TLBs.\n\nFor processors that have more than 64 TLBs, we need to decode both\nconfig1 and config4 to determine the total number TLBs.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: http://patchwork.linux-mips.org/patch/866/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "f868ba29723be46e0981226d7455090d515b08ef", "tree": "77b0fde68563ab8b8b458839608577223d787d81", "parents": [ "9df7d1647fdd729c5bf3f087ae69d07fecf60bdd" ], "author": { "name": "Florian Fainelli", "email": "ffainelli@freebox.fr", "time": "Wed Dec 16 11:29:06 2009 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:12 2010 +0100" }, "message": "MIPS: add readl/write_be accessors\n\nMIPS currently lacks the readl_be and writel_be accessors\nwhich are required by BCM63xx for OHCI and EHCI support.\nLet\u0027s define them globally for MIPS. This also fixes the\ncompilation of the bcm63xx defconfig against USB.\n\nSigned-off-by: Florian Fainelli \u003cffainelli@freebox.fr\u003e\nCc: Geert Uytterhoeven \u003cgeert@linux-m68k.org\u003e\nCc: Thomas Bogendoerfer \u003ctsbogend@alpha.franken.de\u003e\nCc: linux-mips@linux-mips.org\nCc: Maxime Bizon \u003cmbizon@freebox.fr\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/793/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "f7a904dffe30a02636053d8022498ced7e44d31c", "tree": "71130b3b2cf44bafe05d125ee4ea54d771b2ce67", "parents": [ "50549bda2d47f419758dac9bc72e2b0eb9077d83" ], "author": { "name": "Wu Zhangjin", "email": "wuzhangjin@gmail.com", "time": "Mon Jan 04 17:16:51 2010 +0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:12 2010 +0100" }, "message": "MIPS: Loongson: Change the Email address of Wu Zhangjin\n\nCurrently wuzj@lemote.com is not usable; change it to wuzhangjin@gmail.com.\n\nSigned-off-by: Wu Zhangjin \u003cwuzhangjin@gmail.com\u003e\nCc: linux-mips@linux-mips.org\nCc: yanh@lemote.com\nCc: huhb@lemote.com\nCc: zhangfx@lemote.com\nPatchwork: http://patchwork.linux-mips.org/patch/829/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "eb11df472d8491fcb28534b59017e1b5465997fa", "tree": "019fe0166af774fffe0227b42546463a326e144e", "parents": [ "97e6a89634befaf5bd66d3044d36961c887cd98c" ], "author": { "name": "Wu Zhangjin", "email": "wuzhangjin@gmail.com", "time": "Mon Jan 04 17:16:48 2010 +0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:11 2010 +0100" }, "message": "MIPS: Loongson: Cleanup of the environment variables\n\nChanges:\n\n\to Move bus_clock into prom_init_env()\n\to Initialize the cpu_clock_freq to the default values for the\n\tcorrespoding processor revisions if no such environment variable\n\tpassed by BIOS/Bootloader.\n\nSigned-off-by: Wu Zhangjin \u003cwuzhangjin@gmail.com\u003e\nCc: linux-mips@linux-mips.org\nCc: yanh@lemote.com\nCc: huhb@lemote.com\nCc: zhangfx@lemote.com\nPatchwork: http://patchwork.linux-mips.org/patch/826/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "6b07d38aaa520cee922fadfeaf90c97faf217045", "tree": "3d68d10c95ed7d87fd1692448e3903b801b40e94", "parents": [ "f252ffd50c97dae87b45f1dbad24f71358ccfbd6" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Fri Jan 08 17:17:44 2010 -0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:06 2010 +0100" }, "message": "MIPS: Octeon: Use optimized memory barrier primitives.\n\nIn order to achieve correct synchronization semantics, the Octeon port\nhad defined CONFIG_WEAK_REORDERING_BEYOND_LLSC. This resulted in code\nthat looks like:\n\n sync\n ll ...\n .\n .\n .\n sc ...\n .\n .\n sync\n\nThe second SYNC was redundant, but harmless.\n\nOcteon has a SYNCW instruction that acts as a write-memory-barrier\n(due to an erratum in some parts two SYNCW are used). It is much\nfaster than SYNC because it imposes ordering on the writes, but\ndoesn\u0027t otherwise stall the execution pipeline. On Octeon, SYNC\nstalls execution until all preceeding writes are committed to the\ncoherent memory system.\n\nUsing:\n\n syncw;syncw\n ll\n .\n .\n .\n sc\n .\n .\n\nHas identical semantics to the first sequence, but is much faster.\nThe SYNCW orders the writes, and the SC will not complete successfully\nuntil the write is committed to the coherent memory system. So at the\nend all preceeding writes have been committed. Since Octeon does not\ndo speculative reads, this functions as a full barrier.\n\nThe patch removes CONFIG_WEAK_REORDERING_BEYOND_LLSC, and substitutes\nSYNCW for SYNC in write-memory-barriers.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: http://patchwork.linux-mips.org/patch/850/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "f252ffd50c97dae87b45f1dbad24f71358ccfbd6", "tree": "c057fc7c3a819152603b286f935fb367fc48ae73", "parents": [ "ec5380c768864c7afd92aa886dd4bb6d38497a01" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Fri Jan 08 17:17:43 2010 -0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:06 2010 +0100" }, "message": "MIPS: New macro smp_mb__before_llsc.\n\nReplace some instances of smp_llsc_mb() with a new macro\nsmp_mb__before_llsc(). It is used before ll/sc sequences that are\ndocumented as needing write barrier semantics.\n\nThe default implementation of smp_mb__before_llsc() is just smp_llsc_mb(),\nso there are no changes in semantics.\n\nAlso simplify definition of smp_mb(), smp_rmb(), and smp_wmb() to be just\nbarrier() in the non-SMP case.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: http://patchwork.linux-mips.org/patch/851/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "ec5380c768864c7afd92aa886dd4bb6d38497a01", "tree": "c4a744d6aad44bf1c1c0268f647b168fe0e25135", "parents": [ "d95770544604299402e481771a964b0f10d46978" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Thu Jan 07 14:33:30 2010 -0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:05 2010 +0100" }, "message": "MIPS: Remove unused macros from barrier.h\n\nThe smp_llsc_rmb() and smp_llsc_wmb() macros are not used in the tree,\nremove them.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: http://patchwork.linux-mips.org/patch/848/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "f41c3c1b3ed53440b37445712f8e1048a39d7001", "tree": "c737d70385a32aea9de6a2d1e3b9a088c4bbe63f", "parents": [ "d38760ccdf879a8648be53488227bf7fe597792d" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Thu Jan 07 13:23:41 2010 -0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:04 2010 +0100" }, "message": "MIPS: Octeon: Add I2C platform device.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nTo: linux-mips@linux-mips.org\nTo: linux-i2c@vger.kernel.org\nTo: ben-linux@fluff.org\nTo: khali@linux-fr.org\nCc: Rade Bozic \u003crade.bozic.ext@nsn.com\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/847/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "d38760ccdf879a8648be53488227bf7fe597792d", "tree": "133bc52d621608d7a3b8bcd664f03b880dad15c4", "parents": [ "32fd6901a6d8d19f94e4de6be4e4b552ab078620" ], "author": { "name": "Robert P. J. Day", "email": "rpjday@crashcourse.ca", "time": "Thu Dec 31 15:39:00 2009 -0500" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:04 2010 +0100" }, "message": "MIPS: Simplify param.h by using \u003casm-generic/param.h\u003e\n\nSigned-off-by: Robert P. J. Day \u003crpjday@crashcourse.ca\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: http://patchwork.linux-mips.org/patch/810/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "325f8a0a31df567dbafafc48f8e60f3c1f101a46", "tree": "b36383f4d483ecc6d057cdd41ef50b6403e89b9c", "parents": [ "ef6c1fd662d18c0e2ed92825c8837e94b5ec3a1f" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Fri Dec 04 13:52:36 2009 -0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:03 2010 +0100" }, "message": "MIPS: Two-level pagetables for 64-bit kernels with 64KB pages.\n\nFor 64-bit kernels with 64KB pages and two level page tables, there are\n42 bits worth of virtual address space This is larger than the 40 bits of\nvirtual address space obtained with the default 4KB Page size and three\nlevels, so there are no draw backs for using two level tables with this\nconfiguration.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nCc: linux-mips@linux-mips.org\nPatchwork: http://patchwork.linux-mips.org/patch/761/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "5d400f5c59df3ed2c3682a7409c8e81a7c4e650c", "tree": "c501fe5a419532d10cc39dae3f1ce044716e25b4", "parents": [ "70f82f2c59be86fad915a2ee62673fe1aad6c2bd" ], "author": { "name": "Manuel Lauss", "email": "manuel.lauss@googlemail.com", "time": "Mon Nov 23 20:40:01 2009 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:02 2010 +0100" }, "message": "MIPS: Alchemy: Only build AU1000 INTC code for compatible cpus\n\nUse the GPIO config symbol to only build Au1000 interrupt code on chips with\ncompatible hw.\n\nSigned-off-by: Manuel Lauss \u003cmanuel.lauss@gmail.com\u003e\nCc: linux-mips@linux-mips.org\nPatchwork: http://patchwork.linux-mips.org/patch/670/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "70f82f2c59be86fad915a2ee62673fe1aad6c2bd", "tree": "089b089e5962fbc96dd30651889b8a42a04abc6c", "parents": [ "bd2302c220566cffd0756e1ac5f65705f9e3d8e7" ], "author": { "name": "Manuel Lauss", "email": "mlau@msc-ge.com", "time": "Mon Nov 23 20:40:00 2009 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:02 2010 +0100" }, "message": "MIPS: Alchemy: use runtime cpu detection in GPIO code.\n\nRemove the cpu subtype cpp macros in favor of runtime detection,\nto improve compile coverage of the alchemy common code.\n(Increases kernel size by 700 bytes).\n\nSigned-off-by: Manuel Lauss \u003cmanuel.lauss@gmail.com\u003e\nCc: linux-mips@linux-mips.org\nPatchwork: http://patchwork.linux-mips.org/patch/699/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "66f75ccb856304c190fde9c26e651c2b754e3e72", "tree": "f63f8fe9362fc9805b73f9146a20457d1ceddff0", "parents": [ "cf6e47e03239059bcf2942b1b3242e835231ab75" ], "author": { "name": "Florian Fainelli", "email": "florian@openwrt.org", "time": "Tue Nov 10 01:13:30 2009 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:01 2010 +0100" }, "message": "MIPS: Alchemy: Add au1000-eth platform device\n\nThis patch makes the board code register the au1000-eth platform device. The\nau1000-eth platform data can be overriden with the au1xxx_override_eth_cfg\nfunction like it has to be done for the Bosporus board which uses a\ndifferent MAC/PHY setup.\n\nSigned-off-by: Florian Fainelli \u003cflorian@openwrt.org\u003e\nCc: David Miller \u003cdavem@davemloft.net\u003e\nCc: linux-mips@linux-mips.org\nCc: netdev@vger.kernel.org\nPatchwork: http://patchwork.linux-mips.org/patch/618/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "63323ec54a7e922a232c82070727e44eb1a5b43c", "tree": "4f78c66c8db7fdaded28a3eaf76f196bd1c59753", "parents": [ "206aa6cdadad8bbedee5649f1346fe47e922a039" ], "author": { "name": "Manuel Lauss", "email": "manuel.lauss@googlemail.com", "time": "Mon Nov 02 21:21:43 2009 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:53:00 2010 +0100" }, "message": "MIPS: Alchemy: Extended DB1200 board support.\n\nCreate own directory for DB1200 code and update it with new features.\n\n- SPI support:\n - tmp121 temperature sensor\n - SPI flash on DB1200\n- I2C support\n - NE1619 sensor\n - AT24 eeprom\n- I2C/SPI can be selected at boot time via switch S6.8\n- Carddetect IRQs for SD cards.\n- gen_nand based NAND support.\n- hexleds count sleep/wake transitions.\n\nSigned-off-by: Manuel Lauss \u003cmanuel.lauss@gmail.com\u003e\nCc: Linux-MIPS \u003clinux-mips@linux-mips.org\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "66a1d9baf4962defb3fc41439e3a22e752182f9f", "tree": "d60f67828c1a867427ea3a8450906632be866a2e", "parents": [ "b6e6d120c8dd9c9cd888645b01299e2a55d873a4" ], "author": { "name": "Manuel Lauss", "email": "manuel.lauss@googlemail.com", "time": "Thu Oct 15 19:32:01 2009 +0200" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:52:55 2010 +0100" }, "message": "MIPS: Alchemy: remove unused SYS area structure\n\nNothing in-tree uses it, so get rid of it.\n\nSigned-off-by: Manuel Lauss \u003cmanuel.lauss@gmail.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "b6e6d120c8dd9c9cd888645b01299e2a55d873a4", "tree": "a4d5944980e61ec2c6819131cbb8269e340e58c1", "parents": [ "8402a1588a4f63465079e98481dd83d1d9cc9a98" ], "author": { "name": "Manuel Lauss", "email": "manuel.lauss@googlemail.com", "time": "Thu Oct 15 19:07:34 2009 +0200" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:52:55 2010 +0100" }, "message": "MIPS: Alchemy: get rid of superfluous UART definitions\n\nRemove unused uart bit definitions and base macros.\n\nSigned-off-by: Manuel Lauss \u003cmanuel.lauss@gmail.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "8402a1588a4f63465079e98481dd83d1d9cc9a98", "tree": "1ace3c45421fe4b8d29762fcc67bd09064197f18", "parents": [ "963accbc82a0912b39de39d59e2fd6741db3aa4b" ], "author": { "name": "Manuel Lauss", "email": "manuel.lauss@googlemail.com", "time": "Thu Oct 15 18:49:27 2009 +0200" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:52:55 2010 +0100" }, "message": "MIPS: Alchemy: prom_putchar is board dependent\n\nThis patch replaces the general alchemy prom_putchar() implementation\nin favor of board-specific versions: The UART where the output of\nprom_putchar is directed to really depends on the board, the current\nimplementation hardcodes this on a per-SoC basis which is just wrong.\n\nSo a generic uart tx function is provided in the alchemy headers,\nand the boards can provide their own prom_putchar with custom\ndestination uart, and all in-kernel alchemy boards support\nearly printk.\n\nSigned-off-by: Manuel Lauss \u003cmanuel.lauss@gmail.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "963accbc82a0912b39de39d59e2fd6741db3aa4b", "tree": "4ea340b0261ab19f3f0776f47e4fab8708934b5b", "parents": [ "ea071cc705e8bfba0c8bf84be8d4f9f4e9da6962" ], "author": { "name": "Manuel Lauss", "email": "manuel.lauss@googlemail.com", "time": "Tue Oct 13 20:22:35 2009 +0200" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:52:55 2010 +0100" }, "message": "MIPS: Alchemy: change dbdma to accept physical memory addresses\n\nDMA can only be done from physical addresses; move the \"virt_to_phys\"\nsource/destination buffer address translation from the dbdma queueing\nfunctions (since the hardware can only DMA to/from physical addresses)\nto their respective users.\n\nSigned-off-by: Manuel Lauss \u003cmanuel.lauss@gmail.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "ea071cc705e8bfba0c8bf84be8d4f9f4e9da6962", "tree": "9dafff9da1740dcfc475100b4d5dae963650cfd1", "parents": [ "f1fc6645a4d2cb944320ce8ed1e40f88059779e1" ], "author": { "name": "Manuel Lauss", "email": "manuel.lauss@googlemail.com", "time": "Tue Oct 13 20:22:34 2009 +0200" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:52:54 2010 +0100" }, "message": "MIPS: Alchemy: remove dbdma compat macros\n\nRemove dbdma compat macros, move remaining users over to default\nqueueing functions and -flags.\n\n(Queueing function signature has changed in order to give\n a build failure instead of silent functional changes due\n to the no longer implicitly specified DDMA_FLAGS_IE flag)\n\nSigned-off-by: Manuel Lauss \u003cmanuel.lauss@gmail.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "788144656b8a862e724a1296e64ab6375eb541ed", "tree": "96208eed56da25acdf9d923b9d9986e82dcd8944", "parents": [ "93e9cd8485b31e5a33f1040bff4d15e65c0b2d19" ], "author": { "name": "Manuel Lauss", "email": "manuel.lauss@googlemail.com", "time": "Wed Oct 07 20:15:15 2009 +0200" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:52:53 2010 +0100" }, "message": "MIPS: Alchemy: Stop IRQ name sharing\n\nEliminate the sharing of IRQ names among the differenct Alchemy\nvariants. IRQ numbers need no longer be hidden behind a\nCONFIG_SOC_AU1XXX symbol: step 1 in my quest to make the Alchemy\ncode less reliant on a hardcoded subtype.\n\nThis patch also renames the GPIO irq number constants. It\u0027s really\nan interrupt line, NOT a GPIO number!\n\nCode which relied on certain irq numbers to have the same name\nacross all supported cpu subtypes is changed to determine current\ncpu subtype at runtime; in some places this isn\u0027t possible so\na \"compat\" symbol is used.\n\nRun-tested on DB1200.\n\nSigned-off-by: Manuel Lauss \u003cmanuel.lauss@gmail.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "93e9cd8485b31e5a33f1040bff4d15e65c0b2d19", "tree": "a642c7fc09e3a7e3f8f71bb7f16018f807a6864e", "parents": [ "0a0b1295ef26a5f8387771c148fb63dccf897869" ], "author": { "name": "Manuel Lauss", "email": "manuel.lauss@googlemail.com", "time": "Wed Oct 07 20:15:14 2009 +0200" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:52:52 2010 +0100" }, "message": "MIPS: Alchemy: Simple cpu subtype detector\n\nExtract the alchemy chip variant from c0_prid register.\n\nSigned-off-by: Manuel Lauss \u003cmanuel.lauss@gmail.com\u003e\nCc: linux-mips@linux-mips.org\nPatchwork: http://patchwork.linux-mips.org/patch/14/\nPatchwork: http://patchwork.linux-mips.org/patch/707/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "27dd65ac9afabc8e67ab73f7c2f575eddbb47167", "tree": "d8da508ceff4f2e69f8cc621a8bdebe83fef02e8", "parents": [ "66213b3ccfc770704025ce9465fa3aaedde21b55" ], "author": { "name": "Manuel Lauss", "email": "manuel.lauss@googlemail.com", "time": "Sun Oct 04 14:55:28 2009 +0200" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:52:51 2010 +0100" }, "message": "MIPS: Alchemy: devboards: wire up new PCMCIA driver.\n\nRegister the PCMCIA driver on all boards supported by it,\nget rid of now-unused pcmcia macros in the board headers\n(and subsequently empty pb1100/pb1500 ones).\n\nSigned-off-by: Manuel Lauss \u003cmanuel.lauss@gmail.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "66213b3ccfc770704025ce9465fa3aaedde21b55", "tree": "2f74c1819b371926952c9c5b8f98ae808588e728", "parents": [ "7e50b2b741bb4f9dbddc9f56972ef82a7d4b33ed" ], "author": { "name": "Manuel Lauss", "email": "manuel.lauss@googlemail.com", "time": "Sun Oct 04 14:55:27 2009 +0200" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:52:51 2010 +0100" }, "message": "MIPS: PCMCIA: new socket driver for Au1000 demoboards.\n\nNew PCMCIA socket driver for all Db/Pb1xxx boards (except Pb1000),\nwhich replaces au1000_db1x00.c and (most of) au1000_pb1x00.c.\nNotable improvements:\n - supports Db1000, DB/PB1100/1500/1550/1200.\n - support for carddetect and statuschange IRQs.\n - pcmcia socket mem/io/attr areas and irqs passed through\n platform resource information.\n - doesn\u0027t freeze system during card insertion/ejection like\n the one it replaces.\n - boardtype is automatically detected using BCSR ID register.\n\nRun-tested on the DB1200.\n\nCc: Linux-PCMCIA \u003clinux-pcmcia@lists.infradead.org\u003e\nSigned-off-by: Manuel Lauss \u003cmanuel.lauss@gmail.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "7e50b2b741bb4f9dbddc9f56972ef82a7d4b33ed", "tree": "3302cb551b83f715827e967e3f8fd7188d952b91", "parents": [ "95a437966dba642870a93d16bf82af8926bb2082" ], "author": { "name": "Manuel Lauss", "email": "manuel.lauss@googlemail.com", "time": "Sun Oct 04 14:55:26 2009 +0200" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:52:50 2010 +0100" }, "message": "MIPS: Alchemy: remove board_init_irq() function.\n\nremove board_init_irq(): On all in-kernel boards it is sufficient to\ninitialize board interrupts in an arch_initcall by using the default\nlinux irq functions.\n\nSome small irqmap.c files have been folded into board_setup files.\n\nRun-tested on DB1200; compile-tested on all other affected boards.\n\nSigned-off-by: Manuel Lauss \u003cmanuel.lauss@gmail.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "95a437966dba642870a93d16bf82af8926bb2082", "tree": "18e797fc543f9650f03fcb06aae29bf5ca20e585", "parents": [ "9bdcf336d0c061e77f4c45c7b2bc32e3ed6b57e3" ], "author": { "name": "Manuel Lauss", "email": "manuel.lauss@googlemail.com", "time": "Sun Oct 04 14:55:25 2009 +0200" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:52:50 2010 +0100" }, "message": "MIPS: Alchemy: devboards: factor out PB1200 IRQ cascade code.\n\nMove the PB1200 IRQ cascade code out to the BCSR support code:\nupcoming DB1300 support can use it too.\n\nSigned-off-by: Manuel Lauss \u003cmanuel.lauss@gmail.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "9bdcf336d0c061e77f4c45c7b2bc32e3ed6b57e3", "tree": "9cce0d50bb1709654fae719e7175da25279402bc", "parents": [ "ebc89718a4b3fa0e440151fb4484541700828a5d" ], "author": { "name": "Manuel Lauss", "email": "manuel.lauss@googlemail.com", "time": "Sun Oct 04 14:55:24 2009 +0200" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Feb 27 12:52:50 2010 +0100" }, "message": "MIPS: Alchemy: devboard register abstraction\n\nAll Alchemy development boards have external CPLDs with a few registers\nin them. They all share an identical register layout with only a few\nminor differences (except the PB1000) in bit functions and base\naddresses.\n\nThis patch\n- adds a primitive facility to initialize and use these external\n registers,\n- replaces all occurrences of bcsr-\u003exxx accesses with calls to the new\n functions (the pb1200 cascade irq handling code is special).\n- collects BCSR register information scattered throughout the board\n headers in a central place.\n\nSigned-off-by: Manuel Lauss \u003cmanuel.lauss@gmail.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "4b3073e1c53a256275f1079c0fbfbe85883d9275", "tree": "a0fa98cb75edbbc58c43bbe38ac4c6da0913ae6d", "parents": [ "ed42acaef1a9d51631a31b55e9ed52d400430492" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Dec 18 16:40:18 2009 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Feb 20 16:41:46 2010 +0000" }, "message": "MM: Pass a PTE pointer to update_mmu_cache() rather than the PTE itself\n\nOn VIVT ARM, when we have multiple shared mappings of the same file\nin the same MM, we need to ensure that we have coherency across all\ncopies. We do this via make_coherent() by making the pages\nuncacheable.\n\nThis used to work fine, until we allowed highmem with highpte - we\nnow have a page table which is mapped as required, and is not available\nfor modification via update_mmu_cache().\n\nRalf Beache suggested getting rid of the PTE value passed to\nupdate_mmu_cache():\n\n On MIPS update_mmu_cache() calls __update_tlb() which walks pagetables\n to construct a pointer to the pte again. Passing a pte_t * is much\n more elegant. Maybe we might even replace the pte argument with the\n pte_t?\n\nBen Herrenschmidt would also like the pte pointer for PowerPC:\n\n Passing the ptep in there is exactly what I want. I want that\n -instead- of the PTE value, because I have issue on some ppc cases,\n for I$/D$ coherency, where set_pte_at() may decide to mask out the\n _PAGE_EXEC.\n\nSo, pass in the mapped page table pointer into update_mmu_cache(), and\nremove the PTE value, updating all implementations and call sites to\nsuit.\n\nIncludes a fix from Stephen Rothwell:\n\n sparc: fix fallout from update_mmu_cache API change\n\n Signed-off-by: Stephen Rothwell \u003csfr@canb.auug.org.au\u003e\n\nAcked-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "e770a0f1154193ca6b6e720a86aeaa2edc9261c6", "tree": "04f5f5420e4116a18be8f94c117aadb870eaa46d", "parents": [ "7ab02af428c2d312c0cf8fb0b01cc1eb21131a3d", "91dfc423cc8cfd399fb308a837102a7ab7fa067e" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Feb 02 12:45:33 2010 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Feb 02 12:45:33 2010 -0800" }, "message": "Merge branch \u0027upstream\u0027 of git://ftp.linux-mips.org/pub/scm/upstream-linus\n\n* \u0027upstream\u0027 of git://ftp.linux-mips.org/pub/scm/upstream-linus:\n MIPS: 64-bit: Detect virtual memory size\n MIPS: AR7: Fix USB slave mem range typo\n MIPS: Alchemy: Fix dbdma ring destruction memory debugcheck.\n" }, { "commit": "91dfc423cc8cfd399fb308a837102a7ab7fa067e", "tree": "21c75672185153084a5ac8e38ca3938ca0cf4ac1", "parents": [ "ba284b1f199ef7121489010da6614561a679eab6" ], "author": { "name": "Guenter Roeck", "email": "guenter.roeck@ericsson.com", "time": "Tue Feb 02 08:52:20 2010 -0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Feb 02 19:56:23 2010 +0100" }, "message": "MIPS: 64-bit: Detect virtual memory size\n\nLinux kernel 2.6.32 and later allocate address space from the top of the\nkernel virtual memory address space.\n\nThis patch implements virtual memory size detection for 64 bit MIPS CPUs\nto avoid resulting crashes.\n\nSigned-off-by: Guenter Roeck \u003cguenter.roeck@ericsson.com\u003e\nCc: linux-mips@linux-mips.org\nPatchwork: http://patchwork.linux-mips.org/patch/935/\nReviewed-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "ab386128f20c44c458a90039ab1bdc265ac474c9", "tree": "2ad188744922b1bb951fd10ff50dc04c83acce22", "parents": [ "dbfc196a3cc1a2514ad0737a82f764de23bd65e6", "ab658321f32770b903a4426e2a6fae0392757755" ], "author": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Tue Feb 02 14:38:15 2010 +0900" }, "committer": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Tue Feb 02 14:38:15 2010 +0900" }, "message": "Merge branch \u0027master\u0027 into percpu\n" }, { "commit": "22f4bb68b301f4ab896e9b3b0431fdde962242d2", "tree": "62767bbd1ad7d11dbbeea3482b7902f08ea178ce", "parents": [ "be8cde8b24c9dca1e54598690115eee5b1476519" ], "author": { "name": "Manuel Lauss", "email": "manuel.lauss@googlemail.com", "time": "Tue Jan 26 20:39:33 2010 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Feb 01 20:30:25 2010 +0100" }, "message": "MIPS: Alchemy: Fix dbdma ring destruction memory debugcheck.\n\nDBDMA descriptors need to be located at 32-byte aligned addresses;\nhowever kmalloc in conjunction with the SLAB allocator and\nCONFIG_DEBUG_SLUB enabled doesn\u0027t deliver any. The dbdma code works\naround that by allocating a larger area and realigning the start\naddress within it.\n\nWhen freeing a channel however this adjustment is not taken into\naccount which results in an oops:\n\nKernel bug detected[#1]:\n[...]\nCall Trace:\n[\u003c80186010\u003e] cache_free_debugcheck+0x284/0x318\n[\u003c801869d8\u003e] kfree+0xe8/0x2a0\n[\u003c8010b31c\u003e] au1xxx_dbdma_chan_free+0x2c/0x7c\n[\u003c80388dc8\u003e] au1x_pcm_dbdma_free+0x34/0x4c\n[\u003c80388fa8\u003e] au1xpsc_pcm_close+0x28/0x38\n[\u003c80383cb8\u003e] soc_codec_close+0x14c/0x1cc\n[\u003c8036dbb4\u003e] snd_pcm_release_substream+0x60/0xac\n[\u003c8036dc40\u003e] snd_pcm_release+0x40/0xa0\n[\u003c8018c7a8\u003e] __fput+0x11c/0x228\n[\u003c80188f60\u003e] filp_close+0x7c/0x98\n[\u003c80189018\u003e] sys_close+0x9c/0xe4\n[\u003c801022a0\u003e] stack_done+0x20/0x3c\n\nFix this by recording the address delivered by kmalloc() and using\nit as parameter to kfree().\n\nThis fix is only necessary with the SLAB allocator and CONFIG_DEBUG_SLAB\nenabled; non-debug SLAB, SLUB do return nicely aligned addresses,\ndebug-enabled SLUB currently panics early in the boot process.\n\nSigned-off-by: Manuel Lauss \u003cmanuel.lauss@gmail.com\u003e\nTo: Linux-MIPS \u003clinux-mips@linux-mips.org\u003e\nCc: Manuel Lauss \u003cmanuel.lauss@gmail.com\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/878/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "010c108d7af708d9e09b83724a058a76803fbc66", "tree": "6b7108e6852b0306ecd686a8ce9b9ae5733985fa", "parents": [ "59dfa2fcaecc39fb88bfa196cb15adca7146867a" ], "author": { "name": "David VomLehn", "email": "dvomlehn@cisco.com", "time": "Mon Dec 21 17:49:22 2009 -0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Jan 28 00:03:31 2010 +0100" }, "message": "MIPS: PowerTV: Fix support for timer interrupts with \u003e 64 external IRQs\n\nThe MIPS processor is limited to 64 external interrupt sources. Using a\ngreater number without IRQ sharing requires reading platform-specific\nregisters. On such platforms, reading the IntCtl register to determine\nwhich interrupt corresponds to a timer interrupt will not work.\n\nOn MIPSR2 systems there is a solution - the TI bit in the Cause register,\nspecifically indicates that a timer interrupt has occured. This patch uses\nthat bit to detect interrupts for MIPSR2 processors, which may be expected\nto work regardless of how the timer interrupt may be routed in the hardware.\n\nSigned-off-by: David VomLehn (dvomlehn@cisco.com)\nTo: linux-mips@linux-mips.org\nPatchwork: http://patchwork.linux-mips.org/patch/804/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "59dfa2fcaecc39fb88bfa196cb15adca7146867a", "tree": "25a1e3541ec399110d7a53ac8162e1bbcbd5efc0", "parents": [ "9c4a6fce2032fcb5bb8339d53fd3dadfd7ddfb98" ], "author": { "name": "David VomLehn", "email": "dvomlehn@cisco.com", "time": "Wed Dec 23 17:34:46 2009 -0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Jan 28 00:03:31 2010 +0100" }, "message": "MIPS: PowerTV: Streamline access to platform device registers\n\nPre-compute addresses for the basic ASIC registers. This speeds up access\nand allows memory for unused configurations to be freed. In addition,\nuninitialized register addresses will be returned as NULL to catch bad\nusage quickly.\n\nSigned-off-by: David VomLehn \u003cdvomlehn@cisco.com\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: http://patchwork.linux-mips.org/patch/806/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "d797396f3387c5be8f63fcc8e9be98bb884ea86a", "tree": "63024f12dfb080db7d8fbc73776f1bbdc68bbf7f", "parents": [ "0e8a1d8262f41d6e8c1d736a408882bbb7a5c0a6" ], "author": { "name": "Anton Blanchard", "email": "anton@samba.org", "time": "Wed Jan 06 15:55:13 2010 +1100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Jan 12 18:19:37 2010 +0100" }, "message": "MIPS: cpumask_of_node() should handle -1 as a node\n\npcibus_to_node can return -1 if we cannot determine which node a pci bus\nis on. If passed -1, cpumask_of_node will negatively index the lookup array\nand pull in random data:\n\n# cat /sys/devices/pci0000:00/0000:00:01.0/local_cpus\n00000000,00000003,00000000,00000000\n# cat /sys/devices/pci0000:00/0000:00:01.0/local_cpulist\n64-65\n\nChange cpumask_of_node to check for -1 and return cpu_all_mask in this\ncase:\n\n# cat /sys/devices/pci0000:00/0000:00:01.0/local_cpus\nffffffff,ffffffff,ffffffff,ffffffff\n# cat /sys/devices/pci0000:00/0000:00:01.0/local_cpulist\n0-127\n\nSigned-off-by: Anton Blanchard \u003canton@samba.org\u003e\nCc: linux-mips@linux-mips.org\nCc: linux-kernel@vger.kernel.org\nCc: Rusty Russell \u003crusty@rustcorp.com.au\u003e\nCc: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/831/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "38b7827fcdd660f591d645bd3ae6644456a4773c", "tree": "ec6e81d1d2c0f4970ff682499734e1a666bc5de2", "parents": [ "32032df6c2f6c9c6b2ada2ce42322231824f70c2" ], "author": { "name": "Christoph Lameter", "email": "cl@linux-foundation.org", "time": "Tue Jan 05 15:34:49 2010 +0900" }, "committer": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Tue Jan 05 15:34:49 2010 +0900" }, "message": "local_t: Remove cpu_local_xx macros\n\nThese macros have not been used for awhile now.\n\nSigned-off-by: Christoph Lameter \u003ccl@linux-foundation.org\u003e\nSigned-off-by: Tejun Heo \u003ctj@kernel.org\u003e\n" }, { "commit": "dbfc985195410dad803c845743c63cd73bd1fe32", "tree": "6bf6dbecb92539285ebb89948e63e691a0947941", "parents": [ "7c508e50be47737b9a72d0f15c3ef1146925e2d2", "606d62fa02cf1da43c6e21521650fff07a2e56d1" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Dec 17 16:38:06 2009 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Dec 17 16:38:06 2009 -0800" }, "message": "Merge branch \u0027upstream\u0027 of git://ftp.linux-mips.org/pub/scm/upstream-linus\n\n* \u0027upstream\u0027 of git://ftp.linux-mips.org/pub/scm/upstream-linus: (71 commits)\n MIPS: Lasat: Fix botched changes to sysctl code.\n RTC: rtc-cmos.c: Fix warning on MIPS\n MIPS: Cleanup random differences beween lmo and Linus\u0027 kernel.\n MIPS: No longer hardwire CONFIG_EMBEDDED to y\n MIPS: Fix and enhance built-in kernel command line\n MIPS: eXcite: Remove platform.\n MIPS: Loongson: Cleanups of serial port support\n MIPS: Lemote 2F: Suspend CS5536 MFGPT Timer\n MIPS: Excite: move iodev_remove to .devexit.text\n MIPS: Lasat: Convert to proc_fops / seq_file\n MIPS: Cleanup signal code initialization\n MIPS: Modularize COP2 handling\n MIPS: Move EARLY_PRINTK to Kconfig.debug\n MIPS: Yeeloong 2F: Cleanup reset logic using the new ec_write function\n MIPS: Yeeloong 2F: Add LID open event as the wakeup event\n MIPS: Yeeloong 2F: Add basic EC operations\n MIPS: Move several variables from .bss to .init.data\n MIPS: Tracing: Make function graph tracer work with -mmcount-ra-address\n MIPS: Tracing: Reserve $12(t0) for mcount-ra-address of gcc 4.5\n MIPS: Tracing: Make ftrace for MIPS work without -fno-omit-frame-pointer\n ...\n" }, { "commit": "b8a7f3cd7e8212e5c572178ff3b5a514861036a5", "tree": "f88fd0fc83a466a6d5781f90e7ed76cb2fa0f5d7", "parents": [ "a377d181e65241344dd95aa4a42c477477be03f1", "eaff8079d4f1016a12e34ab323737314f24127dd" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Dec 17 08:31:01 2009 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Dec 17 08:31:01 2009 -0800" }, "message": "Merge branch \u0027master\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs-2.6\n\n* \u0027master\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs-2.6:\n kill I_LOCK\n fold do_sync_file_range into sys_sync_file_range\n fix up O_SYNC comments\n VFS/fsstack: handle 32-bit smp + preempt + large files in fsstack_copy_inode_size\n fsstack/ecryptfs: remove unused get_nlinks param to fsstack_copy_attr_all\n vfs: remove extraneous NULL d_inode check from do_filp_open\n fs: no games with DCACHE_UNHASHED\n fs: anon_inodes implement dname\n dio: fix use-after-free\n" }, { "commit": "76b7e0058d09f8104387980a690001681c04cc0a", "tree": "98ed096b9f5f7e25651a7d10750706026c543250", "parents": [ "1b8ab8159ef8f818f870a1d2e3b6953d80eefd3f" ], "author": { "name": "Christoph Hellwig", "email": "hch@lst.de", "time": "Thu Dec 17 14:24:20 2009 +0100" }, "committer": { "name": "Al Viro", "email": "viro@zeniv.linux.org.uk", "time": "Thu Dec 17 11:03:24 2009 -0500" }, "message": "fix up O_SYNC comments\n\nProper Posix O_SYNC handling only made it into 2.6.33, not 2.6.32.\n\nSigned-off-by: Christoph Hellwig \u003chch@lst.de\u003e\nSigned-off-by: Al Viro \u003cviro@zeniv.linux.org.uk\u003e\n" }, { "commit": "5a865c0606eb44d5d12cabb429751c83712183de", "tree": "726d6eaf3b20f30900304bd0cbb6339b423a071f", "parents": [ "331d9d5958277de27e6ce42247e1cbec54fd1c7e", "46e75f66677f5094bb51e91f9473128c4e907c7d" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Dec 17 07:23:42 2009 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Dec 17 07:23:42 2009 -0800" }, "message": "Merge branch \u0027for-33\u0027 of git://repo.or.cz/linux-kbuild\n\n* \u0027for-33\u0027 of git://repo.or.cz/linux-kbuild: (29 commits)\n net: fix for utsrelease.h moving to generated\n gen_init_cpio: fixed fwrite warning\n kbuild: fix make clean after mismerge\n kbuild: generate modules.builtin\n genksyms: properly consider EXPORT_UNUSED_SYMBOL{,_GPL}()\n score: add asm/asm-offsets.h wrapper\n unifdef: update to upstream revision 1.190\n kbuild: specify absolute paths for cscope\n kbuild: create include/generated in silentoldconfig\n scripts/package: deb-pkg: use fakeroot if available\n scripts/package: add KBUILD_PKG_ROOTCMD variable\n scripts/package: tar-pkg: use tar --owner\u003droot\n Kbuild: clean up marker\n net: add net_tstamp.h to headers_install\n kbuild: move utsrelease.h to include/generated\n kbuild: move autoconf.h to include/generated\n drop explicit include of autoconf.h\n kbuild: move compile.h to include/generated\n kbuild: drop include/asm\n kbuild: do not check for include/asm-$ARCH\n ...\n\nFixed non-conflicting clean merge of modpost.c as per comments from\nStephen Rothwell (modpost.c had grown an include of linux/autoconf.h\nthat needed to be changed to generated/autoconf.h)\n" }, { "commit": "de4148f3ef54b644a181ad75a6fb4b373f2b01f0", "tree": "83aa287fbbcc14a3df9e161af99af49776b61b6f", "parents": [ "c3d8d85019c9e4f6e4f23d194b6432a2c2464372" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 17 01:57:35 2009 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 17 01:57:35 2009 +0000" }, "message": "MIPS: eXcite: Remove platform.\n\nThe platform has never been fully merged \n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\nCc: Thomas Koeller \u003cthomas.koeller@baslerweb.com\u003e\nCc: David Woodhouse \u003cdwmw2@infradead.org\u003e\nCc: Wim Van Sebroeck \u003cwim@iguana.be\u003e\nCc: linux-kernel@vger.kernel.org\nCc: linux-mtd@lists.infradead.org\nAcked-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\nAcked-by: Wim Van Sebroeck \u003cwim@iguana.be\u003e\n" }, { "commit": "c3d8d85019c9e4f6e4f23d194b6432a2c2464372", "tree": "644e1cf5e7f215fa6789d96bce9fac7e14666846", "parents": [ "c47a48d83a7a82c86ff3e74bdcabeee8f6e6b730" ], "author": { "name": "Wu Zhangjin", "email": "wuzhangjin@gmail.com", "time": "Sat Nov 28 14:21:50 2009 +0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 17 01:57:34 2009 +0000" }, "message": "MIPS: Loongson: Cleanups of serial port support\n\nThis patchs uses a loongson_uart_base variable instead of the\nuart_base[] array and adds a new kernel option to avoid to compile\nuart_base.c all the time, which will save a little bit of memory for us.\n\nSigned-off-by: Wu Zhangjin \u003cwuzhangjin@gmail.com\u003e\nCc: linux-mips@linux-mips.org\nhttp://patchwork.linux-mips.org/patch/727/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "137f6f3e284e8215a940cf20dbf2aef449fe5a60", "tree": "a8243dc24c2e00eb2d6b0c924b2dde3910912eb0", "parents": [ "69f3a7de1f1ec935924b1b13f83812f8b30e92ce" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Nov 24 19:35:41 2009 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 17 01:57:32 2009 +0000" }, "message": "MIPS: Cleanup signal code initialization\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\nCc: linux-mips@linux-mips.org\nPatchwork: http://patchwork.linux-mips.org/patch/709/\n" }, { "commit": "69f3a7de1f1ec935924b1b13f83812f8b30e92ce", "tree": "a5f8a71b9cb3026a44ae7a1564488de8c3d8d2a9", "parents": [ "4dd92e15b316d1a782772f16074571a70ceb9184" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Nov 24 01:24:58 2009 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 17 01:57:30 2009 +0000" }, "message": "MIPS: Modularize COP2 handling\n\nAway with the daemons of ifdef; get ready for future COP2 users.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/708/\n" }, { "commit": "cb1ed9e117098269de3c0dfff816dff453dd4b59", "tree": "918d2eec2f59ca418e395d44b95881951a4dddab", "parents": [ "ec614d80b58677de30b876a16fdd3fde85bebdc1" ], "author": { "name": "Wu Zhangjin", "email": "wuzhangjin@gmail.com", "time": "Sat Nov 21 19:05:24 2009 +0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 17 01:57:28 2009 +0000" }, "message": "MIPS: Yeeloong 2F: Add LID open event as the wakeup event\n\nYeeloong 2F netbook has an KB3310B embedded controller to manage the LID\naction. When the LID is closed or opened a SCI interrupt is sent out and\nthe corresponding event is saved to an EC register for later query.\n\nAllow the LID open interrupt to wake the processor from wait mode if it is\nin the suspend mode.\n\nSigned-off-by: Wu Zhangjin \u003cwuzhangjin@gmail.com\u003e\nCc: linux-mips@linux-mips.org\nPatchwork: http://patchwork.linux-mips.org/patch/685/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "046199cae714a7f9e88f5a7940b077f4515f48cb", "tree": "8fb3a93a80fc2f719daa0ac905b610de68cf6693", "parents": [ "e17ff5fec65a0213416efbe7ceae5f2f9887dda2" ], "author": { "name": "Wu Zhangjin", "email": "wuzhangjin@gmail.com", "time": "Fri Nov 20 20:34:36 2009 +0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 17 01:57:25 2009 +0000" }, "message": "MIPS: Tracing: Make ftrace for MIPS work without -fno-omit-frame-pointer\n\nWhen remove the -fno-omit-frame-pointer, gcc will not save the frame\npointer for us, we need to save one ourselves.\n\nSigned-off-by: Wu Zhangjin \u003cwuzhangjin@gmail.com\u003e\nCc: Steven Rostedt \u003crostedt@goodmis.org\u003e\nCc: Nicholas Mc Guire \u003cder.herr@hofr.at\u003e\nCc: zhangfx@lemote.com\nCc: Wu Zhangjin \u003cwuzhangjin@gmail.com\u003e\nCc: Ingo Molnar \u003cmingo@elte.hu\u003e\nCc: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: Frederic Weisbecker \u003cfweisbec@gmail.com\u003e\nCc: linux-kernel@vger.kernel.org\nCc: linux-mips@linux-mips.org\nPatchwork: http://patchwork.linux-mips.org/patch/679/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" } ], "next": "8f99a162653531ef25a3dd0f92bfb6332cd2b295" }