)]}'
{
  "log": [
    {
      "commit": "62c4f0a2d5a188f73a94f2cb8ea0dba3e7cf0a7f",
      "tree": "e85ca2d0dd43f90dccf758338764c3caa55f333f",
      "parents": [
        "089f26d5e31b7bf42a9a8fefec08b30cd27f4b0e"
      ],
      "author": {
        "name": "David Woodhouse",
        "email": "dwmw2@infradead.org",
        "time": "Wed Apr 26 12:56:16 2006 +0100"
      },
      "committer": {
        "name": "David Woodhouse",
        "email": "dwmw2@infradead.org",
        "time": "Wed Apr 26 12:56:16 2006 +0100"
      },
      "message": "Don\u0027t include linux/config.h from anywhere else in include/\n\nSigned-off-by: David Woodhouse \u003cdwmw2@infradead.org\u003e\n"
    },
    {
      "commit": "23bdf86aa06ebe71bcbf6b7d25de9958c6ab33fa",
      "tree": "56636558e8cdeee0739e7d8c82d66ffe625340b3",
      "parents": [
        "de4533a04eb4f66dbef71f59a9c118256b886823"
      ],
      "author": {
        "name": "Lennert Buytenhek",
        "email": "buytenh@wantstofly.org",
        "time": "Tue Mar 28 21:00:40 2006 +0100"
      },
      "committer": {
        "name": "Russell King",
        "email": "rmk+kernel@arm.linux.org.uk",
        "time": "Tue Mar 28 21:00:40 2006 +0100"
      },
      "message": "[ARM] 3377/2: add support for intel xsc3 core\n\nPatch from Lennert Buytenhek\n\nThis patch adds support for the new XScale v3 core.  This is an\nARMv5 ISA core with the following additions:\n\n- L2 cache\n- I/O coherency support (on select chipsets)\n- Low-Locality Reference cache attributes (replaces mini-cache)\n- Supersections (v6 compatible)\n- 36-bit addressing (v6 compatible)\n- Single instruction cache line clean/invalidate\n- LRU cache replacement (vs round-robin)\n\nI attempted to merge the XSC3 support into proc-xscale.S, but XSC3\ncores have separate errata and have to handle things like L2, so it\nis simpler to keep it separate.\n\nL2 cache support is currently a build option because the L2 enable\nbit must be set before we enable the MMU and there is no easy way to\ncapture command line parameters at this point.\n\nThere are still optimizations that can be done such as using LLR for\ncopypage (in theory using the exisiting mini-cache code) but those\ncan be addressed down the road.\n\nSigned-off-by: Deepak Saxena \u003cdsaxena@plexity.net\u003e\nSigned-off-by: Lennert Buytenhek \u003cbuytenh@wantstofly.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n"
    },
    {
      "commit": "78ff18a412da24a4b79c6a97000ef5e467e813da",
      "tree": "901d67dc2c709b71fba37b37b901ea167cef21a2",
      "parents": [
        "9d4f13e531b4722fe40cc8e28c02a495bdd49267"
      ],
      "author": {
        "name": "Russell King",
        "email": "rmk@dyn-67.arm.linux.org.uk",
        "time": "Tue Jan 03 17:39:34 2006 +0000"
      },
      "committer": {
        "name": "Russell King",
        "email": "rmk+kernel@arm.linux.org.uk",
        "time": "Tue Jan 03 17:39:34 2006 +0000"
      },
      "message": "[ARM] Cleanup ARM includes\n\narch/arm/kernel/entry-armv.S has contained a comment suggesting\nthat asm/hardware.h and asm/arch/irqs.h should be moved into the\nasm/arch/entry-macro.S include.  So move the includes to these\ntwo files as required.\n\nAdd missing includes (asm/hardware.h, asm/io.h) to asm/arch/system.h\nincludes which use those facilities, and remove asm/io.h from\nkernel/process.c.\n\nRemove other unnecessary includes from arch/arm/kernel, arch/arm/mm\nand arch/arm/mach-footbridge.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n"
    },
    {
      "commit": "d7b6b3589471c3856f1e6dc9c77abc4af962ffdb",
      "tree": "82751eba321a062ce91af7f0f0bff8c4c5531a1c",
      "parents": [
        "b38d950d3aedf90c8b15b3c7c799b5eb53c47c45"
      ],
      "author": {
        "name": "Russell King",
        "email": "rmk@dyn-67.arm.linux.org.uk",
        "time": "Thu Sep 08 15:32:23 2005 +0100"
      },
      "committer": {
        "name": "Russell King",
        "email": "rmk+kernel@arm.linux.org.uk",
        "time": "Thu Sep 08 15:32:23 2005 +0100"
      },
      "message": "[ARM] Fix ARMv6 VIPT cache \u003e\u003d 32K\n\nThis adds the necessary changes to ensure that we flush the\ncaches correctly with aliasing VIPT caches.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n"
    },
    {
      "commit": "b8a9b66fbee09d0cc71c272b5c1d1f3320afbbf0",
      "tree": "25be8fc2ef91f6dcbb7f7dd2b9e3db2a95963477",
      "parents": [
        "8830f04a092b47f3d246271b24685cd9eab82027"
      ],
      "author": {
        "name": "Russell King",
        "email": "rmk@dyn-67.arm.linux.org.uk",
        "time": "Mon Jun 20 11:31:09 2005 +0100"
      },
      "committer": {
        "name": "Russell King",
        "email": "rmk@dyn-67.arm.linux.org.uk",
        "time": "Mon Jun 20 11:31:09 2005 +0100"
      },
      "message": "[PATCH] ARM: Add common CACHE_COLOUR macro\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n"
    },
    {
      "commit": "1da177e4c3f41524e886b7f1b8a0c1fc7321cac2",
      "tree": "0bba044c4ce775e45a88a51686b5d9f90697ea9d",
      "parents": [],
      "author": {
        "name": "Linus Torvalds",
        "email": "torvalds@ppc970.osdl.org",
        "time": "Sat Apr 16 15:20:36 2005 -0700"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@ppc970.osdl.org",
        "time": "Sat Apr 16 15:20:36 2005 -0700"
      },
      "message": "Linux-2.6.12-rc2\n\nInitial git repository build. I\u0027m not bothering with the full history,\neven though we have it. We can create a separate \"historical\" git\narchive of that later if we want to, and in the meantime it\u0027s about\n3.2GB when imported into git - space that would just make the early\ngit days unnecessarily complicated, when we don\u0027t have a lot of good\ninfrastructure for it.\n\nLet it rip!\n"
    }
  ]
}