)]}'
{
  "log": [
    {
      "commit": "df2071bd081408318d659cd14a9cf6ff23d874c9",
      "tree": "b31291b5fd4b9f84c629833afbfaa8d431857475",
      "parents": [
        "97e3d94aac1c3e95bd04d1b186479a4df3663ab8",
        "be1066bbcd443a65df312fdecea7e4959adedb45"
      ],
      "author": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Mon May 03 11:28:58 2010 +0800"
      },
      "committer": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Mon May 03 11:28:58 2010 +0800"
      },
      "message": "Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6\n"
    },
    {
      "commit": "5a0e3ad6af8660be21ca98a971cd00f331318c05",
      "tree": "5bfb7be11a03176a87296a43ac6647975c00a1d1",
      "parents": [
        "ed391f4ebf8f701d3566423ce8f17e614cde9806"
      ],
      "author": {
        "name": "Tejun Heo",
        "email": "tj@kernel.org",
        "time": "Wed Mar 24 17:04:11 2010 +0900"
      },
      "committer": {
        "name": "Tejun Heo",
        "email": "tj@kernel.org",
        "time": "Tue Mar 30 22:02:32 2010 +0900"
      },
      "message": "include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h\n\npercpu.h is included by sched.h and module.h and thus ends up being\nincluded when building most .c files.  percpu.h includes slab.h which\nin turn includes gfp.h making everything defined by the two files\nuniversally available and complicating inclusion dependencies.\n\npercpu.h -\u003e slab.h dependency is about to be removed.  Prepare for\nthis change by updating users of gfp and slab facilities include those\nheaders directly instead of assuming availability.  As this conversion\nneeds to touch large number of source files, the following script is\nused as the basis of conversion.\n\n  http://userweb.kernel.org/~tj/misc/slabh-sweep.py\n\nThe script does the followings.\n\n* Scan files for gfp and slab usages and update includes such that\n  only the necessary includes are there.  ie. if only gfp is used,\n  gfp.h, if slab is used, slab.h.\n\n* When the script inserts a new include, it looks at the include\n  blocks and try to put the new include such that its order conforms\n  to its surrounding.  It\u0027s put in the include block which contains\n  core kernel includes, in the same order that the rest are ordered -\n  alphabetical, Christmas tree, rev-Xmas-tree or at the end if there\n  doesn\u0027t seem to be any matching order.\n\n* If the script can\u0027t find a place to put a new include (mostly\n  because the file doesn\u0027t have fitting include block), it prints out\n  an error message indicating which .h file needs to be added to the\n  file.\n\nThe conversion was done in the following steps.\n\n1. The initial automatic conversion of all .c files updated slightly\n   over 4000 files, deleting around 700 includes and adding ~480 gfp.h\n   and ~3000 slab.h inclusions.  The script emitted errors for ~400\n   files.\n\n2. Each error was manually checked.  Some didn\u0027t need the inclusion,\n   some needed manual addition while adding it to implementation .h or\n   embedding .c file was more appropriate for others.  This step added\n   inclusions to around 150 files.\n\n3. The script was run again and the output was compared to the edits\n   from #2 to make sure no file was left behind.\n\n4. Several build tests were done and a couple of problems were fixed.\n   e.g. lib/decompress_*.c used malloc/free() wrappers around slab\n   APIs requiring slab.h to be added manually.\n\n5. The script was run on all .h files but without automatically\n   editing them as sprinkling gfp.h and slab.h inclusions around .h\n   files could easily lead to inclusion dependency hell.  Most gfp.h\n   inclusion directives were ignored as stuff from gfp.h was usually\n   wildly available and often used in preprocessor macros.  Each\n   slab.h inclusion directive was examined and added manually as\n   necessary.\n\n6. percpu.h was updated not to include slab.h.\n\n7. Build test were done on the following configurations and failures\n   were fixed.  CONFIG_GCOV_KERNEL was turned off for all tests (as my\n   distributed build env didn\u0027t work with gcov compiles) and a few\n   more options had to be turned off depending on archs to make things\n   build (like ipr on powerpc/64 which failed due to missing writeq).\n\n   * x86 and x86_64 UP and SMP allmodconfig and a custom test config.\n   * powerpc and powerpc64 SMP allmodconfig\n   * sparc and sparc64 SMP allmodconfig\n   * ia64 SMP allmodconfig\n   * s390 SMP allmodconfig\n   * alpha SMP allmodconfig\n   * um on x86_64 SMP allmodconfig\n\n8. percpu.h modifications were reverted so that it could be applied as\n   a separate patch and serve as bisection point.\n\nGiven the fact that I had only a couple of failures from tests on step\n6, I\u0027m fairly confident about the coverage of this conversion patch.\nIf there is a breakage, it\u0027s likely to be something in one of the arch\nheaders which should be easily discoverable easily on most builds of\nthe specific arch.\n\nSigned-off-by: Tejun Heo \u003ctj@kernel.org\u003e\nGuess-its-ok-by: Christoph Lameter \u003ccl@linux-foundation.org\u003e\nCc: Ingo Molnar \u003cmingo@redhat.com\u003e\nCc: Lee Schermerhorn \u003cLee.Schermerhorn@hp.com\u003e\n"
    },
    {
      "commit": "32cbd7dfce93382a70f155bf539871b4c55bed29",
      "tree": "30ae215018df38e5f6b29eec73ad9a00d693ccc9",
      "parents": [
        "18bcc9194da3c97e8f458fb1b06ac5b9b35fb23f"
      ],
      "author": {
        "name": "Huang Ying",
        "email": "ying.huang@intel.com",
        "time": "Sat Mar 13 16:28:42 2010 +0800"
      },
      "committer": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Sat Mar 13 16:28:42 2010 +0800"
      },
      "message": "crypto: aesni-intel - Fix CTR optimization build failure with gas 2.16.1\n\nAndrew Morton reported that AES-NI CTR optimization failed to compile\nwith gas 2.16.1, the error message is as follow:\n\narch/x86/crypto/aesni-intel_asm.S: Assembler messages:\narch/x86/crypto/aesni-intel_asm.S:752: Error: suffix or operands invalid for `movq\u0027\narch/x86/crypto/aesni-intel_asm.S:753: Error: suffix or operands invalid for `movq\u0027\n\nTo fix this, a gas macro is defined to assemble movq with 64bit\ngeneral purpose registers and XMM registers. The macro will generate\nthe raw .byte sequence for needed instructions.\n\nReported-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n"
    },
    {
      "commit": "12387a46bb150f5608de4aa9a90dfdddbf991e3f",
      "tree": "a840b4a5da93cc3658eeb2477e47f402d0c77e28",
      "parents": [
        "269ab459da46ae37979a0d16307d1fcaa05600b2"
      ],
      "author": {
        "name": "Huang Ying",
        "email": "ying.huang@intel.com",
        "time": "Wed Mar 10 18:28:55 2010 +0800"
      },
      "committer": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Wed Mar 10 18:28:55 2010 +0800"
      },
      "message": "crypto: aesni-intel - Add AES-NI accelerated CTR mode\n\nTo take advantage of the hardware pipeline implementation of AES-NI\ninstructions. CTR mode cryption is implemented in ASM to schedule\nmultiple AES-NI instructions one after another. This way, some latency\nof AES-NI instruction can be eliminated.\n\nPerformance testing based on dm-crypt should 50% reduction of\necryption/decryption time.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n"
    },
    {
      "commit": "3ad2f3fbb961429d2aa627465ae4829758bc7e07",
      "tree": "f365c513e8f5b477a61336a600ff54f32b7ad6e1",
      "parents": [
        "1537a3638cbf741d3826c1002026cce487a6bee0"
      ],
      "author": {
        "name": "Daniel Mack",
        "email": "daniel@caiaq.de",
        "time": "Wed Feb 03 08:01:28 2010 +0800"
      },
      "committer": {
        "name": "Jiri Kosina",
        "email": "jkosina@suse.cz",
        "time": "Tue Feb 09 11:13:56 2010 +0100"
      },
      "message": "tree-wide: Assorted spelling fixes\n\nIn particular, several occurances of funny versions of \u0027success\u0027,\n\u0027unknown\u0027, \u0027therefore\u0027, \u0027acknowledge\u0027, \u0027argument\u0027, \u0027achieve\u0027, \u0027address\u0027,\n\u0027beginning\u0027, \u0027desirable\u0027, \u0027separate\u0027 and \u0027necessary\u0027 are fixed.\n\nSigned-off-by: Daniel Mack \u003cdaniel@caiaq.de\u003e\nCc: Joe Perches \u003cjoe@perches.com\u003e\nCc: Junio C Hamano \u003cgitster@pobox.com\u003e\nSigned-off-by: Jiri Kosina \u003cjkosina@suse.cz\u003e\n"
    },
    {
      "commit": "838632438145ac6863377eb12d8b8eef9c55d288",
      "tree": "fbb0757df837f3c75a99c518a3596c38daef162d",
      "parents": [
        "9996508b3353063f2d6c48c1a28a84543d72d70b",
        "29e553631b2a0d4eebd23db630572e1027a9967a"
      ],
      "author": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Tue Dec 01 15:16:22 2009 +0800"
      },
      "committer": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Tue Dec 01 15:16:22 2009 +0800"
      },
      "message": "Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6\n"
    },
    {
      "commit": "68ee87164e73f68cf09070043c97e7f61e6966d4",
      "tree": "b06f6aac191d35fdb28d464cab686714565bd80e",
      "parents": [
        "564ec0ec05ac6ee409bde81f7ef27a3dadbf3a6a"
      ],
      "author": {
        "name": "Jiri Kosina",
        "email": "jkosina@suse.cz",
        "time": "Mon Nov 23 20:19:47 2009 +0800"
      },
      "committer": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Mon Nov 23 20:19:47 2009 +0800"
      },
      "message": "crypto: ghash-clmulni-intel - Put proper .data section in place\n\nLbswap_mask, Lpoly and Ltwo_one should clearly belong to\n.data section, not .text.\n\nSigned-off-by: Jiri Kosina \u003cjkosina@suse.cz\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n"
    },
    {
      "commit": "564ec0ec05ac6ee409bde81f7ef27a3dadbf3a6a",
      "tree": "b4bb4e29cdfc2ceb90ac10ed4da139546375faa7",
      "parents": [
        "b369e521237d6ef21c453f3ac4f4b8577ec14f87"
      ],
      "author": {
        "name": "Huang Ying",
        "email": "ying.huang@intel.com",
        "time": "Mon Nov 23 19:55:22 2009 +0800"
      },
      "committer": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Mon Nov 23 19:55:22 2009 +0800"
      },
      "message": "crypto: ghash-clmulni-intel - Use gas macro for PCLMULQDQ-NI and PSHUFB\n\nOld binutils do not support PCLMULQDQ-NI and PSHUFB, to make kernel\ncan be compiled by them, .byte code is used instead of assembly\ninstructions. But the readability and flexibility of raw .byte code is\nnot good.\n\nSo corresponding assembly instruction like gas macro is used instead.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n"
    },
    {
      "commit": "b369e521237d6ef21c453f3ac4f4b8577ec14f87",
      "tree": "cedf1e4f1287c441d1afc29efd45c0f02f21c761",
      "parents": [
        "fd650a6394b3242edf125ba9c4d500349a6d7178"
      ],
      "author": {
        "name": "Huang Ying",
        "email": "ying.huang@intel.com",
        "time": "Mon Nov 23 19:54:06 2009 +0800"
      },
      "committer": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Mon Nov 23 19:54:06 2009 +0800"
      },
      "message": "crypto: aesni-intel - Use gas macro for AES-NI instructions\n\nOld binutils do not support AES-NI instructions, to make kernel can be\ncompiled by them, .byte code is used instead of AES-NI assembly\ninstructions. But the readability and flexibility of raw .byte code is\nnot good.\n\nSo corresponding assembly instruction like gas macro is used instead.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n"
    },
    {
      "commit": "01dd95827726534230d8f03f7e6faafe24e49260",
      "tree": "2b198f49ad60e96b8564897f65939c41dd7de2a3",
      "parents": [
        "3b0d65969b549b796abc6f0230f6142fed365d49"
      ],
      "author": {
        "name": "Huang Ying",
        "email": "ying.huang@intel.com",
        "time": "Tue Nov 03 10:55:20 2009 -0500"
      },
      "committer": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Tue Nov 03 10:55:20 2009 -0500"
      },
      "message": "crypto: ghash-intel - Fix irq_fpu_usable usage\n\nWhen renaming kernel_fpu_using to irq_fpu_usable, the semantics of the\nfunction is changed too, from mesuring whether kernel is using FPU,\nthat is, the FPU is NOT available, to measuring whether FPU is usable,\nthat is, the FPU is available.\n\nBut the usage of irq_fpu_usable in ghash-clmulni-intel_glue.c is not\nchanged accordingly. This patch fixes this.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n"
    },
    {
      "commit": "3b0d65969b549b796abc6f0230f6142fed365d49",
      "tree": "0cce8ac977df20e0902cda3d6092bcb6e90e03c1",
      "parents": [
        "2d06ef7f42ed8c9969c9aa84e95df5d5c6378327"
      ],
      "author": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Tue Nov 03 09:11:15 2009 -0500"
      },
      "committer": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Tue Nov 03 09:11:15 2009 -0500"
      },
      "message": "crypto: ghash-intel - Add PSHUFB macros\n\nAdd PSHUFB macros instead of repeating byte sequences, suggested\nby Ingo.\n\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\nAcked-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n"
    },
    {
      "commit": "2d06ef7f42ed8c9969c9aa84e95df5d5c6378327",
      "tree": "20ff0f62949a957225cd1a021e20464cf85247a4",
      "parents": [
        "3e02e5cb47e049727a26c9c110867a26972bd0d6"
      ],
      "author": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Sun Nov 01 12:49:44 2009 -0500"
      },
      "committer": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Sun Nov 01 12:49:44 2009 -0500"
      },
      "message": "crypto: ghash-intel - Hard-code pshufb\n\nOld gases don\u0027t have a clue what pshufb stands for so we have\nto hard-code it for now.\n\nReported-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n"
    },
    {
      "commit": "13b79b971564ddd0f14e706592472adc8199e912",
      "tree": "9e9b680352318aafe356c499dec9319cf25ac3e0",
      "parents": [
        "4c6ab3ee4cdb86cbd4e9400dd22fad7701cbe795"
      ],
      "author": {
        "name": "Huang Ying",
        "email": "ying.huang@intel.com",
        "time": "Tue Oct 20 16:20:47 2009 +0900"
      },
      "committer": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Tue Oct 20 16:20:47 2009 +0900"
      },
      "message": "crypto: aesni-intel - Fix irq_fpu_usable usage\n\nWhen renaming kernel_fpu_using to irq_fpu_usable, the semantics of the\nfunction is changed too, from mesuring whether kernel is using FPU,\nthat is, the FPU is NOT available, to measuring whether FPU is usable,\nthat is, the FPU is available.\n\nBut the usage of irq_fpu_usable in aesni-intel_glue.c is not changed\naccordingly. This patch fixes this.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n"
    },
    {
      "commit": "0e1227d356e9b2fe0500d6cc7084f752040a1e0e",
      "tree": "6f059b8e3c31539942ad244e7aadabcb54e8d904",
      "parents": [
        "4c6ab3ee4cdb86cbd4e9400dd22fad7701cbe795"
      ],
      "author": {
        "name": "Huang Ying",
        "email": "ying.huang@intel.com",
        "time": "Mon Oct 19 11:53:06 2009 +0900"
      },
      "committer": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Mon Oct 19 11:53:06 2009 +0900"
      },
      "message": "crypto: ghash - Add PCLMULQDQ accelerated implementation\n\nPCLMULQDQ is used to accelerate the most time-consuming part of GHASH,\ncarry-less multiplication. More information about PCLMULQDQ can be\nfound at:\n\nhttp://software.intel.com/en-us/articles/carry-less-multiplication-and-its-usage-for-computing-the-gcm-mode/\n\nBecause PCLMULQDQ changes XMM state, its usage must be enclosed with\nkernel_fpu_begin/end, which can be used only in process context, the\nacceleration is implemented as crypto_ahash. That is, request in soft\nIRQ context will be defered to the cryptd kernel thread.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n"
    },
    {
      "commit": "c7208de304ac335d5d58db346bb773a471fc636b",
      "tree": "47808484fc3ff8447fe30943a33880bae00d5fee",
      "parents": [
        "15b0404272e1513940223cf9eefadfd22804a060",
        "5367b6887e7d8c870a5da7d9b8c6e9c207684e43"
      ],
      "author": {
        "name": "Linus Torvalds",
        "email": "torvalds@linux-foundation.org",
        "time": "Mon Sep 14 07:57:32 2009 -0700"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@linux-foundation.org",
        "time": "Mon Sep 14 07:57:32 2009 -0700"
      },
      "message": "Merge branch \u0027x86-cpu-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip\n\n* \u0027x86-cpu-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (22 commits)\n  x86: Fix code patching for paravirt-alternatives on 486\n  x86, msr: change msr-reg.o to obj-y, and export its symbols\n  x86: Use hard_smp_processor_id() to get apic id for AMD K8 cpus\n  x86, sched: Workaround broken sched domain creation for AMD Magny-Cours\n  x86, mcheck: Use correct cpumask for shared bank4\n  x86, cacheinfo: Fixup L3 cache information for AMD multi-node processors\n  x86: Fix CPU llc_shared_map information for AMD Magny-Cours\n  x86, msr: Fix msr-reg.S compilation with gas 2.16.1, on 32-bit too\n  x86: Move kernel_fpu_using to irq_fpu_usable in asm/i387.h\n  x86, msr: fix msr-reg.S compilation with gas 2.16.1\n  x86, msr: Export the register-setting MSR functions via /dev/*/msr\n  x86, msr: Create _on_cpu helpers for {rw,wr}msr_safe_regs()\n  x86, msr: Have the _safe MSR functions return -EIO, not -EFAULT\n  x86, msr: CFI annotations, cleanups for msr-reg.S\n  x86, asm: Make _ASM_EXTABLE() usable from assembly code\n  x86, asm: Add 32-bit versions of the combined CFI macros\n  x86, AMD: Disable wrongly set X86_FEATURE_LAHF_LM CPUID bit\n  x86, msr: Rewrite AMD rd/wrmsr variants\n  x86, msr: Add rd/wrmsr interfaces with preset registers\n  x86: add specific support for Intel Atom architecture\n  ...\n"
    },
    {
      "commit": "ae4b688db2432baad379f73fdcac13ec24f603d5",
      "tree": "e367ad761a6835fffeb25694f3308e9315d7ef3c",
      "parents": [
        "f6909f394c2d4a0a71320797df72d54c49c5927e"
      ],
      "author": {
        "name": "Huang Ying",
        "email": "ying.huang@intel.com",
        "time": "Mon Aug 31 13:11:54 2009 +0800"
      },
      "committer": {
        "name": "H. Peter Anvin",
        "email": "hpa@zytor.com",
        "time": "Tue Sep 01 21:39:15 2009 -0700"
      },
      "message": "x86: Move kernel_fpu_using to irq_fpu_usable in asm/i387.h\n\nThis function measures whether the FPU/SSE state can be touched in\ninterrupt context. If the interrupted code is in user space or has no\nvalid FPU/SSE context (CR0.TS \u003d\u003d 1), FPU/SSE state can be used in IRQ\nor soft_irq context too.\n\nThis is used by AES-NI accelerated AES implementation and PCLMULQDQ\naccelerated GHASH implementation.\n\nv3:\n - Renamed to irq_fpu_usable to reflect the purpose of the function.\n\nv2:\n - Renamed to irq_is_fpu_using to reflect the real situation.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nCC: H. Peter Anvin \u003chpa@zytor.com\u003e\nSigned-off-by: H. Peter Anvin \u003chpa@zytor.com\u003e\n"
    },
    {
      "commit": "c9944881acf02b6f25fa62a0441a98b7dc0d7ae6",
      "tree": "264d1e88c293bf8d959d4cbceaa348325618629b",
      "parents": [
        "215ccd6f55a2144bd553e0a3d12e1386f02309fd"
      ],
      "author": {
        "name": "Roland Dreier",
        "email": "rolandd@cisco.com",
        "time": "Wed Jun 24 13:42:40 2009 +0800"
      },
      "committer": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Wed Jun 24 13:42:40 2009 +0800"
      },
      "message": "crypto: aes-ni - Don\u0027t print message with KERN_ERR on old system\n\nWhen the aes-intel module is loaded on a system that does not have the\nAES instructions, it prints\n\n    Intel AES-NI instructions are not detected.\n\nat level KERN_ERR.  Since aes-intel is aliased to \"aes\" it will be tried\nwhenever anything uses AES and spam the console.  This doesn\u0027t match\nexisting practice for how to handle \"no hardware\" when initializing a\nmodule, so downgrade the message to KERN_INFO.\n\nSigned-off-by: Roland Dreier \u003crolandd@cisco.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n"
    },
    {
      "commit": "b6f34d44cb341ad32f08717d1a2c418e6053a031",
      "tree": "220c1cb09bf5a0610cd285c7f36d3cef2dc8e918",
      "parents": [
        "9251b64fb2d2326d28f0e0646a9e4fb8bbb51d8e"
      ],
      "author": {
        "name": "Huang Ying",
        "email": "ying.huang@intel.com",
        "time": "Thu Jun 18 19:44:01 2009 +0800"
      },
      "committer": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Thu Jun 18 19:44:01 2009 +0800"
      },
      "message": "crypto: aes-ni - Remove CRYPTO_TFM_REQ_MAY_SLEEP from fpu template\n\nkernel_fpu_begin/end used preempt_disable/enable, so sleep should be\nprevented between kernel_fpu_begin/end.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n"
    },
    {
      "commit": "9251b64fb2d2326d28f0e0646a9e4fb8bbb51d8e",
      "tree": "2ef7e20387ee2646679c587abef236100684a7d6",
      "parents": [
        "e6efaa025384f86a18814a6b9f4e5d54484ab9ff"
      ],
      "author": {
        "name": "Huang Ying",
        "email": "ying.huang@intel.com",
        "time": "Thu Jun 18 19:41:27 2009 +0800"
      },
      "committer": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Thu Jun 18 19:41:27 2009 +0800"
      },
      "message": "crypto: aes-ni - Do not sleep when using the FPU\n\nBecause AES-NI instructions will touch XMM state, corresponding code\nmust be enclosed within kernel_fpu_begin/end, which used\npreempt_disable/enable. So sleep should be prevented between\nkernel_fpu_begin/end.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n"
    },
    {
      "commit": "e6efaa025384f86a18814a6b9f4e5d54484ab9ff",
      "tree": "e67688f905c8bbea2f35d4e001ef7790676a50e9",
      "parents": [
        "8d8409f773af2cfd52e23e4b138a7d55a31182cd"
      ],
      "author": {
        "name": "Huang Ying",
        "email": "ying.huang@intel.com",
        "time": "Thu Jun 18 19:33:57 2009 +0800"
      },
      "committer": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Thu Jun 18 19:33:57 2009 +0800"
      },
      "message": "crypto: aes-ni - Fix cbc mode IV saving\n\nOriginal implementation of aesni_cbc_dec do not save IV if input\nlength % 4 \u003d\u003d 0. This will make decryption of next block failed.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n"
    },
    {
      "commit": "2cf4ac8beb9dc50a315a6155b7b70e754d511958",
      "tree": "0c4043a1455ab581b4e505604df290acd59ef79e",
      "parents": [
        "150c7e85526e80474b87004f4b420e8834fdeb43"
      ],
      "author": {
        "name": "Huang Ying",
        "email": "ying.huang@intel.com",
        "time": "Sun Mar 29 15:41:20 2009 +0800"
      },
      "committer": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Tue Jun 02 14:04:16 2009 +1000"
      },
      "message": "crypto: aes-ni - Add support for more modes\n\nBecause kernel_fpu_begin() and kernel_fpu_end() operations are too\nslow, the performance gain of general mode implementation + aes-aesni\nis almost all compensated.\n\nThe AES-NI support for more modes are implemented as follow:\n\n- Add a new AES algorithm implementation named __aes-aesni without\n  kernel_fpu_begin/end()\n\n- Use fpu(\u003cmode\u003e(AES)) to provide kenrel_fpu_begin/end() invoking\n\n- Add \u003cmode\u003e(AES) ablkcipher, which uses cryptd(fpu(\u003cmode\u003e(AES))) to\n  defer cryption to cryptd context in soft_irq context.\n\nNow the ctr, lrw, pcbc and xts support are added.\n\nPerformance testing based on dm-crypt shows that cryption time can be\nreduced to 50% of general mode implementation + aes-aesni implementation.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n"
    },
    {
      "commit": "150c7e85526e80474b87004f4b420e8834fdeb43",
      "tree": "66ab693aadaacca850f222ac5fa248fddde3ac32",
      "parents": [
        "505fd21d6138545aa5e96aa738975e6a9deb98a9"
      ],
      "author": {
        "name": "Huang Ying",
        "email": "ying.huang@intel.com",
        "time": "Sun Mar 29 15:39:02 2009 +0800"
      },
      "committer": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Tue Jun 02 14:04:15 2009 +1000"
      },
      "message": "crypto: fpu - Add template for blkcipher touching FPU\n\nBlkcipher touching FPU need to be enclosed by kernel_fpu_begin() and\nkernel_fpu_end(). If they are invoked in cipher algorithm\nimplementation, they will be invoked for each block, so that\nperformance will be hurt, because they are \"slow\" operations. This\npatch implements \"fpu\" template, which makes these operations to be\ninvoked for each request.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n"
    },
    {
      "commit": "54b6a1bd5364aca95cd6ffae00f2b64c6511122c",
      "tree": "b1e288b009df7fefa92ce001d8709b04dd20663f",
      "parents": [
        "1cac2cbc76b9f3fce0d4ccc374e724e7f2533a47"
      ],
      "author": {
        "name": "Huang Ying",
        "email": "ying.huang@intel.com",
        "time": "Sun Jan 18 16:28:34 2009 +1100"
      },
      "committer": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Wed Feb 18 16:48:06 2009 +0800"
      },
      "message": "crypto: aes-ni - Add support to Intel AES-NI instructions for x86_64 platform\n\nIntel AES-NI is a new set of Single Instruction Multiple Data (SIMD)\ninstructions that are going to be introduced in the next generation of\nIntel processor, as of 2009. These instructions enable fast and secure\ndata encryption and decryption, using the Advanced Encryption Standard\n(AES), defined by FIPS Publication number 197.  The architecture\nintroduces six instructions that offer full hardware support for\nAES. Four of them support high performance data encryption and\ndecryption, and the other two instructions support the AES key\nexpansion procedure.\n\nThe white paper can be downloaded from:\n\nhttp://softwarecommunity.intel.com/isn/downloads/intelavx/AES-Instructions-Set_WP.pdf\n\nAES may be used in soft_irq context, but MMX/SSE context can not be\ntouched safely in soft_irq context. So in_interrupt() is checked, if\nin IRQ or soft_irq context, the general x86_64 implementation are used\ninstead.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n"
    },
    {
      "commit": "07bf44f86989f5ed866510374fe761d1903681fb",
      "tree": "b7a4bbd3a66dd6fec0243a12f8569a4ad0fce9da",
      "parents": [
        "109568e110ed67d4be1b28609b9fa00fca97f8eb"
      ],
      "author": {
        "name": "Huang Ying",
        "email": "ying.huang@intel.com",
        "time": "Fri Jan 09 17:25:50 2009 +1100"
      },
      "committer": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Wed Feb 18 16:48:05 2009 +0800"
      },
      "message": "crypto: aes - Export x86 AES encrypt/decrypt functions\n\nIntel AES-NI AES acceleration instructions touch XMM state, to use\nthat in soft_irq context, general x86 AES implementation is used as\nfallback. The first parameter is changed from struct crypto_tfm * to\nstruct crypto_aes_ctx * to make it easier to deal with 16 bytes\nalignment requirement of AES-NI implementation.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n"
    },
    {
      "commit": "109568e110ed67d4be1b28609b9fa00fca97f8eb",
      "tree": "f40a1c6a35bb45abf7edcf8ab55ed75af6d405fb",
      "parents": [
        "8eb2dfac41c71701bb741f496f0cb7b7e4a3c3f6"
      ],
      "author": {
        "name": "Huang Ying",
        "email": "ying.huang@intel.com",
        "time": "Fri Jan 09 16:49:30 2009 +1100"
      },
      "committer": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Wed Feb 18 16:48:04 2009 +0800"
      },
      "message": "crypto: aes - Move key_length in struct crypto_aes_ctx to be the last field\n\nThe Intel AES-NI AES acceleration instructions need key_enc, key_dec\nin struct crypto_aes_ctx to be 16 byte aligned, it make this easier to\nmove key_length to be the last one.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n"
    },
    {
      "commit": "b7e8bdadce6317eb13c13b9451d7114614aa1450",
      "tree": "8a3ed3c64f5a96ce760dba5f79323b3e5b5e9dcc",
      "parents": [
        "faccc4bba160784e834b758f23d598e500ac7108"
      ],
      "author": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Thu Nov 06 16:56:41 2008 +0800"
      },
      "committer": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Thu Dec 25 11:01:37 2008 +1100"
      },
      "message": "crypto: crc32c-intel - Switch to shash\n\nThis patch changes crc32c-intel to the new shash interface.\n\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n"
    },
    {
      "commit": "1c06da81a5d042d5fba67c4c533b16ae62a174ab",
      "tree": "a0f102a16d5d752a67b0a9119c575e689230bf90",
      "parents": [
        "4b24ea971a93f5d0bec34bf7bfd0939f70cfaae6"
      ],
      "author": {
        "name": "Kent Liu",
        "email": "kent.liu@intel.com",
        "time": "Fri Oct 31 16:52:58 2008 +0800"
      },
      "committer": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Thu Dec 25 11:01:18 2008 +1100"
      },
      "message": "crypto: crc32c-intel - Update copyright head\n\nThe original copyright head for crc32c-intel.c is incorrect. Please merge\nthe patch to update it.\n\nSigned-Off-By: Kent Liu \u003ckent.liu@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n"
    },
    {
      "commit": "8cb51ba8e06570a5fff674b3744d12a1b089f2d0",
      "tree": "cb46d2598a22aeffb68827b1d09fe4cb1dcd7612",
      "parents": [
        "f139cfa7cdccd0b315fad098889897b5fcd389b0"
      ],
      "author": {
        "name": "Austin Zhang",
        "email": "austin.zhang@intel.com",
        "time": "Thu Aug 07 09:57:03 2008 +0800"
      },
      "committer": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Fri Aug 29 15:49:50 2008 +1000"
      },
      "message": "crypto: crc32c - Use Intel CRC32 instruction\n\nFrom NHM processor onward, Intel processors can support hardware accelerated\nCRC32c algorithm with the new CRC32 instruction in SSE 4.2 instruction set.\nThe patch detects the availability of the feature, and chooses the most proper\nway to calculate CRC32c checksum.\nByte code instructions are used for compiler compatibility.\nNo MMX / XMM registers is involved in the implementation.\n\nSigned-off-by: Austin Zhang \u003caustin.zhang@intel.com\u003e\nSigned-off-by: Kent Liu \u003ckent.liu@intel.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n"
    },
    {
      "commit": "744b5a28109e6a107c24a1426ee22f92b17995e9",
      "tree": "619ebb94279bd34fb72e10ff77449b11a55511f4",
      "parents": [
        "d5dc392742a9818e2766a63f3533980543e18060"
      ],
      "author": {
        "name": "Sebastian Siewior",
        "email": "sebastian@breakpoint.cc",
        "time": "Tue Mar 11 21:29:47 2008 +0800"
      },
      "committer": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Mon Apr 21 10:19:21 2008 +0800"
      },
      "message": "[CRYPTO] aes-x86-32: Remove unused return code\n\nThe return parameter isn\u0027t used remove it.\n\nSigned-off-by: Sebastian Siewior \u003csebastian@breakpoint.cc\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n"
    },
    {
      "commit": "15e7b4452b72ae890f2fcb027b4c4fa63a1c9a7a",
      "tree": "3612a2135d5193642289f1aed33a83fd3ecca9e5",
      "parents": [
        "b966b54654598aebdac9c57f102d769b36d2f68f"
      ],
      "author": {
        "name": "Sebastian Siewior",
        "email": "sebastian@breakpoint.cc",
        "time": "Mon Jan 14 17:07:57 2008 +1100"
      },
      "committer": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Mon Jan 14 17:07:57 2008 +1100"
      },
      "message": "[CRYPTO] twofish: Merge common glue code\n\nThere is almost no difference between 32 \u0026 64 bit glue code.\n\nSigned-off-by: Sebastian Siewior \u003csebastian@breakpoint.cc\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n"
    },
    {
      "commit": "9a7dafbba47384c330779c75a1546684efaa8c1a",
      "tree": "0fde4a938ebc3c9deb0873b709dc5d2d69ab25c3",
      "parents": [
        "974e4b752ee623854c5dc2bbfc7c7725029ce173"
      ],
      "author": {
        "name": "Tan Swee Heng",
        "email": "thesweeheng@gmail.com",
        "time": "Tue Dec 18 00:04:40 2007 +0800"
      },
      "committer": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Fri Jan 11 08:16:57 2008 +1100"
      },
      "message": "[CRYPTO] salsa20: Add x86-64 assembly version\n\nThis is the x86-64 version of the Salsa20 stream cipher algorithm. The\noriginal assembly code came from\n\u003chttp://cr.yp.to/snuffle/salsa20/amd64-3/salsa20.s\u003e. It has been\nreformatted for clarity.\n\nSigned-off-by: Tan Swee Heng \u003cthesweeheng@gmail.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n"
    },
    {
      "commit": "974e4b752ee623854c5dc2bbfc7c7725029ce173",
      "tree": "e2eb69820a90058a026def6a02a397c082811934",
      "parents": [
        "dadbc53d0bbde0e84c40b9f6bc5c50eb9eb7352a"
      ],
      "author": {
        "name": "Tan Swee Heng",
        "email": "thesweeheng@gmail.com",
        "time": "Mon Dec 10 15:52:56 2007 +0800"
      },
      "committer": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Fri Jan 11 08:16:57 2008 +1100"
      },
      "message": "[CRYPTO] salsa20_i586: Salsa20 stream cipher algorithm (i586 version)\n\nThis patch contains the salsa20-i586 implementation. The original\nassembly code came from\n\u003chttp://cr.yp.to/snuffle/salsa20/x86-pm/salsa20.s\u003e. I have reformatted\nit (added indents) so that it matches the other algorithms in\narch/x86/crypto.\n\nSigned-off-by: Tan Swee Heng \u003cthesweeheng@gmail.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n"
    },
    {
      "commit": "06e1a8f0505426a97292174a959560fd86ea0a3d",
      "tree": "4b002a28d57b35d655d74636b52924a20d4b686b",
      "parents": [
        "28db8e3e38e593d22e2c69942bb1ca7be2a35f05"
      ],
      "author": {
        "name": "Sebastian Siewior",
        "email": "sebastian@breakpoint.cc",
        "time": "Fri Nov 30 00:15:11 2007 +1100"
      },
      "committer": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Fri Jan 11 08:16:24 2008 +1100"
      },
      "message": "[CRYPTO] aes-asm: Merge common glue code\n\n32 bit and 64 bit glue code is using (now) the same\npiece code. This patch unifies them.\n\nSigned-off-by: Sebastian Siewior \u003csebastian@breakpoint.cc\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n"
    },
    {
      "commit": "5157dea8139cf0edc4834d528531e642c0d27e37",
      "tree": "33d14cadc04c60ea95449c6bdc64ec0102eb823d",
      "parents": [
        "b345cee90a3ffec5eca6d6c1c59bd0d1feb453d4"
      ],
      "author": {
        "name": "Sebastian Siewior",
        "email": "sebastian@breakpoint.cc",
        "time": "Sat Nov 10 19:07:16 2007 +0800"
      },
      "committer": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Fri Jan 11 08:16:10 2008 +1100"
      },
      "message": "[CRYPTO] aes-i586: Remove setkey\n\nThe setkey() function can be shared with the generic algorithm.\n\nSigned-off-by: Sebastian Siewior \u003csebastian@breakpoint.cc\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n"
    },
    {
      "commit": "81190b321548bb0bf2d6e1f172695275b0fd1363",
      "tree": "00948bc67bf8cd450595988c4f96a5f9749ee157",
      "parents": [
        "96e82e4551d38e0863b366a7b61185bc4a9946cc"
      ],
      "author": {
        "name": "Sebastian Siewior",
        "email": "sebastian@breakpoint.cc",
        "time": "Thu Nov 08 21:25:04 2007 +0800"
      },
      "committer": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Fri Jan 11 08:16:10 2008 +1100"
      },
      "message": "[CRYPTO] aes-x86-64: Remove setkey\n\nThe setkey() function can be shared with the generic algorithm.\n\nSigned-off-by: Sebastian Siewior \u003csebastian@breakpoint.cc\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n"
    },
    {
      "commit": "89e12654312dddbbdbf17b5adc95b22cb672f947",
      "tree": "b6c90424ece4dae2178c3b3843e37ebf41c8286b",
      "parents": [
        "f1901f1fc710ec0fc482a7c98ee4552874139f39"
      ],
      "author": {
        "name": "Sebastian Siewior",
        "email": "sebastian@breakpoint.cc",
        "time": "Wed Oct 17 23:18:57 2007 +0800"
      },
      "committer": {
        "name": "Herbert Xu",
        "email": "herbert@gondor.apana.org.au",
        "time": "Fri Jan 11 08:16:04 2008 +1100"
      },
      "message": "[CRYPTO] aes: Move common defines into a header file\n\nThis three defines are used in all AES related hardware.\n\nSigned-off-by: Sebastian Siewior \u003csebastian@breakpoint.cc\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n"
    },
    {
      "commit": "9b58aebc73095c045826d891f8e8de6d5bd48c12",
      "tree": "02aa3ca6d2798c9c9597c3c49c7f2e3f696484c6",
      "parents": [
        "bec2c48c2045ca467d07bba54783318b8672bda7"
      ],
      "author": {
        "name": "Thomas Gleixner",
        "email": "tglx@linutronix.de",
        "time": "Tue Oct 23 22:37:23 2007 +0200"
      },
      "committer": {
        "name": "Thomas Gleixner",
        "email": "tglx@linutronix.de",
        "time": "Tue Oct 23 22:37:23 2007 +0200"
      },
      "message": "x86: merge arch/x86/crypto Makefiles\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n\n"
    },
    {
      "commit": "987c75d7170686804b404b7f917b9e4b703702ff",
      "tree": "6c2d871f0cf29afa027ef2fed7aca1c6ed68200a",
      "parents": [
        "9a163ed8e0552fdcffe405d2ea7134819a81456e"
      ],
      "author": {
        "name": "Thomas Gleixner",
        "email": "tglx@linutronix.de",
        "time": "Thu Oct 11 11:17:03 2007 +0200"
      },
      "committer": {
        "name": "Thomas Gleixner",
        "email": "tglx@linutronix.de",
        "time": "Thu Oct 11 11:17:03 2007 +0200"
      },
      "message": "x86_64: move crypto\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n"
    },
    {
      "commit": "9c2019421511a1bc646981d55528334ae46464c0",
      "tree": "12bd39b5201d0afc74dccd8e06464233d3058e58",
      "parents": [
        "af49d41e8c0e6649b3966470aa6319585144f8e8"
      ],
      "author": {
        "name": "Thomas Gleixner",
        "email": "tglx@linutronix.de",
        "time": "Thu Oct 11 11:16:21 2007 +0200"
      },
      "committer": {
        "name": "Thomas Gleixner",
        "email": "tglx@linutronix.de",
        "time": "Thu Oct 11 11:16:21 2007 +0200"
      },
      "message": "i386: move crypto\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n"
    }
  ]
}