)]}'
{
  "log": [
    {
      "commit": "cf9b59e9d3e008591d1f54830f570982bb307a0d",
      "tree": "113478ce8fd8c832ba726ffdf59b82cb46356476",
      "parents": [
        "44504b2bebf8b5823c59484e73096a7d6574471d",
        "f4b87dee923342505e1ddba8d34ce9de33e75050"
      ],
      "author": {
        "name": "Grant Likely",
        "email": "grant.likely@secretlab.ca",
        "time": "Sat May 22 00:36:56 2010 -0600"
      },
      "committer": {
        "name": "Grant Likely",
        "email": "grant.likely@secretlab.ca",
        "time": "Sat May 22 00:36:56 2010 -0600"
      },
      "message": "Merge remote branch \u0027origin\u0027 into secretlab/next-devicetree\n\nMerging in current state of Linus\u0027 tree to deal with merge conflicts and\nbuild failures in vio.c after merge.\n\nConflicts:\n\tdrivers/i2c/busses/i2c-cpm.c\n\tdrivers/i2c/busses/i2c-mpc.c\n\tdrivers/net/gianfar.c\n\nAlso fixed up one line in arch/powerpc/kernel/vio.c to use the\ncorrect node pointer.\n\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n"
    },
    {
      "commit": "4018294b53d1dae026880e45f174c1cc63b5d435",
      "tree": "6db3538eaf91b653381720a6d92f4f15634a93d0",
      "parents": [
        "597b9d1e44e9ba69f2454a5318bbe7a6d5e6930a"
      ],
      "author": {
        "name": "Grant Likely",
        "email": "grant.likely@secretlab.ca",
        "time": "Tue Apr 13 16:13:02 2010 -0700"
      },
      "committer": {
        "name": "Grant Likely",
        "email": "grant.likely@secretlab.ca",
        "time": "Sat May 22 00:10:40 2010 -0600"
      },
      "message": "of: Remove duplicate fields from of_platform_driver\n\n.name, .match_table and .owner are duplicated in both of_platform_driver\nand device_driver.  This patch is a removes the extra copies from struct\nof_platform_driver and converts all users to the device_driver members.\n\nThis patch is a pretty mechanical change.  The usage model doesn\u0027t change\nand if any drivers have been missed, or if anything has been fixed up\nincorrectly, then it will fail with a compile time error, and the fixup\nwill be trivial.  This patch looks big and scary because it touches so\nmany files, but it should be pretty safe.\n\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\nAcked-by: Sean MacLennan \u003csmaclennan@pikatech.com\u003e\n\n"
    },
    {
      "commit": "61c7a080a5a061c976988fd4b844dfb468dda255",
      "tree": "8cb492b73f2755c38a6164d770da34d5af6486a0",
      "parents": [
        "d12d42f744f805a9ccc33cd76f04b237cd83ce56"
      ],
      "author": {
        "name": "Grant Likely",
        "email": "grant.likely@secretlab.ca",
        "time": "Tue Apr 13 16:12:29 2010 -0700"
      },
      "committer": {
        "name": "Grant Likely",
        "email": "grant.likely@secretlab.ca",
        "time": "Tue May 18 16:10:44 2010 -0600"
      },
      "message": "of: Always use \u0027struct device.of_node\u0027 to get device node pointer.\n\nThe following structure elements duplicate the information in\n\u0027struct device.of_node\u0027 and so are being eliminated.  This patch\nmakes all readers of these elements use device.of_node instead.\n\n(struct of_device *)-\u003enode\n(struct dev_archdata *)-\u003eprom_node (sparc)\n(struct dev_archdata *)-\u003eof_node (powerpc \u0026 microblaze)\n\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n"
    },
    {
      "commit": "0b28330e39bbe0ffee4c56b09fc415fcec595ea3",
      "tree": "fcf504879883763557e696eff81427b1ab78f76b",
      "parents": [
        "058276303dbc4ed089c1f7dad0871810b1f5ddf1",
        "caa20d974c86af496b419eef70010e63b7fab7ac"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Mon May 17 16:30:58 2010 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Mon May 17 16:30:58 2010 -0700"
      },
      "message": "Merge branch \u0027ioat\u0027 into dmaengine\n"
    },
    {
      "commit": "058276303dbc4ed089c1f7dad0871810b1f5ddf1",
      "tree": "df26ff701721b2a91d61bd29e48bad7cbcedd746",
      "parents": [
        "4aed79b2818e7330b5d00143e4c20bc6555df91f"
      ],
      "author": {
        "name": "Linus Walleij",
        "email": "linus.walleij@stericsson.com",
        "time": "Mon May 17 16:30:42 2010 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Mon May 17 16:30:42 2010 -0700"
      },
      "message": "DMAENGINE: extend the control command to include an arg\n\nThis adds an argument to the DMAengine control function, so that\nwe can later provide control commands that need some external data\npassed in through an argument akin to the ioctl() operation\nprototype.\n\n[dan.j.williams@intel.com: fix up some missed conversions]\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "5a0e3ad6af8660be21ca98a971cd00f331318c05",
      "tree": "5bfb7be11a03176a87296a43ac6647975c00a1d1",
      "parents": [
        "ed391f4ebf8f701d3566423ce8f17e614cde9806"
      ],
      "author": {
        "name": "Tejun Heo",
        "email": "tj@kernel.org",
        "time": "Wed Mar 24 17:04:11 2010 +0900"
      },
      "committer": {
        "name": "Tejun Heo",
        "email": "tj@kernel.org",
        "time": "Tue Mar 30 22:02:32 2010 +0900"
      },
      "message": "include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h\n\npercpu.h is included by sched.h and module.h and thus ends up being\nincluded when building most .c files.  percpu.h includes slab.h which\nin turn includes gfp.h making everything defined by the two files\nuniversally available and complicating inclusion dependencies.\n\npercpu.h -\u003e slab.h dependency is about to be removed.  Prepare for\nthis change by updating users of gfp and slab facilities include those\nheaders directly instead of assuming availability.  As this conversion\nneeds to touch large number of source files, the following script is\nused as the basis of conversion.\n\n  http://userweb.kernel.org/~tj/misc/slabh-sweep.py\n\nThe script does the followings.\n\n* Scan files for gfp and slab usages and update includes such that\n  only the necessary includes are there.  ie. if only gfp is used,\n  gfp.h, if slab is used, slab.h.\n\n* When the script inserts a new include, it looks at the include\n  blocks and try to put the new include such that its order conforms\n  to its surrounding.  It\u0027s put in the include block which contains\n  core kernel includes, in the same order that the rest are ordered -\n  alphabetical, Christmas tree, rev-Xmas-tree or at the end if there\n  doesn\u0027t seem to be any matching order.\n\n* If the script can\u0027t find a place to put a new include (mostly\n  because the file doesn\u0027t have fitting include block), it prints out\n  an error message indicating which .h file needs to be added to the\n  file.\n\nThe conversion was done in the following steps.\n\n1. The initial automatic conversion of all .c files updated slightly\n   over 4000 files, deleting around 700 includes and adding ~480 gfp.h\n   and ~3000 slab.h inclusions.  The script emitted errors for ~400\n   files.\n\n2. Each error was manually checked.  Some didn\u0027t need the inclusion,\n   some needed manual addition while adding it to implementation .h or\n   embedding .c file was more appropriate for others.  This step added\n   inclusions to around 150 files.\n\n3. The script was run again and the output was compared to the edits\n   from #2 to make sure no file was left behind.\n\n4. Several build tests were done and a couple of problems were fixed.\n   e.g. lib/decompress_*.c used malloc/free() wrappers around slab\n   APIs requiring slab.h to be added manually.\n\n5. The script was run on all .h files but without automatically\n   editing them as sprinkling gfp.h and slab.h inclusions around .h\n   files could easily lead to inclusion dependency hell.  Most gfp.h\n   inclusion directives were ignored as stuff from gfp.h was usually\n   wildly available and often used in preprocessor macros.  Each\n   slab.h inclusion directive was examined and added manually as\n   necessary.\n\n6. percpu.h was updated not to include slab.h.\n\n7. Build test were done on the following configurations and failures\n   were fixed.  CONFIG_GCOV_KERNEL was turned off for all tests (as my\n   distributed build env didn\u0027t work with gcov compiles) and a few\n   more options had to be turned off depending on archs to make things\n   build (like ipr on powerpc/64 which failed due to missing writeq).\n\n   * x86 and x86_64 UP and SMP allmodconfig and a custom test config.\n   * powerpc and powerpc64 SMP allmodconfig\n   * sparc and sparc64 SMP allmodconfig\n   * ia64 SMP allmodconfig\n   * s390 SMP allmodconfig\n   * alpha SMP allmodconfig\n   * um on x86_64 SMP allmodconfig\n\n8. percpu.h modifications were reverted so that it could be applied as\n   a separate patch and serve as bisection point.\n\nGiven the fact that I had only a couple of failures from tests on step\n6, I\u0027m fairly confident about the coverage of this conversion patch.\nIf there is a breakage, it\u0027s likely to be something in one of the arch\nheaders which should be easily discoverable easily on most builds of\nthe specific arch.\n\nSigned-off-by: Tejun Heo \u003ctj@kernel.org\u003e\nGuess-its-ok-by: Christoph Lameter \u003ccl@linux-foundation.org\u003e\nCc: Ingo Molnar \u003cmingo@redhat.com\u003e\nCc: Lee Schermerhorn \u003cLee.Schermerhorn@hp.com\u003e\n"
    },
    {
      "commit": "bca3469205402d9fb14060d255d8786ae2256640",
      "tree": "3b0c7f246fb9a6eafd3a82dd621dd9753589b3f4",
      "parents": [
        "0793448187643b50af89d36b08470baf45a3cab4"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Fri Mar 26 16:52:10 2010 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Fri Mar 26 16:52:10 2010 -0700"
      },
      "message": "dmaengine: provide helper for setting txstate\n\nSimple conditional struct filler to cut out some duplicated code.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "0793448187643b50af89d36b08470baf45a3cab4",
      "tree": "b3313ff58d47e26a8cf707d196177effa1aadfbe",
      "parents": [
        "c3635c78e500a52c9fcd55de381a72928d9e054d"
      ],
      "author": {
        "name": "Linus Walleij",
        "email": "linus.walleij@stericsson.com",
        "time": "Fri Mar 26 16:50:49 2010 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Fri Mar 26 16:50:49 2010 -0700"
      },
      "message": "DMAENGINE: generic channel status v2\n\nConvert the device_is_tx_complete() operation on the\nDMA engine to a generic device_tx_status()operation which\ncan return three states, DMA_TX_RUNNING, DMA_TX_COMPLETE,\nDMA_TX_PAUSED.\n\n[dan.j.williams@intel.com: update for timberdale]\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nAcked-by: Mark Brown \u003cbroonie@opensource.wolfsonmicro.com\u003e\nCc: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nCc: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nCc: Pavel Machek \u003cpavel@ucw.cz\u003e\nCc: Li Yang \u003cleoli@freescale.com\u003e\nCc: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nCc: Paul Mundt \u003clethal@linux-sh.org\u003e\nCc: Ralf Baechle \u003cralf@linux-mips.org\u003e\nCc: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nCc: Magnus Damm \u003cdamm@opensource.se\u003e\nCc: Liam Girdwood \u003clrg@slimlogic.co.uk\u003e\nCc: Joe Perches \u003cjoe@perches.com\u003e\nCc: Roland Dreier \u003crdreier@cisco.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "c3635c78e500a52c9fcd55de381a72928d9e054d",
      "tree": "87403f402227cd8b5572550e70facf81c9eaa0d9",
      "parents": [
        "0f65169b1bf44220308e1ce1f6666ad03ddc27af"
      ],
      "author": {
        "name": "Linus Walleij",
        "email": "linus.walleij@stericsson.com",
        "time": "Fri Mar 26 16:44:01 2010 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Fri Mar 26 16:44:01 2010 -0700"
      },
      "message": "DMAENGINE: generic slave control v2\n\nConvert the device_terminate_all() operation on the\nDMA engine to a generic device_control() operation\nwhich can now optionally support also pausing and\nresuming DMA on a certain channel. Implemented for the\nCOH 901 318 DMAC as an example.\n\n[dan.j.williams@intel.com: update for timberdale]\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nAcked-by: Mark Brown \u003cbroonie@opensource.wolfsonmicro.com\u003e\nCc: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nCc: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nCc: Pavel Machek \u003cpavel@ucw.cz\u003e\nCc: Li Yang \u003cleoli@freescale.com\u003e\nCc: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nCc: Paul Mundt \u003clethal@linux-sh.org\u003e\nCc: Ralf Baechle \u003cralf@linux-mips.org\u003e\nCc: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nCc: Magnus Damm \u003cdamm@opensource.se\u003e\nCc: Liam Girdwood \u003clrg@slimlogic.co.uk\u003e\nCc: Joe Perches \u003cjoe@perches.com\u003e\nCc: Roland Dreier \u003crdreier@cisco.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "76bd061f5c7b7550cdaed68ad6219ea7cee288fc",
      "tree": "5ae663b8bab6bd77cab2b8bc095c0743cc2da138",
      "parents": [
        "6ca3a7a96e91b1aa8c704153c992b191d35b5747"
      ],
      "author": {
        "name": "Steven J. Magnani",
        "email": "steve@digidescorp.com",
        "time": "Sun Feb 28 22:18:16 2010 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sun Feb 28 22:18:16 2010 -0700"
      },
      "message": "fsldma: Fix cookie issues\n\nfsl_dma_update_completed_cookie() appears to calculate the last completed\ncookie incorrectly in the corner case where DMA on cookie 1 is in progress\njust following a cookie wrap.\n\nSigned-off-by: Steven J. Magnani \u003csteve@digidescorp.com\u003e\nAcked-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\n[dan.j.williams@intel.com: fix an integer overflow warning with INT_MAX]\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "6ca3a7a96e91b1aa8c704153c992b191d35b5747",
      "tree": "4700e2eecbae9e33492df683d11e5366f16aeca2",
      "parents": [
        "9ad7bd2944bd979ef4877cd439719be44c5f3b47"
      ],
      "author": {
        "name": "Steven J. Magnani",
        "email": "steve@digidescorp.com",
        "time": "Thu Feb 25 13:39:30 2010 -0600"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sun Feb 28 20:27:42 2010 -0700"
      },
      "message": "fsldma: Fix cookie issues\n\nfsl_dma_tx_submit() only sets the cookie on the first descriptor of a\ntransaction. It should set the cookie on all.\n\nSigned-off-by: Steven J. Magnani \u003csteve@digidescorp.com\u003e\nAcked-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "4b1cf1facca31b7db2a61d8aa2ba40d5a93a0957",
      "tree": "97fd86a2a15a6e482546b7f8b92e47c5a56a2aaa",
      "parents": [
        "9c3a50b7d7ec45da34e73cac66cde12dd6092dd8"
      ],
      "author": {
        "name": "Márton Németh",
        "email": "nm127@freemail.hu",
        "time": "Tue Feb 02 23:41:06 2010 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Feb 02 23:41:06 2010 -0700"
      },
      "message": "dma: make Open Firmware device id constant\n\nThe match_table field of the struct of_device_id is constant in \u003clinux/of_platform.h\u003e\nso it is worth to make the initialization data also constant.\n\nThe semantic match that finds this kind of pattern is as follows:\n(http://coccinelle.lip6.fr/)\n\n// \u003csmpl\u003e\n@r@\ndisable decl_init,const_decl_init;\nidentifier I1, I2, x;\n@@\n\tstruct I1 {\n\t  ...\n\t  const struct I2 *x;\n\t  ...\n\t};\n@s@\nidentifier r.I1, y;\nidentifier r.x, E;\n@@\n\tstruct I1 y \u003d {\n\t  .x \u003d E,\n\t};\n@c@\nidentifier r.I2;\nidentifier s.E;\n@@\n\tconst struct I2 E[] \u003d ... ;\n@depends on !c@\nidentifier r.I2;\nidentifier s.E;\n@@\n+\tconst\n\tstruct I2 E[] \u003d ...;\n// \u003c/smpl\u003e\n\nSigned-off-by: Márton Németh \u003cnm127@freemail.hu\u003e\nCc: Julia Lawall \u003cjulia@diku.dk\u003e\nCc: cocci@diku.dk\n[dan.j.williams@intel.com: resolved conflict with recent fsldma updates]\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "9c3a50b7d7ec45da34e73cac66cde12dd6092dd8",
      "tree": "a16b2dd972ba8ebdd9e6796ad8f0027513316f49",
      "parents": [
        "a1c03319018061304be28d131073ac13a5cb86fb"
      ],
      "author": {
        "name": "Ira Snyder",
        "email": "iws@ovro.caltech.edu",
        "time": "Wed Jan 06 13:34:06 2010 +0000"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Feb 02 14:51:42 2010 -0700"
      },
      "message": "fsldma: major cleanups and fixes\n\nFix locking. Use two queues in the driver, one for pending transacions, and\none for transactions which are actually running on the hardware. Call\ndma_run_dependencies() on descriptor cleanup so that the async_tx API works\ncorrectly.\n\nThere are a number of places throughout the code where lists of descriptors\nare freed in a loop. Create functions to handle this, and use them instead\nof open-coding the loop each time.\n\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "a1c03319018061304be28d131073ac13a5cb86fb",
      "tree": "9d5e2f1d0a66d001e94c8dc34681ac49cf1b66bb",
      "parents": [
        "d3f620b2c4fecdc8e060b70e8d92d29fc01c6126"
      ],
      "author": {
        "name": "Ira Snyder",
        "email": "iws@ovro.caltech.edu",
        "time": "Wed Jan 06 13:34:05 2010 +0000"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Feb 02 14:51:41 2010 -0700"
      },
      "message": "fsldma: rename fsl_chan to chan\n\nThe name fsl_chan seems too long, so it has been shortened to chan. There\nare only a few places where the higher level \"struct dma_chan *chan\" name\nconflicts. These have been changed to \"struct dma_chan *dchan\" instead.\n\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "d3f620b2c4fecdc8e060b70e8d92d29fc01c6126",
      "tree": "652ddf41247241ef3f82419a80e36bb5ee5dd810",
      "parents": [
        "e7a29151de1bd52081f27f149b68074fac0323be"
      ],
      "author": {
        "name": "Ira Snyder",
        "email": "iws@ovro.caltech.edu",
        "time": "Wed Jan 06 13:34:04 2010 +0000"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Feb 02 14:51:41 2010 -0700"
      },
      "message": "fsldma: simplify IRQ probing and handling\n\nThe IRQ probing is needlessly complex. All off the 83xx device trees in\narch/powerpc/boot/dts/ specify 5 interrupts per DMA controller: one for the\ncontroller, and one for each channel. These interrupts are all attached to\nthe same IRQ line.\n\nThis causes an interesting situation if two channels interrupt at the same\ntime. The per-controller handler will handle the first channel, and the\nper-channel handler will handle the remaining channels.\n\nInstead of this mess, we fix the bug in the per-controller handler, and\nmake it handle all channels that generated an interrupt. When a\nper-controller handler is specified in the device tree, we prefer to use\nthe shared handler instead of the per-channel handler.\n\nThe 85xx/86xx controllers do not have a per-controller interrupt, and\ninstead use a per-channel interrupt. This behavior has not been changed.\n\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "e7a29151de1bd52081f27f149b68074fac0323be",
      "tree": "72fa616e49d5ca99e0a1dc79f467e73d071d5dd9",
      "parents": [
        "738f5f7e1ae876448cb7d9c82bea258b69386647"
      ],
      "author": {
        "name": "Ira Snyder",
        "email": "iws@ovro.caltech.edu",
        "time": "Wed Jan 06 13:34:03 2010 +0000"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Feb 02 14:51:41 2010 -0700"
      },
      "message": "fsldma: clean up the OF subsystem routines\n\nThis fixes some errors in the cleanup paths of the OF subsystem, including\nmissing checks for ioremap failing. Also, some variables were renamed for\nbrevity.\n\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "738f5f7e1ae876448cb7d9c82bea258b69386647",
      "tree": "61616b4be922b7e3461f26d0d4dc2f9e5b0ac8cc",
      "parents": [
        "a4f56d4b103d4e5d1a59a9118db0185a6bd1a83b"
      ],
      "author": {
        "name": "Ira Snyder",
        "email": "iws@ovro.caltech.edu",
        "time": "Wed Jan 06 13:34:02 2010 +0000"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Feb 02 14:51:41 2010 -0700"
      },
      "message": "fsldma: rename dest to dst for uniformity\n\nMost functions in the standard library use \"dst\" as a parameter, rather\nthan \"dest\". This renames all use of \"dest\" to \"dst\" to match the usual\nconvention.\n\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "a4f56d4b103d4e5d1a59a9118db0185a6bd1a83b",
      "tree": "aa00d6faf06d168e57c090f1eb05b16596b9a299",
      "parents": [
        "4ce0e953f6286777452bf07c83056342d6b9b257"
      ],
      "author": {
        "name": "Ira Snyder",
        "email": "iws@ovro.caltech.edu",
        "time": "Wed Jan 06 13:34:01 2010 +0000"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Feb 02 14:51:41 2010 -0700"
      },
      "message": "fsldma: rename struct fsl_dma_chan to struct fsldma_chan\n\nThis is the beginning of a cleanup which will change all instances of\n\"fsl_dma\" to \"fsldma\" to match the name of the driver itself.\n\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "4ce0e953f6286777452bf07c83056342d6b9b257",
      "tree": "69a182aaa86cad2e8680132464b122374d7a53b0",
      "parents": [
        "272ca655090978bdaa2630fc44fb2c03da5576fd"
      ],
      "author": {
        "name": "Ira Snyder",
        "email": "iws@ovro.caltech.edu",
        "time": "Wed Jan 06 13:34:00 2010 +0000"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Feb 02 14:51:40 2010 -0700"
      },
      "message": "fsldma: remove unused structure members\n\nRemove some unused members from the fsldma data structures. A few trivial\nuses of struct resource were converted to use the stack rather than keeping\nthe memory allocated for the lifetime of the driver.\n\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "272ca655090978bdaa2630fc44fb2c03da5576fd",
      "tree": "3ad63195951405f4a51c44f1a57f125415d649e6",
      "parents": [
        "abe94c756c08d50566c09a65b9c7fe72f83071c5"
      ],
      "author": {
        "name": "Ira Snyder",
        "email": "iws@ovro.caltech.edu",
        "time": "Wed Jan 06 13:33:59 2010 +0000"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Feb 02 14:51:40 2010 -0700"
      },
      "message": "fsldma: reduce kernel text size\n\nSome of the functions are written in a way where they use multiple reads\nand writes where a single read/write pair could suffice. This shrinks the\nkernel text size measurably, while making the functions easier to\nunderstand.\n\nadd/remove: 0/0 grow/shrink: 1/4 up/down: 4/-196 (-192)\nfunction                                     old     new   delta\nfsl_chan_set_request_count                   120     124      +4\ndma_halt                                     300     272     -28\nfsl_chan_set_src_loop_size                   208     156     -52\nfsl_chan_set_dest_loop_size                  208     156     -52\nfsl_chan_xfer_ld_queue                       500     436     -64\n\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7d",
      "tree": "5f2145c023b9145d1461ecb63c839fd32f762378",
      "parents": [
        "e6c7ecb64e08ef346cb7062b4a5421f00bc602bd"
      ],
      "author": {
        "name": "Ira Snyder",
        "email": "iws@ovro.caltech.edu",
        "time": "Tue Sep 08 17:53:04 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:53:04 2009 -0700"
      },
      "message": "fsldma: Add DMA_SLAVE support\n\nUse the DMA_SLAVE capability of the DMAEngine API to copy/from a\nscatterlist into an arbitrary list of hardware address/length pairs.\n\nThis allows a single DMA transaction to copy data from several different\ndevices into a scatterlist at the same time.\n\nThis also adds support to enable some controller-specific features such as\nexternal start and external pause for a DMA transaction.\n\n[dan.j.williams@intel.com: rebased on tx_list movement]\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nAcked-by: Li Yang \u003cleoli@freescale.com\u003e\nAcked-by: Kumar Gala \u003cgalak@kernel.crashing.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n"
    },
    {
      "commit": "e6c7ecb64e08ef346cb7062b4a5421f00bc602bd",
      "tree": "73424d223391302a9a16df65378d78f25fd05929",
      "parents": [
        "162b96e63e518aa6ff029ce23de12d7f027483bf"
      ],
      "author": {
        "name": "Ira Snyder",
        "email": "iws@ovro.caltech.edu",
        "time": "Tue Sep 08 17:53:04 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:53:04 2009 -0700"
      },
      "message": "fsldma: split apart external pause and request count features\n\nWhen using the Freescale DMA controller in external control mode, both the\nrequest count and external pause bits need to be setup correctly. This was\nbeing done with the same function.\n\nThe 83xx controller lacks the external pause feature, but has a similar\nfeature called external start. This feature requires that the request count\nbits be setup correctly.\n\nSplit the function into two parts, to make it possible to use the external\nstart feature on the 83xx controller.\n\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "eda34234578fd822c950fd06b5c5ff7ac08b3001",
      "tree": "860b3c9d347ddd57e6884f9f1e019370de4d45b1",
      "parents": [
        "e0bd0f8cb09cf3ccac1425f0f3a6705106c4d65c"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:53:02 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:53:02 2009 -0700"
      },
      "message": "fsldma: implement a private tx_list\n\nDrop fsldma\u0027s use of tx_list from struct dma_async_tx_descriptor in\npreparation for removal of this field.\n\nCc: Li Yang \u003cleoli@freescale.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n"
    },
    {
      "commit": "e3d433040ee6077e33d4ad22e2f60a38b085786d",
      "tree": "48fdd979c9062e032b868524082f625d43c97cf6",
      "parents": [
        "daf4219dbcbb2efcd638fcd3c29a622e1c18cc38"
      ],
      "author": {
        "name": "Joe Perches",
        "email": "joe@perches.com",
        "time": "Sun Jun 28 09:26:20 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Jul 22 21:29:16 2009 -0700"
      },
      "message": "drivers/dma/fsldma.c: Remove unnecessary semicolons\n\nSigned-off-by: Joe Perches \u003cjoe@perches.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "43a1a3ed6bf5a1b9ae197b4f5f20033baf19db61",
      "tree": "e14df96fd17ae32d4d3b77d881de7080947e7fb2",
      "parents": [
        "be30b226f2ae618cd719e40267d9923db1db9001"
      ],
      "author": {
        "name": "Ira Snyder",
        "email": "iws@ovro.caltech.edu",
        "time": "Thu May 28 09:26:40 2009 +0000"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jun 16 11:43:40 2009 -0700"
      },
      "message": "fsldma: do not clear bandwidth control bits on the 83xx controller\n\nThe 83xx controller does not support the external pause feature. The bit\nin the mode register that controls external pause on the 85xx controller\nhappens to be part of the bandwidth control settings for the 83xx\ncontroller.\n\nThis patch fixes the driver so that it only clears the external pause bit\nif the hardware is the 85xx controller. When driving the 83xx controller,\nthe bit is left untouched. This follows the existing convention that mode\nregisters settings are not touched unless necessary.\n\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "be30b226f2ae618cd719e40267d9923db1db9001",
      "tree": "3a260d33973214ce50c27d335da37c1eccd04fe3",
      "parents": [
        "a7aea373b4ca428f1be2c1fedd2f26c8e3f2864d"
      ],
      "author": {
        "name": "Ira Snyder",
        "email": "iws@ovro.caltech.edu",
        "time": "Thu May 28 09:20:42 2009 +0000"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jun 16 11:43:00 2009 -0700"
      },
      "message": "fsldma: enable external start for the 83xx controller\n\nThe 83xx controller has external start capability, but lacks external pause\ncapability. Hook up the external start function pointer for the 83xx\ncontroller.\n\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "a7aea373b4ca428f1be2c1fedd2f26c8e3f2864d",
      "tree": "ca05d01f882aee0f5fd54fd6f649ca0ab566f938",
      "parents": [
        "07a2039b8eb0af4ff464efd3dfd95de5c02648c6"
      ],
      "author": {
        "name": "Ira W. Snyder",
        "email": "iws@ovro.caltech.edu",
        "time": "Thu Apr 23 16:17:54 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jun 16 11:29:17 2009 -0700"
      },
      "message": "fsldma: use PCI Read Multiple command\n\nBy default, the Freescale 83xx DMA controller uses the PCI Read Line\ncommand when reading data over the PCI bus. Setting the controller to use\nthe PCI Read Multiple command instead allows the controller to read much\nlarger bursts of data, which provides a drastic speed increase.\n\nThe slowdown due to using PCI Read Line was only observed when a PCI-to-PCI\nbridge was between the devices trying to communicate.\n\nA simple test driver showed an increase from 4MB/sec to 116MB/sec when\nperforming DMA over the PCI bus. Using DMA to transfer between blocks of\nlocal SDRAM showed no change in performance with this patch. The dmatest\ndriver was also used to verify the correctness of the transfers, and showed\nno errors.\n\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nAcked-by: Timur Tabi \u003ctimur@freescale.com\u003e\nAcked-by: Kumar Gala \u003cgalak@kernel.crashing.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "b787f2e2a37a373a045f4d9b9bed941ccff01663",
      "tree": "5134f57fde67dd352c8b021b4d9334dd0b2c0583",
      "parents": [
        "2e077f8e8337e52eef3c39c24c31e103b11a0326"
      ],
      "author": {
        "name": "Kumar Gala",
        "email": "galak@kernel.crashing.org",
        "time": "Wed May 13 16:25:57 2009 -0500"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed May 27 13:40:00 2009 -0700"
      },
      "message": "fsldma: Fix compile warnings\n\nWe we build with dma_addr_t as a 64-bit quantity we get:\n\ndrivers/dma/fsldma.c: In function \u0027fsl_chan_xfer_ld_queue\u0027:\ndrivers/dma/fsldma.c:625: warning: cast to pointer from integer of different size\ndrivers/dma/fsldma.c: In function \u0027fsl_dma_chan_do_interrupt\u0027:\ndrivers/dma/fsldma.c:737: warning: cast to pointer from integer of different size\ndrivers/dma/fsldma.c:737: warning: cast to pointer from integer of different size\ndrivers/dma/fsldma.c: In function \u0027of_fsl_dma_probe\u0027:\ndrivers/dma/fsldma.c:927: warning: cast to pointer from integer of different\n\nSigned-off-by: Kumar Gala \u003cgalak@kernel.crashing.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "2e077f8e8337e52eef3c39c24c31e103b11a0326",
      "tree": "686c9965c8304f5b6d59d3538e989674467ee129",
      "parents": [
        "776c8943f2766f2819fafd88fdfbaf418ecd6e41"
      ],
      "author": {
        "name": "Ira Snyder",
        "email": "iws@ovro.caltech.edu",
        "time": "Fri May 15 09:59:46 2009 -0700"
      },
      "committer": {
        "name": "Li Yang",
        "email": "leoli@freescale.com",
        "time": "Fri May 22 16:54:42 2009 +0800"
      },
      "message": "fsldma: fix memory leak on error path in fsl_dma_prep_memcpy()\n\nWhen preparing a memcpy operation, if the kernel fails to allocate memory\nfor a link descriptor after the first link descriptor has already been\nallocated, then some memory will never be released. Fix the problem by\nwalking the list of allocated descriptors backwards, and freeing the\nallocated descriptors back into the DMA pool.\n\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Li Yang \u003cleoli@freescale.com\u003e\n"
    },
    {
      "commit": "776c8943f2766f2819fafd88fdfbaf418ecd6e41",
      "tree": "6309f7faa86f2c0f7b843b9263ccc13bf379ec64",
      "parents": [
        "bcfb7465c03a8c62c89da374677df56f6b894d44"
      ],
      "author": {
        "name": "Ira Snyder",
        "email": "iws@ovro.caltech.edu",
        "time": "Fri May 15 11:33:20 2009 -0700"
      },
      "committer": {
        "name": "Li Yang",
        "email": "leoli@freescale.com",
        "time": "Fri May 22 16:53:56 2009 +0800"
      },
      "message": "fsldma: snooping is not enabled for last entry in descriptor chain\n\nOn the 83xx controller, snooping is necessary for the DMA controller to\nensure cache coherence with the CPU when transferring to/from RAM.\n\nThe last descriptor in a chain will always have the End-of-Chain interrupt\nbit set, so we can set the snoop bit while adding the End-of-Chain\ninterrupt bit.\n\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Li Yang \u003cleoli@freescale.com\u003e\n"
    },
    {
      "commit": "bcfb7465c03a8c62c89da374677df56f6b894d44",
      "tree": "70194cbfab5fb172bcbf7b8443082a721589f04c",
      "parents": [
        "138ef0185177a6d221d24b6aa8f12d867fbbef90"
      ],
      "author": {
        "name": "Ira Snyder",
        "email": "iws@ovro.caltech.edu",
        "time": "Fri May 15 14:27:16 2009 -0700"
      },
      "committer": {
        "name": "Li Yang",
        "email": "leoli@freescale.com",
        "time": "Fri May 22 16:51:28 2009 +0800"
      },
      "message": "fsldma: fix infinite loop on multi-descriptor DMA chain completion\n\nWhen creating a DMA transaction with multiple descriptors, the async_tx\ncookie is set to 0 for each descriptor in the chain, excluding the last\ndescriptor, whose cookie is set to -EBUSY.\n\nWhen fsl_dma_tx_submit() is run, it only assigns a cookie to the first\ndescriptor. All of the remaining descriptors keep their original value,\nincluding the last descriptor, which is set to -EBUSY.\n\nAfter the DMA completes, the driver will update the last completed cookie\nto be -EBUSY, which is an error code instead of a valid cookie. This causes\ndma_async_is_complete() to always return DMA_IN_PROGRESS.\n\nThis causes the fsldma driver to never cleanup the queue of link\ndescriptors, and the driver will re-run the DMA transaction on the hardware\neach time it receives the End-of-Chain interrupt. This causes an infinite\nloop.\n\nWith this patch, fsl_dma_tx_submit() is changed to assign a cookie to every\ndescriptor in the chain. The rest of the code then works without problems.\n\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Li Yang \u003cleoli@freescale.com\u003e\n"
    },
    {
      "commit": "138ef0185177a6d221d24b6aa8f12d867fbbef90",
      "tree": "4a48ab1154b7533dcaac831ff2dad0e10865efa1",
      "parents": [
        "f47edc6dab11801c2e97088ba7bbce042ded867c"
      ],
      "author": {
        "name": "Ira Snyder",
        "email": "iws@ovro.caltech.edu",
        "time": "Tue May 19 15:42:13 2009 -0700"
      },
      "committer": {
        "name": "Li Yang",
        "email": "leoli@freescale.com",
        "time": "Fri May 22 16:49:17 2009 +0800"
      },
      "message": "fsldma: fix \"DMA halt timeout!\" errors\n\nWhen using the DMA controller from multiple threads at the same time, it is\npossible to get lots of \"DMA halt timeout!\" errors printed to the kernel\nlog.\n\nThis occurs due to a race between fsl_dma_memcpy_issue_pending() and the\ninterrupt handler, fsl_dma_chan_do_interrupt(). Both call the\nfsl_chan_xfer_ld_queue() function, which does not protect against\nconcurrent accesses to dma_halt() and dma_start().\n\nThe existing spinlock is moved to cover the dma_halt() and dma_start()\nfunctions. Testing shows that the \"DMA halt timeout!\" errors disappear.\n\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Li Yang \u003cleoli@freescale.com\u003e\n"
    },
    {
      "commit": "f47edc6dab11801c2e97088ba7bbce042ded867c",
      "tree": "99de3f248d23b997813ba0da149359601ed281e1",
      "parents": [
        "0899d6349c60e4021224b51c8c97f49b829dfefd"
      ],
      "author": {
        "name": "Roel Kluin",
        "email": "roel.kluin@gmail.com",
        "time": "Fri May 22 16:46:52 2009 +0800"
      },
      "committer": {
        "name": "Li Yang",
        "email": "leoli@freescale.com",
        "time": "Fri May 22 16:46:52 2009 +0800"
      },
      "message": "fsldma: fix check on potential fdev-\u003echan[] overflow\n\nFix the check of potential array overflow when using corrupted channel\ndevice tree nodes.\n\nSigned-off-by: Roel Kluin \u003croel.kluin@gmail.com\u003e\nSigned-off-by: Li Yang \u003cleoli@freescale.com\u003e\n"
    },
    {
      "commit": "ccccce229c633a92c42cd1a40c0738d7b0d12644",
      "tree": "a954537ae73f2e03c4431b244796cdc255af7a10",
      "parents": [
        "8d47bae004f062630f69f7f83d098424252e232d"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Mar 25 09:13:24 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Mar 25 09:13:24 2009 -0700"
      },
      "message": "dmaengine: initialize tx_list in dma_async_tx_descriptor_init\n\nCentralize this common initialization (and one case where ipu_idmac is\nduplicating -\u003echan initialization).\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n"
    },
    {
      "commit": "900325a6ce33995688b7a680a34e7698f16f4d72",
      "tree": "8684bc969f3c355307bec56a0c55ad50a1094c0e",
      "parents": [
        "0c33e1ca3d80647f2e72e44524fd21e79214da20"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Mon Mar 02 15:33:46 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Mar 04 16:04:40 2009 -0700"
      },
      "message": "fsldma: fix off by one in dma_halt\n\nPrevent dev_err from firing even if we successfully detected \u0027dma-idle\u0027\nbefore the full 1ms timeout has elapsed.\n\nAcked-by: Roel Kluin \u003croel.kluin@gmail.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n"
    },
    {
      "commit": "169d5f663759ec494aa74a552ce99486235e6e50",
      "tree": "af5947b705412c99a7f24d9f26104a6ee1132605",
      "parents": [
        "6782dfe44acedf1e583d84e9e0d4f966d8e9befa"
      ],
      "author": {
        "name": "Peter Korsgaard",
        "email": "jacmet@sunsite.dk",
        "time": "Wed Jan 14 22:33:31 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Jan 15 23:50:22 2009 -0700"
      },
      "message": "fsldma: print correct IRQ on mpc83xx\n\nThe mpc83xx variant uses a shared IRQ for all channels, so the individual\nchannel nodes don\u0027t have an interrupt property. Fix the code to print the\ncontroller IRQ instead if there isn\u0027t any for the channel.\n\nAcked-by: Timur Tabi \u003ctimur@freescale.com\u003e\nAcked-by: Li Yang \u003cleoli@freescale.com\u003e\nSigned-off-by: Peter Korsgaard \u003cjacmet@sunsite.dk\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n"
    },
    {
      "commit": "6782dfe44acedf1e583d84e9e0d4f966d8e9befa",
      "tree": "508ec1430f22f8b099231b8c8bcd8ef26c940d8b",
      "parents": [
        "d86be86e9aab221089d72399072511f13fe2a771"
      ],
      "author": {
        "name": "Peter Korsgaard",
        "email": "jacmet@sunsite.dk",
        "time": "Wed Jan 14 22:32:58 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Jan 14 22:32:58 2009 -0700"
      },
      "message": "fsldma: check for NO_IRQ in fsl_dma_chan_remove()\n\nThere\u0027s no per-channel IRQ on mpc83xx, so only call free_irq if we have one.\n\nAcked-by: Timur Tabi \u003ctimur@freescale.com\u003e\nAcked-by: Li Yang \u003cleoli@freescale.com\u003e\nSigned-off-by: Peter Korsgaard \u003cjacmet@sunsite.dk\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "6527de6d6d25ebfae7c7572cb7a4ed768e2e20a5",
      "tree": "65d5a2abb226808f9135dda8f9affb6ae8aa4e01",
      "parents": [
        "dd59b8537f6cb53ab863fafad86a5828f1e889a2"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Mon Jan 12 15:18:34 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Mon Jan 12 15:20:42 2009 -0700"
      },
      "message": "fsldma: use a valid \u0027device\u0027 for dma_pool_create\n\nThe dmaengine sysfs implementation was fixed to support proper\nlifetime rules which means that the current:\n\nnew_fsl_chan-\u003edev \u003d \u0026new_fsl_chan-\u003ecommon.dev-\u003edevice;\n\n...retrieves a NULL pointer because new_fsl_chan-\u003ecommon.dev has not\nbeen allocated at this point.  So, set new_fsl_chan-\u003edev to a valid\ndevice.\n\nCc: Li Yang \u003cleoli@freescale.com\u003e\nCc: Zhang Wei \u003czw@zh-kernel.org\u003e\nReported-by: Ira Snyder \u003ciws@ovro.caltech.edu\u003e\nTested-by: Ira Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n"
    },
    {
      "commit": "41d5e59c1299f27983977bcfe3b360600996051c",
      "tree": "f0e80b6fea3af04f266843af97f433198ad535c7",
      "parents": [
        "4fac7fa57cf8001be259688468c825f836daf739"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jan 06 11:38:21 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jan 06 11:38:21 2009 -0700"
      },
      "message": "dmaengine: add a release for dma class devices and dependent infrastructure\n\nResolves:\nWARNING: at drivers/base/core.c:122 device_release+0x4d/0x52()\nDevice \u0027dma0chan0\u0027 does not have a release() function, it is broken and must be fixed.\n\nThe dma_chan_dev object is introduced to gear-match sysfs kobject and\ndmaengine channel lifetimes.  When a channel is removed access to the\nsysfs entries return -ENODEV until the kobject can be released.\n\nThe bulk of the change is updates to existing code to handle the extra\nlayer of indirection between a dma_chan and its struct device.\n\nReported-by: Alexander Beregalov \u003ca.beregalov@gmail.com\u003e\nAcked-by: Stephen Hemminger \u003cshemminger@vyatta.com\u003e\nCc: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n\n"
    },
    {
      "commit": "aa1e6f1a385eb2b04171ec841f3b760091e4a8ee",
      "tree": "1401e7f1e867e5d4a769b648605e0317d25d5ccb",
      "parents": [
        "209b84a88fe81341b4d8d465acc4a67cb7c3feb3"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jan 06 11:38:17 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jan 06 11:38:17 2009 -0700"
      },
      "message": "dmaengine: kill struct dma_client and supporting infrastructure\n\nAll users have been converted to either the general-purpose allocator,\ndma_find_channel, or dma_request_channel.\n\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n\n"
    },
    {
      "commit": "77cd62e8082b9743b59ee1946a4c3ee2e3cd2bce",
      "tree": "8fe08914499988f47f51e74395522e5862b0c31d",
      "parents": [
        "59f647c25a4f27c1e5c84710e0608b36303089f9"
      ],
      "author": {
        "name": "Timur Tabi",
        "email": "timur@freescale.com",
        "time": "Fri Sep 26 17:00:11 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Fri Sep 26 17:00:11 2008 -0700"
      },
      "message": "fsldma: allow Freescale Elo DMA driver to be compiled as a module\n\nModify the Freescale Elo / Elo Plus DMA driver so that it can be compiled as\na module.\n\nThe primary change is to stop treating the DMA controller as a bus, and the\nDMA channels as devices on the bus.  This is because the Open Firmware (OF)\nkernel code does not allow busses to be removed, so although we can call\nof_platform_bus_probe() to probe the DMA channels, there is no\nof_platform_bus_remove().  Instead, the DMA channels are manually probed,\nsimilar to what fsl_elbc_nand.c does.\n\nCc: Scott Wood \u003cscottwood@freescale.com\u003e\nAcked-by: Li Yang \u003cleoli@freescale.com\u003e\nSigned-off-by: Timur Tabi \u003ctimur@freescale.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "59f647c25a4f27c1e5c84710e0608b36303089f9",
      "tree": "654f611ff5b8ff98e7233e6a31ececd2af69b7bb",
      "parents": [
        "6fdb8bd47111d3f94be221082b725ec2dec1d5c7"
      ],
      "author": {
        "name": "Timur Tabi",
        "email": "timur@freescale.com",
        "time": "Tue Sep 23 15:55:56 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 23 15:55:56 2008 -0700"
      },
      "message": "fsldma: remove internal self-test from Freescale Elo DMA driver\n\nThe Freescale Elo DMA driver runs an internal self-test before registering\nthe channels with the DMA engine.  This self-test has a fundemental flaw in\nthat it calls the DMA engine\u0027s callback functions directly before the\nregistration.  However, the registration initializes some variables that the\ncallback functions uses, namely the device struct.\n\nThe code works today because there are two device structs: the one created\nby the DMA engine, and one created by the Open Firmware (OF) subsystem.  The\nself-test currently uses the device struct created by OF.  However, in the\nfuture, some of the device structs created by OF will be eliminated.\nThis means that the self-test will only have access to the device struct\ncreated by the DMA engine.  But this device struct isn\u0027t initialized when\nthe self-test runs, and this causes a kernel panic.\n\nSince there is already a DMA test module (dmatest), the internal self-test\ncode is not useful anyway.  It is extremely unlikely that the test will fail\nin normal usage.  It may have been helpful during development, but not any more.\n\nCc: Kumar Gala \u003cgalak@kernel.crashing.org\u003e\nCc: Li Yang \u003cleoli@freescale.com\u003e\nCc: Scott Wood \u003cscottwood@freescale.com\u003e\nSigned-off-by: Timur Tabi \u003ctimur@freescale.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "848c536a37b8db4e461f14ca15fe29850151c822",
      "tree": "f4a88e92e31de28511e3a3de99200a77d2613dae",
      "parents": [
        "4a776f0aa922a552460192c07b56f4fe9cd82632"
      ],
      "author": {
        "name": "Haavard Skinnemoen",
        "email": "haavard.skinnemoen@atmel.com",
        "time": "Tue Jul 08 11:58:58 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jul 08 11:58:58 2008 -0700"
      },
      "message": "dmaengine: Add dma_client parameter to device_alloc_chan_resources\n\nA DMA controller capable of doing slave transfers may need to know a\nfew things about the slave when preparing the channel. We don\u0027t want\nto add this information to struct dma_channel since the channel hasn\u0027t\nyet been bound to a client at this point.\n\nInstead, pass a reference to the client requesting the channel to the\ndriver\u0027s device_alloc_chan_resources hook so that it can pick the\nnecessary information from the dma_client struct by itself.\n\n[dan.j.williams@intel.com: fixed up fsldma and mv_xor]\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "51ee87f27a1d2c0e08492924f2fb0223c4c704d9",
      "tree": "4c2ede7b480144a1b20441c164761881c3df9f47",
      "parents": [
        "0a2ce2ffc358da96792d514c1024b72c52be9cc1"
      ],
      "author": {
        "name": "Li Yang",
        "email": "leoli@freescale.com",
        "time": "Thu May 29 23:25:45 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jul 08 11:57:45 2008 -0700"
      },
      "message": "fsldma: fix incorrect exit path for initialization\n\nSigned-off-by: Li Yang \u003cleoli@freescale.com\u003e\nAcked-by: Zhang Wei \u003czw@zh-kernel.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "636bdeaa1243327501edfd2a597ed7443eb4239a",
      "tree": "59b894f124e3664ea4a537d7c07c527abdb9c8da",
      "parents": [
        "c4fe15541d0ef5cc8cc1ce43057663851f8fc387"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Apr 17 20:17:26 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Apr 17 13:25:54 2008 -0700"
      },
      "message": "dmaengine: ack to flags: make use of the unused bits in the \u0027ack\u0027 field\n\n\u0027ack\u0027 is currently a simple integer that flags whether or not a client is done\ntouching fields in the given descriptor.  It is effectively just a single bit\nof information.  Converting this to a flags parameter allows the other bits to\nbe put to use to control completion actions, like dma-unmap, and capture\nresults, like xor-zero-sum \u003d\u003d 0.\n\nChanges are one of:\n1/ convert all open-coded -\u003eack manipulations to use async_tx_ack\n   and async_tx_test_ack.\n2/ set the ack bit at prep time where possible\n3/ make drivers store the flags at prep time\n4/ add flags to the device_prep_dma_interrupt prototype\n\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "ce4d65a5db77e1568c82d5151a746f627c4f6ed5",
      "tree": "1f3936d2984fc03125bde025796465f9cada9075",
      "parents": [
        "19242d7233df7d658405d4b7ee1758d21414cfaa"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Apr 17 20:17:26 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Apr 17 13:25:54 2008 -0700"
      },
      "message": "async_tx: kill -\u003edevice_dependency_added\n\nDMA drivers no longer need to be notified of dependency submission\nevents as async_tx_run_dependencies and async_tx_channel_switch will\nhandle the scheduling and execution of dependent operations.\n\n[sfr@canb.auug.org.au: extend this for fsldma]\nAcked-by: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "1c62979ed29a8e2bf9fbe1db101c81a0089676f8",
      "tree": "c652c60d180ec4c5f6fbe17eabeed7b1ac5b601b",
      "parents": [
        "411e23dbe9c5867045f34ba83ee84b31b5b9950c"
      ],
      "author": {
        "name": "Zhang Wei",
        "email": "wei.zhang@freescale.com",
        "time": "Thu Apr 17 20:17:25 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Apr 17 13:22:16 2008 -0700"
      },
      "message": "fsldma: Split the MPC83xx event from MPC85xx and refine irq codes.\n\nSplit MPC83xx EOCDI event from MPC85xx EOLNI event, which is\nalso need to update cookie and start the next transfer.\nThe DMA channel irq handler function code is refined.\nThe patch is tested on MPC8377MDS board.\n\nSigned-off-by: Zhang Wei \u003cwei.zhang@freescale.com\u003e\nSigned-off-by; Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "411e23dbe9c5867045f34ba83ee84b31b5b9950c",
      "tree": "bbdf0ce4244c52e1256082711da17c8775a2f48f",
      "parents": [
        "4b119e21d0c66c22e8ca03df05d9de623d0eb50f"
      ],
      "author": {
        "name": "Zhang Wei",
        "email": "wei.zhang@freescale.com",
        "time": "Thu Apr 17 20:17:25 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Apr 17 13:22:15 2008 -0700"
      },
      "message": "fsldma: Remove CONFIG_FSL_DMA_SELFTEST, keep fsl_dma_self_test() running always.\n\nAlways enabling the fsl_dma_self_test() to ensure the DMA controller\nshould works well after the driver probed.\n\nSigned-off-by: Zhang Wei \u003cwei.zhang@freescale.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "049c9d45531d9825bf737891163a794fca1421c5",
      "tree": "7f3f782cdbc2b467ff7c5714328734b94e27b087",
      "parents": [
        "96ce1b6dc5824cc6027c954b9a2e4717c70e01b5"
      ],
      "author": {
        "name": "Kumar Gala",
        "email": "galak@kernel.crashing.org",
        "time": "Mon Mar 31 11:13:21 2008 -0500"
      },
      "committer": {
        "name": "Kumar Gala",
        "email": "galak@kernel.crashing.org",
        "time": "Mon Mar 31 11:45:41 2008 -0500"
      },
      "message": "[POWERPC] fsldma: Use compatiable binding as spec\n\nDocumentation/powerpc/booting-without-of.txt specifies the\ncompatiables we should bind to for this driver (elo, eloplus).\nUse these instead of the extremely specific \u0027mpc8540\u0027 and \u0027mpc8349\u0027\ncompatiables.\n\nAcked-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nSigned-off-by: Kumar Gala \u003cgalak@kernel.crashing.org\u003e\n"
    },
    {
      "commit": "f79abb627f033c85a6088231f20c85bc4a9bd757",
      "tree": "151538a3a33026ae516606240a13404d1f1e7037",
      "parents": [
        "f920bb6f5fe21047e669381fe4dd346f6a9d3562"
      ],
      "author": {
        "name": "Zhang Wei",
        "email": "wei.zhang@freescale.com",
        "time": "Tue Mar 18 18:45:00 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Mar 18 17:00:59 2008 -0700"
      },
      "message": "fsldma: Fix the DMA halt when using DMA_INTERRUPT async_tx transfer.\n\nThe DMA_INTERRUPT async_tx is a NULL transfer, thus the BCR(count register)\nis 0. When the transfer started with a byte count of zero, the DMA\ncontroller will triger a PE(programming error) event and halt, not a normal\ninterrupt. I add special codes for PE event and DMA_INTERRUPT\nasync_tx testing.\n\nSigned-off-by: Zhang Wei \u003cwei.zhang@freescale.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "9c98718e7371fa781043d5a2e70cecebec048091",
      "tree": "5b89ca3b3a1fc61e12371859f2318d3ec6ed013d",
      "parents": [
        "2187c269ad29510f1d65ec684133d1d3426d0eed"
      ],
      "author": {
        "name": "Zhang Wei",
        "email": "wei.zhang@freescale.com",
        "time": "Thu Mar 13 17:45:28 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Mar 13 10:57:09 2008 -0700"
      },
      "message": "fsldma: Add a completed cookie updated action in DMA finish interrupt.\n\nThe patch \u0027fsldma: do not cleanup descriptors in hardirq context\u0027\n(commit 222ccf9ab838a1ca7163969fabd2cddc10403fb5) removed descriptors\ncleanup function to tasklet but the completed cookie do not updated.\nThus, the DMA controller will get lots of duplicated transfer\ninterrupts. Just make a completed cookie update in interrupt handler.\nAnd keep other cleanup jobs in tasklet function.\n\nTested-by: Sebastian Siewior \u003cbigeasy@linutronix.de\u003e\nSigned-off-by: Zhang Wei \u003cwei.zhang@freescale.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "2187c269ad29510f1d65ec684133d1d3426d0eed",
      "tree": "491d854f31d0080cf74842561a5df9a3f71bcf98",
      "parents": [
        "9b941c6660bae673e27c207f1d20d98ef8ecd450"
      ],
      "author": {
        "name": "Zhang Wei",
        "email": "wei.zhang@freescale.com",
        "time": "Thu Mar 13 17:45:28 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Mar 13 10:57:08 2008 -0700"
      },
      "message": "fsldma: Add device_prep_dma_interrupt support to fsldma.c\n\nThis is a bug that I assigned DMA_INTERRUPT capability to fsldma\nbut missing device_prep_dma_interrupt function. For a bug in\ndmaengine.c the driver passed BUG_ON() checking. The patch fixes it.\n\nSigned-off-by: Zhang Wei \u003cwei.zhang@freescale.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "56822843ff99c88c778a614851328fcbb1503d10",
      "tree": "6b747f0a942451be80e69bac0fcf066530cef15a",
      "parents": [
        "93d74463d018ddf05c169ad399e62e90e0f82fc0"
      ],
      "author": {
        "name": "Zhang Wei",
        "email": "wei.zhang@freescale.com",
        "time": "Thu Mar 13 10:45:27 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Mar 13 10:57:07 2008 -0700"
      },
      "message": "fsldma: Fix fsldma.c warning messages when it\u0027s compiled under PPC64.\n\nThere are warning messages reported by Stephen Rothwell with\nARCH\u003dpowerpc allmodconfig build:\n\ndrivers/dma/fsldma.c: In function \u0027fsl_dma_prep_memcpy\u0027:\ndrivers/dma/fsldma.c:439: warning: comparison of distinct pointer types\nlacks a cast\ndrivers/dma/fsldma.c: In function \u0027fsl_chan_xfer_ld_queue\u0027:\ndrivers/dma/fsldma.c:584: warning: format \u0027%016llx\u0027 expects type \u0027long long\nunsigned int\u0027, but argument 4 has type \u0027dma_addr_t\u0027\ndrivers/dma/fsldma.c: In function \u0027fsl_dma_chan_do_interrupt\u0027:\ndrivers/dma/fsldma.c:668: warning: format \u0027%x\u0027 expects type \u0027unsigned int\u0027,\nbut argument 5 has type \u0027dma_addr_t\u0027\ndrivers/dma/fsldma.c:684: warning: format \u0027%016llx\u0027 expects type \u0027long long\nunsigned int\u0027, but argument 4 has type \u0027dma_addr_t\u0027\ndrivers/dma/fsldma.c:684: warning: format \u0027%016llx\u0027 expects type \u0027long long\nunsigned int\u0027, but argument 5 has type \u0027dma_addr_t\u0027\ndrivers/dma/fsldma.c:701: warning: format \u0027%02x\u0027 expects type \u0027unsigned\nint\u0027, but argument 4 has type \u0027dma_addr_t\u0027\ndrivers/dma/fsldma.c: In function \u0027fsl_dma_self_test\u0027:\ndrivers/dma/fsldma.c:840: warning: format \u0027%d\u0027 expects type \u0027int\u0027, but\nargument 5 has type \u0027size_t\u0027\ndrivers/dma/fsldma.c: In function \u0027of_fsl_dma_probe\u0027:\ndrivers/dma/fsldma.c:1010: warning: format \u0027%08x\u0027 expects type \u0027unsigned\nint\u0027, but argument 5 has type \u0027resource_size_t\u0027\n\nThis patch fixed the above warning messages.\n\nSigned-off-by: Zhang Wei \u003cwei.zhang@freescale.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "222ccf9ab838a1ca7163969fabd2cddc10403fb5",
      "tree": "7d0c6102be13a4de0d6e22254625dc505923bcb7",
      "parents": [
        "173acc7ce8538f1f3040791dc622a92aadc12cf4"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sat Mar 01 07:51:17 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Mar 04 10:16:46 2008 -0700"
      },
      "message": "fsldma: do not cleanup descriptors in hardirq context\n\n\"Cleaning\" descriptors involves calling pending callbacks and clients\nassume that their callback will only ever happen in softirq context.\nDelay cleanup to the tasklet.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nAcked-by: Zhang Wei \u003cwei.zhang@freescale.com\u003e\n"
    },
    {
      "commit": "173acc7ce8538f1f3040791dc622a92aadc12cf4",
      "tree": "f408e415851cf3343af6077287984169958951ad",
      "parents": [
        "976dde010e513a9c7c3117a32b7b015f84b37430"
      ],
      "author": {
        "name": "Zhang Wei",
        "email": "wei.zhang@freescale.com",
        "time": "Sat Mar 01 07:42:48 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Mar 04 10:16:46 2008 -0700"
      },
      "message": "dmaengine: add driver for Freescale MPC85xx DMA controller\n\nThe driver implements DMA engine API for Freescale MPC85xx DMA controller,\nwhich could be used by devices in the silicon.  The driver supports the\nBasic mode of Freescale MPC85xx DMA controller.  The MPC85xx processors\nsupported include MPC8540/60, MPC8555, MPC8548, MPC8641 and so on.\n\nThe MPC83xx(MPC8349, MPC8360) are also supported.\n\n[kamalesh@linux.vnet.ibm.com: build fix]\n[dan.j.williams@intel.com: merge mm fixes, rebase on async_tx-2.6.25]\nSigned-off-by: Zhang Wei \u003cwei.zhang@freescale.com\u003e\nSigned-off-by: Ebony Zhu \u003cebony.zhu@freescale.com\u003e\nAcked-by: Kumar Gala \u003cgalak@gate.crashing.org\u003e\nCc: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\nCc: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nCc: Paul Mackerras \u003cpaulus@samba.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    }
  ]
}