)]}'
{
  "log": [
    {
      "commit": "0b28330e39bbe0ffee4c56b09fc415fcec595ea3",
      "tree": "fcf504879883763557e696eff81427b1ab78f76b",
      "parents": [
        "058276303dbc4ed089c1f7dad0871810b1f5ddf1",
        "caa20d974c86af496b419eef70010e63b7fab7ac"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Mon May 17 16:30:58 2010 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Mon May 17 16:30:58 2010 -0700"
      },
      "message": "Merge branch \u0027ioat\u0027 into dmaengine\n"
    },
    {
      "commit": "c86e1401c9f2ba8d989fa1c4b33d0f0ec3ba8aaf",
      "tree": "f835f2fa83130eecc9e0a2d2e218e6f942bf134e",
      "parents": [
        "2adfc550b6d9646301c810643bc309fa49375987"
      ],
      "author": {
        "name": "Minskey Guo",
        "email": "chaohong_guo@linux.intel.com",
        "time": "Sun May 02 12:52:35 2010 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sun May 02 12:52:35 2010 -0700"
      },
      "message": "ioat: Remove duplicated devm_kzalloc() calls for ioatdma_device\n\nThe memory for ioatdma_device structure is being allocated in\nalloc_ioatdma()\n\nSigned-off-by: Minskey Guo \u003cchaohong_guo@linux.intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "2adfc550b6d9646301c810643bc309fa49375987",
      "tree": "1e1fe80772dc588be2dc294d8b9f371caec3f0b0",
      "parents": [
        "074cc47679f8b0931d7d5384e95822d82768f149"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sat May 01 15:22:56 2010 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sat May 01 15:22:56 2010 -0700"
      },
      "message": "ioat3: disable cacheline-unaligned transfers for raid operations\n\nThere are cases where cacheline-unaligned raid operations can hang the\ndma channel.  Simply disable these operations by increasing the\nalignment constraints published to async_tx.  The raid456 driver always\nissues page aligned requests, so the only in-kernel user of the ioatdma\ndriver that is affected by this change is dmatest.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "074cc47679f8b0931d7d5384e95822d82768f149",
      "tree": "bd4699a1c769553f2bbfa931913352d26c81dc4d",
      "parents": [
        "abb12dfd50c7580d7dcbd581cf6265ba4d01ea7e"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sat May 01 15:22:55 2010 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sat May 01 15:22:55 2010 -0700"
      },
      "message": "ioat2,3: convert to producer/consumer locking\n\nUse separate locks for the descriptor prep (producer) and descriptor\ncleanup (consumer) paths.  Allows the producer path to run concurrently\nwith the cleanup path.  Inspired by Documentation/circular-buffer.txt.\n\nCc: David Howells \u003cdhowells@redhat.com\u003e\nCc: Paul E. McKenney \u003cpaulmck@linux.vnet.ibm.com\u003e\nCc: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "abb12dfd50c7580d7dcbd581cf6265ba4d01ea7e",
      "tree": "d774315dd2620028f1801c8ec0ec31b0e78a536d",
      "parents": [
        "0d0fb0f9c5fddef4a10242fe3337f00f528a3099"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sat May 01 15:22:54 2010 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sat May 01 15:22:54 2010 -0700"
      },
      "message": "ioat: convert to circ_buf\n\nUse the common power-of-2 circular buffer macros.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "5a0e3ad6af8660be21ca98a971cd00f331318c05",
      "tree": "5bfb7be11a03176a87296a43ac6647975c00a1d1",
      "parents": [
        "ed391f4ebf8f701d3566423ce8f17e614cde9806"
      ],
      "author": {
        "name": "Tejun Heo",
        "email": "tj@kernel.org",
        "time": "Wed Mar 24 17:04:11 2010 +0900"
      },
      "committer": {
        "name": "Tejun Heo",
        "email": "tj@kernel.org",
        "time": "Tue Mar 30 22:02:32 2010 +0900"
      },
      "message": "include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h\n\npercpu.h is included by sched.h and module.h and thus ends up being\nincluded when building most .c files.  percpu.h includes slab.h which\nin turn includes gfp.h making everything defined by the two files\nuniversally available and complicating inclusion dependencies.\n\npercpu.h -\u003e slab.h dependency is about to be removed.  Prepare for\nthis change by updating users of gfp and slab facilities include those\nheaders directly instead of assuming availability.  As this conversion\nneeds to touch large number of source files, the following script is\nused as the basis of conversion.\n\n  http://userweb.kernel.org/~tj/misc/slabh-sweep.py\n\nThe script does the followings.\n\n* Scan files for gfp and slab usages and update includes such that\n  only the necessary includes are there.  ie. if only gfp is used,\n  gfp.h, if slab is used, slab.h.\n\n* When the script inserts a new include, it looks at the include\n  blocks and try to put the new include such that its order conforms\n  to its surrounding.  It\u0027s put in the include block which contains\n  core kernel includes, in the same order that the rest are ordered -\n  alphabetical, Christmas tree, rev-Xmas-tree or at the end if there\n  doesn\u0027t seem to be any matching order.\n\n* If the script can\u0027t find a place to put a new include (mostly\n  because the file doesn\u0027t have fitting include block), it prints out\n  an error message indicating which .h file needs to be added to the\n  file.\n\nThe conversion was done in the following steps.\n\n1. The initial automatic conversion of all .c files updated slightly\n   over 4000 files, deleting around 700 includes and adding ~480 gfp.h\n   and ~3000 slab.h inclusions.  The script emitted errors for ~400\n   files.\n\n2. Each error was manually checked.  Some didn\u0027t need the inclusion,\n   some needed manual addition while adding it to implementation .h or\n   embedding .c file was more appropriate for others.  This step added\n   inclusions to around 150 files.\n\n3. The script was run again and the output was compared to the edits\n   from #2 to make sure no file was left behind.\n\n4. Several build tests were done and a couple of problems were fixed.\n   e.g. lib/decompress_*.c used malloc/free() wrappers around slab\n   APIs requiring slab.h to be added manually.\n\n5. The script was run on all .h files but without automatically\n   editing them as sprinkling gfp.h and slab.h inclusions around .h\n   files could easily lead to inclusion dependency hell.  Most gfp.h\n   inclusion directives were ignored as stuff from gfp.h was usually\n   wildly available and often used in preprocessor macros.  Each\n   slab.h inclusion directive was examined and added manually as\n   necessary.\n\n6. percpu.h was updated not to include slab.h.\n\n7. Build test were done on the following configurations and failures\n   were fixed.  CONFIG_GCOV_KERNEL was turned off for all tests (as my\n   distributed build env didn\u0027t work with gcov compiles) and a few\n   more options had to be turned off depending on archs to make things\n   build (like ipr on powerpc/64 which failed due to missing writeq).\n\n   * x86 and x86_64 UP and SMP allmodconfig and a custom test config.\n   * powerpc and powerpc64 SMP allmodconfig\n   * sparc and sparc64 SMP allmodconfig\n   * ia64 SMP allmodconfig\n   * s390 SMP allmodconfig\n   * alpha SMP allmodconfig\n   * um on x86_64 SMP allmodconfig\n\n8. percpu.h modifications were reverted so that it could be applied as\n   a separate patch and serve as bisection point.\n\nGiven the fact that I had only a couple of failures from tests on step\n6, I\u0027m fairly confident about the coverage of this conversion patch.\nIf there is a breakage, it\u0027s likely to be something in one of the arch\nheaders which should be easily discoverable easily on most builds of\nthe specific arch.\n\nSigned-off-by: Tejun Heo \u003ctj@kernel.org\u003e\nGuess-its-ok-by: Christoph Lameter \u003ccl@linux-foundation.org\u003e\nCc: Ingo Molnar \u003cmingo@redhat.com\u003e\nCc: Lee Schermerhorn \u003cLee.Schermerhorn@hp.com\u003e\n"
    },
    {
      "commit": "bca3469205402d9fb14060d255d8786ae2256640",
      "tree": "3b0c7f246fb9a6eafd3a82dd621dd9753589b3f4",
      "parents": [
        "0793448187643b50af89d36b08470baf45a3cab4"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Fri Mar 26 16:52:10 2010 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Fri Mar 26 16:52:10 2010 -0700"
      },
      "message": "dmaengine: provide helper for setting txstate\n\nSimple conditional struct filler to cut out some duplicated code.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "0793448187643b50af89d36b08470baf45a3cab4",
      "tree": "b3313ff58d47e26a8cf707d196177effa1aadfbe",
      "parents": [
        "c3635c78e500a52c9fcd55de381a72928d9e054d"
      ],
      "author": {
        "name": "Linus Walleij",
        "email": "linus.walleij@stericsson.com",
        "time": "Fri Mar 26 16:50:49 2010 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Fri Mar 26 16:50:49 2010 -0700"
      },
      "message": "DMAENGINE: generic channel status v2\n\nConvert the device_is_tx_complete() operation on the\nDMA engine to a generic device_tx_status()operation which\ncan return three states, DMA_TX_RUNNING, DMA_TX_COMPLETE,\nDMA_TX_PAUSED.\n\n[dan.j.williams@intel.com: update for timberdale]\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nAcked-by: Mark Brown \u003cbroonie@opensource.wolfsonmicro.com\u003e\nCc: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nCc: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nCc: Pavel Machek \u003cpavel@ucw.cz\u003e\nCc: Li Yang \u003cleoli@freescale.com\u003e\nCc: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nCc: Paul Mundt \u003clethal@linux-sh.org\u003e\nCc: Ralf Baechle \u003cralf@linux-mips.org\u003e\nCc: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nCc: Magnus Damm \u003cdamm@opensource.se\u003e\nCc: Liam Girdwood \u003clrg@slimlogic.co.uk\u003e\nCc: Joe Perches \u003cjoe@perches.com\u003e\nCc: Roland Dreier \u003crdreier@cisco.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "52cf25d0ab7f78eeecc59ac652ed5090f69b619e",
      "tree": "031d1ffb3890bd69c0260c864c512e0be62ac05c",
      "parents": [
        "6c1733aca0b48db4d0e660d54976a1cca25b5eaf"
      ],
      "author": {
        "name": "Emese Revfy",
        "email": "re.emese@gmail.com",
        "time": "Tue Jan 19 02:58:23 2010 +0100"
      },
      "committer": {
        "name": "Greg Kroah-Hartman",
        "email": "gregkh@suse.de",
        "time": "Sun Mar 07 17:04:49 2010 -0800"
      },
      "message": "Driver core: Constify struct sysfs_ops in struct kobj_type\n\nConstify struct sysfs_ops.\n\nThis is part of the ops structure constification\neffort started by Arjan van de Ven et al.\n\nBenefits of this constification:\n\n * prevents modification of data that is shared\n   (referenced) by many other structure instances\n   at runtime\n\n * detects/prevents accidental (but not intentional)\n   modification attempts on archs that enforce\n   read-only kernel data at runtime\n\n * potentially better optimized code as the compiler\n   can assume that the const data cannot be changed\n\n * the compiler/linker move const data into .rodata\n   and therefore exclude them from false sharing\n\nSigned-off-by: Emese Revfy \u003cre.emese@gmail.com\u003e\nAcked-by: David Teigland \u003cteigland@redhat.com\u003e\nAcked-by: Matt Domsch \u003cMatt_Domsch@dell.com\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nAcked-by: Hans J. Koch \u003chjk@linutronix.de\u003e\nAcked-by: Pekka Enberg \u003cpenberg@cs.helsinki.fi\u003e\nAcked-by: Jens Axboe \u003cjens.axboe@oracle.com\u003e\nAcked-by: Stephen Hemminger \u003cshemminger@vyatta.com\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n"
    },
    {
      "commit": "984b3f5746ed2cde3d184651dabf26980f2b66e5",
      "tree": "87dc2162b4778b0075874d9592384530022e15a4",
      "parents": [
        "e3cb91ce1ac1d93a7cc6f81bb5247f7602b572bb"
      ],
      "author": {
        "name": "Akinobu Mita",
        "email": "akinobu.mita@gmail.com",
        "time": "Fri Mar 05 13:41:37 2010 -0800"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@linux-foundation.org",
        "time": "Sat Mar 06 11:26:23 2010 -0800"
      },
      "message": "bitops: rename for_each_bit() to for_each_set_bit()\n\nRename for_each_bit to for_each_set_bit in the kernel source tree.  To\npermit for_each_clear_bit(), should that ever be added.\n\nThe patch includes a macro to map the old for_each_bit() onto the new\nfor_each_set_bit().  This is a (very) temporary thing to ease the migration.\n\n[akpm@linux-foundation.org: add temporary for_each_bit()]\nSuggested-by: Alexey Dobriyan \u003cadobriyan@gmail.com\u003e\nSuggested-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Akinobu Mita \u003cakinobu.mita@gmail.com\u003e\nCc: \"David S. Miller\" \u003cdavem@davemloft.net\u003e\nCc: Russell King \u003crmk@arm.linux.org.uk\u003e\nCc: David Woodhouse \u003cdwmw2@infradead.org\u003e\nCc: Artem Bityutskiy \u003cdedekind@infradead.org\u003e\nCc: Stephen Rothwell \u003csfr@canb.auug.org.au\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n"
    },
    {
      "commit": "dd58ffcf5a5352fc10820c8ffbcd5fed416a2c3a",
      "tree": "f36172b40f9f3fc2c646f70da40e01705399b6b8",
      "parents": [
        "aa4d72ae946a4fa40486b871717778734184fa29",
        "56a5d3cf21c71963c8fc506e9b9d3f71641d9c71"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Mar 03 21:22:21 2010 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Mar 03 21:22:21 2010 -0700"
      },
      "message": "Merge branch \u0027coh\u0027 into dmaengine\n"
    },
    {
      "commit": "aa4d72ae946a4fa40486b871717778734184fa29",
      "tree": "5c98641f00a7866e28a364861b9af9b6df606fdd",
      "parents": [
        "b9cc98697d1ca35a86bbb708acc6d93993c28f0f"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Mar 03 21:21:13 2010 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Mar 03 21:21:13 2010 -0700"
      },
      "message": "ioat: cleanup -\u003etimer_fn() and -\u003ecleanup_fn() prototypes\n\nIf the calling convention of -\u003etimer_fn() and -\u003ecleanup_fn() are unified\nacross hardware versions we can drop parameters to ioat_init_channel() and\nunify ioat_is_dma_complete() implementations.\n\nBoth -\u003etimer_fn() and -\u003ecleanup_fn() are modified to expect a struct\ndma_chan pointer.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "b9cc98697d1ca35a86bbb708acc6d93993c28f0f",
      "tree": "22bace58c86068483209b8b2d9a2b6238eb0c179",
      "parents": [
        "aa75db0080603bae27961c0502812dfd0f522bb3"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Mar 03 21:21:13 2010 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Mar 03 21:21:13 2010 -0700"
      },
      "message": "ioat3: interrupt coalescing\n\nThe hardware automatically disables further interrupts after each event\nuntil rearmed.  This allows a delay to be injected between the occurence\nof the interrupt and the running of the cleanup routine.  The delay is\nscaled by the descriptor backlog and then written to the INTRDELAY\nregister which specifies the number of microseconds to hold off\ninterrupt delivery after an interrupt event occurs.  According to\npowertop this reduces the interrupt rate from ~5000 intr/s to ~150\nintr/s per without affecting throughput (simple dd to a raid6 array).\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "aa75db0080603bae27961c0502812dfd0f522bb3",
      "tree": "3e7fbb0ef4415c9f36107a81378f00bba6db9440",
      "parents": [
        "281befa5592b0c5f9a3856b5666c62ac66d3d9ee"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Mar 03 21:21:10 2010 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Mar 03 21:21:10 2010 -0700"
      },
      "message": "ioat: close potential BUG_ON race in the descriptor cleanup path\n\nSince ioat_cleanup_preamble() and the update of the last completed\ndescriptor are not synchronized there is a chance that two cleanup threads\ncan see descriptors to clean.  If the first cleans up all pending\ndescriptors then the second will trigger the BUG_ON.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "281befa5592b0c5f9a3856b5666c62ac66d3d9ee",
      "tree": "a0e7ca560fd1f2c43d3352786b0a5317af97ccf7",
      "parents": [
        "b372ec2d900a5b50e47ef9e9624536ad146236be"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Mar 03 11:47:43 2010 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Mar 03 11:47:43 2010 -0700"
      },
      "message": "ioat2: kill pending flag\n\nThe pending \u003d\u003d 2 case no longer exists in the driver so, we can use\nioat2_ring_pending() outside the lock to determine if there might be any\ndescriptors in the ring that the hardware has not seen.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "b372ec2d900a5b50e47ef9e9624536ad146236be",
      "tree": "3c9efbdcac54e7b924057d8b60e223058195d768",
      "parents": [
        "773d9e2d8dbf02cfaf65786cf9100eef02c9fda4"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Mar 03 11:47:42 2010 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Mar 03 11:47:42 2010 -0700"
      },
      "message": "ioat3: use ioat2_quiesce()\n\nReplace open coded ioat2_quiesce() call in ioat3_restart_channel\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "773d9e2d8dbf02cfaf65786cf9100eef02c9fda4",
      "tree": "f4cdd84bb7ebd3ae8340f02c3c1e0e641601f88c",
      "parents": [
        "0fb6f739bb612bc989d295056877374b749e721b"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Mar 03 11:47:42 2010 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Mar 03 11:47:42 2010 -0700"
      },
      "message": "ioat3: cleanup, don\u0027t enable DCA completion writes\n\nWe already disallow raid operations while DCA is globally enabled, so\nhaving it locally enabled is a nop and confusing when reading the code.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "7e55a70c5b9a57c12f49c44b0847c9343d4f54e4",
      "tree": "e9ba9f5896d8e97e76894f23641afd3abce5aac4",
      "parents": [
        "adef477268ff5ddd0195611dc7e26d7a879fefe1"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Jan 13 13:33:12 2010 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Feb 02 22:57:34 2010 -0700"
      },
      "message": "ioat: fix infinite timeout checking in ioat2_quiesce\n\nFix typo in ioat2_quiesce. check \u0027tmo\u0027 is zero, not \u0027end\u0027.  Also applies\nto 2.6.32.3\n\nCc: \u003cstable@kernel.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "a6d52d70677e99bdb89b6921c265d0a58c22e597",
      "tree": "9310005efbfa5d3141c1bf9d9ed5464377419f1e",
      "parents": [
        "e02a0e47a3f061c1a53fc4376332a988ec047e8a"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sat Dec 19 15:36:02 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sat Dec 19 15:36:02 2009 -0700"
      },
      "message": "ioat2,3: put channel hardware in known state at init\n\nPut the ioat2 and ioat3 state machines in the halted state with all\nerrors cleared.\n\nThe ioat1 init path is not disturbed for stability, there are no\nreported ioat1 initiaization issues.\n\nCc: \u003cstable@kernel.org\u003e\nReported-by: Roland Dreier \u003crdreier@cisco.com\u003e\nTested-by: Roland Dreier \u003crdreier@cisco.com\u003e\nAcked-by: Simon Horman \u003chorms@verge.net.au\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "cd78809f6191485a90ea6c92c2b58900ab5c156f",
      "tree": "d17a0e30178ec8ae78e04df69ca3d7b280054361",
      "parents": [
        "22763c5cf3690a681551162c15d34d935308c8d7"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Dec 17 13:52:39 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Dec 17 13:52:39 2009 -0700"
      },
      "message": "ioat3: fix p-disabled q-continuation\n\nWhen continuing a pq calculation the driver needs 3 extra sources.  The\ndriver can perform a 3 source calculation with a single descriptor, but\nneeds an extended descriptor to process up to 8 sources in one\noperation.  However, in the p-disabled case only one extra source is\nneeded.  When continuing a p-disabled operation there are occasions\n(i.e. 0 \u003c src_cnt % 8 \u003c 3) where the tail operation does not need an\nextended descriptor.  Properly account for this fact otherwise invalid\n\u0027dmacount\u0027 values will be written to hardware usually causing the\nchannel to halt with \u0027invalid descriptor\u0027 errors.\n\nCc: \u003cstable@kernel.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "49954c1567cb0d70d28bb5512d471dc5bd4e2c3f",
      "tree": "c64b4585518028b5c8ae749b93d9f560d536f649",
      "parents": [
        "7b3cc2b1fc2066391e498f3387204908c4eced21"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Nov 19 17:11:03 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Nov 19 23:21:03 2009 -0700"
      },
      "message": "ioat3: fix pq completion versus channel deallocation race\n\nThe completion of a pq operation is notified with a null descriptor\nappended to the end of the chain.  This descriptor needs to be visible\nto dma clients otherwise the client is precluded from ensuring all\noperations are quiesced before freeing channel resources, i.e. due to\ndescriptor polling it may get the completion notification ahead of the\ninterrupt delivered by the null descriptor.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "7b3cc2b1fc2066391e498f3387204908c4eced21",
      "tree": "8a2bc28955710c580201046d04843773cb7d87a1",
      "parents": [
        "4499a24dec00e037da7d09caccad45e7594a9c19"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Nov 19 17:10:37 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Nov 19 23:21:03 2009 -0700"
      },
      "message": "async_tx: build-time toggling of async_{syndrome,xor}_val dma support\n\nioat3.2 does not support asynchronous error notifications which makes\nthe driver experience latencies when non-zero pq validate results are\nexpected.  Provide a mechanism for turning off async_xor_val and\nasync_syndrome_val via Kconfig.  This approach is generally useful for\nany driver that specifies ASYNC_TX_DISABLE_CHANNEL_SWITCH and would like\nto force the async_tx api to fall back to the synchronous path for\ncertain operations.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n"
    },
    {
      "commit": "b57014def9afc2bd8a62299d2f51b77dad5ae0c7",
      "tree": "b196078bed3b982475bd0dd22ce0ce8aad2f517a",
      "parents": [
        "de581b65f6fe78168affa552c3bd15b8c80ed614"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Nov 19 17:10:07 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Nov 19 23:21:03 2009 -0700"
      },
      "message": "ioat2,3: report all uncorrectable errors\n\nModify is_ioat_bug() to catch all errors that are uncorrectable, or not\ncurrently handled.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "de581b65f6fe78168affa552c3bd15b8c80ed614",
      "tree": "b980e64cf31ad79c489838310be2e13e626dd05c",
      "parents": [
        "6f82b83b7a56bc6e9dd6d7b93531dde6027c5309"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Nov 19 17:08:45 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Nov 19 17:08:45 2009 -0700"
      },
      "message": "ioat3: specify valid address for disabled-Q or disabled-P\n\nAlthough disabled, hardware still checks address validity, so duplicate\nthe known address.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "6f82b83b7a56bc6e9dd6d7b93531dde6027c5309",
      "tree": "d6f9fc6064e60711e1d041a48d8ff0927ca819e7",
      "parents": [
        "228c4f5cfbf1cda411d9aa7204a612a63c89b1e8"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Nov 19 17:07:57 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Nov 19 17:07:57 2009 -0700"
      },
      "message": "ioat2,3: disable asynchronous error notifications\n\nError interrupts and error completions may cause channel hangs, so\npoll the channel status register after a timeout.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "228c4f5cfbf1cda411d9aa7204a612a63c89b1e8",
      "tree": "0920f900732ce598fef2cdc0c4899860534e837d",
      "parents": [
        "e22dde9904c2d26a522f1a2b89854a8238bf0933"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Nov 19 17:07:10 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Nov 19 17:07:10 2009 -0700"
      },
      "message": "ioat3: dca and raid operations are incompatible\n\nRAID operations cause a system hang on platforms with DCA\n(Direct-Cache-Access) enabled.  So turn off RAID capabilities in this\ncase.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "e22dde9904c2d26a522f1a2b89854a8238bf0933",
      "tree": "dbb3b1f2d1d1ddafb3c004819c25c31a73811ae8",
      "parents": [
        "b419148e567728f6af0c3b01965c1cc141e3e13a"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Nov 17 11:34:31 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Nov 17 11:34:31 2009 -0700"
      },
      "message": "ioat: silence \"dca disabled\" messages\n\nTurning off dca is not an \"error\", and the dca-enabled state can be\nviewed from sysfs.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "cdef57dbb618608bfffda2fc32c8d0a4012a1d3a",
      "tree": "e58d3301ea4fb264f713c4602c25e6451d4e6707",
      "parents": [
        "f477f5b3316f39c841aa121a219b82b3a56e7da7"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Mon Sep 21 09:22:29 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Mon Sep 21 09:22:29 2009 -0700"
      },
      "message": "ioat3: fix uninitialized var warnings\n\ndrivers/dma/ioat/dma_v3.c: In function \u0027ioat3_prep_memset_lock\u0027:\ndrivers/dma/ioat/dma_v3.c:439: warning: \u0027fill\u0027 may be used uninitialized in this function\ndrivers/dma/ioat/dma_v3.c:437: warning: \u0027desc\u0027 may be used uninitialized in this function\ndrivers/dma/ioat/dma_v3.c: In function \u0027__ioat3_prep_xor_lock\u0027:\ndrivers/dma/ioat/dma_v3.c:489: warning: \u0027xor\u0027 may be used uninitialized in this function\ndrivers/dma/ioat/dma_v3.c:486: warning: \u0027desc\u0027 may be used uninitialized in this function\ndrivers/dma/ioat/dma_v3.c: In function \u0027__ioat3_prep_pq_lock\u0027:\ndrivers/dma/ioat/dma_v3.c:631: warning: \u0027pq\u0027 may be used uninitialized in this function\ndrivers/dma/ioat/dma_v3.c:628: warning: \u0027desc\u0027 may be used uninitialized in this function\n\ngcc-4.0, unlike gcc-4.3, does not see that these variables are\ninitialized before use.  Convert the descriptor loops to do-while make\nthis initialization apparent.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "f477f5b3316f39c841aa121a219b82b3a56e7da7",
      "tree": "392476186ece4084f85b3c5227853d92ecae79a6",
      "parents": [
        "1b6df6930994d5d027375b07ac9da63644eb5758"
      ],
      "author": {
        "name": "Andrew Morton",
        "email": "akpm@linux-foundation.org",
        "time": "Mon Sep 21 09:17:58 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Mon Sep 21 09:17:58 2009 -0700"
      },
      "message": "drivers/dma/ioat/dma_v2.c: fix warnings\n\ndrivers/dma/ioat/dma_v2.c: In function \u0027ioat2_dma_prep_memcpy_lock\u0027:\ndrivers/dma/ioat/dma_v2.c:680: warning: \u0027hw\u0027 may be used uninitialized in this function\ndrivers/dma/ioat/dma_v2.c:681: warning: \u0027desc\u0027 may be used uninitialized in this function\n\nCc: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "376ec37667b510453f5a62fcd95d762786e6a0a9",
      "tree": "7352166b585463ce53633e379b96196dff72014f",
      "parents": [
        "6c910a78e495b4c1778a8b136b37fe3c05712730"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Sep 16 15:16:50 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Sep 16 15:16:50 2009 -0700"
      },
      "message": "ioat2: clarify ring size limits\n\nWith the addition of ioat_max_alloc_order it is not clear what the\nmaximum allocation order is, so document that in the modinfo.  Also take\nan opportunity to kill a stray semicolon.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "3208ca52f3bfa36914c44db207d0a34071f9897f",
      "tree": "fb28779eb8ec74fd650f2df085f507353fcd79ce",
      "parents": [
        "1a5aeeecd550ee4344cfba1791f1134739b16dc6"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Sep 10 11:27:36 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Sep 10 11:27:36 2009 -0700"
      },
      "message": "ioat: driver version 4.0\n\nA new ring implementation and the addition of raid functionality\nconstitutes a bump in the driver major version number.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "1a5aeeecd550ee4344cfba1791f1134739b16dc6",
      "tree": "0b2f1f104d7dbff82130ea1d41c037a74fa6753e",
      "parents": [
        "9a8de639f35ca3951b910d5e3a2f92f4cf3afc8f"
      ],
      "author": {
        "name": "Maciej Sosnowski",
        "email": "maciej.sosnowski@intel.com",
        "time": "Thu Sep 10 15:05:58 2009 +0200"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Sep 10 10:00:05 2009 -0700"
      },
      "message": "dca: registering requesters in multiple dca domains\n\nThis patch enables DCA support on multiple-IOH/multiple-IIO architectures.\nIt modifies dca module by replacing single dca_providers list\nwith dca_domains list, each domain containing separate list of providers.\nThis approach lets dca driver manage multiple domains, i.e. sets of providers\nand requesters mapped back to the same PCI root complex device.\nThe driver takes care to register each requester to a provider\nfrom the same domain.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\n"
    },
    {
      "commit": "bbb20089a3275a19e475dbc21320c3742e3ca423",
      "tree": "216fdc1cbef450ca688135c5b8969169482d9a48",
      "parents": [
        "3e48e656903e9fd8bc805c6a2c4264d7808d315b",
        "657a77fa7284d8ae28dfa48f1dc5d919bf5b2843"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:55:21 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:55:21 2009 -0700"
      },
      "message": "Merge branch \u0027dmaengine\u0027 into async-tx-next\n\nConflicts:\n\tcrypto/async_tx/async_xor.c\n\tdrivers/dma/ioat/dma_v2.h\n\tdrivers/dma/ioat/pci.c\n\tdrivers/md/raid5.c\n"
    },
    {
      "commit": "162b96e63e518aa6ff029ce23de12d7f027483bf",
      "tree": "532191d0cef7cf975b70a07b1c69a293d6f552f7",
      "parents": [
        "0803172778901e24a75ab074798d98c2b7411559"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:53:04 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:53:04 2009 -0700"
      },
      "message": "ioat2,3: cacheline align software descriptor allocations\n\nAll the necessary fields for handling an ioat2,3 ring entry can fit into\none cacheline.  Move -\u003elen prior to -\u003etxd in struct ioat_ring_ent, and\nmove allocation of these entries to a hw-cache-aligned kmem cache to\nreduce the number of cachelines dirtied for descriptor management.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "ea25968a32a621b02c3715d6b649f0c6ef53c24e",
      "tree": "8da75c38c0ac0690eb03e89ccf146d062ba4d855",
      "parents": [
        "308136d1abcb2d759bac40ed4f5d42ac4af59d8b"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:53:02 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:53:02 2009 -0700"
      },
      "message": "ioat: implement a private tx_list\n\nDrop ioatdma\u0027s use of tx_list from struct dma_async_tx_descriptor in\npreparation for removal of this field.\n\nCc: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n"
    },
    {
      "commit": "a6417dd58d6832f123f36c6f22c63ec1ab62ce1c",
      "tree": "b8aa7273a874904396c79099facd104eeb4074e0",
      "parents": [
        "6506cbca6b5b36d682bd39afcbf3f575c81dddb6"
      ],
      "author": {
        "name": "Roland Dreier",
        "email": "rdreier@cisco.com",
        "time": "Tue Sep 08 17:43:03 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:43:03 2009 -0700"
      },
      "message": "I/OAT: Convert to PCI_VDEVICE()\n\nTrivial cleanup to make the PCI ID table easier to read.\n\n[dan.j.williams@intel.com: extended to v3.2 devices]\nSigned-off-by: Roland Dreier \u003crolandd@cisco.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "6506cbca6b5b36d682bd39afcbf3f575c81dddb6",
      "tree": "ea82de689e7712eaa76209afcaf9a8678dac9f3f",
      "parents": [
        "e3232714d465c42ac631929b990f5e35e2d8a955"
      ],
      "author": {
        "name": "Roland Dreier",
        "email": "rdreier@cisco.com",
        "time": "Tue Sep 08 17:43:03 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:43:03 2009 -0700"
      },
      "message": "Add MODULE_DEVICE_TABLE() so ioatdma module is autoloaded\n\nThe ioatdma module is missing aliases for the PCI devices it supports,\nso it is not autoloaded on boot.  Add a MODULE_DEVICE_TABLE() to get\nthese aliases.\n\nSigned-off-by: Roland Dreier \u003crolandd@cisco.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "e3232714d465c42ac631929b990f5e35e2d8a955",
      "tree": "f6b9fe66bd11cdae420f558bebf7e8d4b89b52b4",
      "parents": [
        "b265b11fc1a0bd6ae5a7fde12e374583a52ab326"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:43:02 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:43:02 2009 -0700"
      },
      "message": "ioat3: segregate raid engines\n\nThe cleanup routine for the raid cases imposes extra checks for handling\nraid descriptors and extended descriptors.  If the channel does not\nsupport raid it can avoid this extra overhead by using the ioat2 cleanup\npath.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "b265b11fc1a0bd6ae5a7fde12e374583a52ab326",
      "tree": "8a864413b52e06f11f7f0299cdefd398999e82fb",
      "parents": [
        "58c8649e0e25de511c4a66ce3fa38891e2ec4e9e"
      ],
      "author": {
        "name": "Tom Picard",
        "email": "tom.s.picard@intel.com",
        "time": "Tue Sep 08 17:43:01 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:43:01 2009 -0700"
      },
      "message": "ioat3: ioat3.2 pci ids for Jasper Forest\n\nJasper Forest introduces raid offload support via ioat3.2 support.  When\nraid offload is enabled two (out of 8 channels) will report raid5/raid6\noffload capabilities.  The remaining channels will only report ioat3.0\ncapabilities (memcpy).\n\nSigned-off-by: Tom Picard \u003ctom.s.picard@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "58c8649e0e25de511c4a66ce3fa38891e2ec4e9e",
      "tree": "edb87012a3e42a7bbaa26a1172442da6ea389632",
      "parents": [
        "ae786624c27411c1d38823f640b39f3d97412d5a"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:43:00 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:43:00 2009 -0700"
      },
      "message": "ioat3: interrupt descriptor support\n\nThe async_tx api uses the DMA_INTERRUPT operation type to terminate a\nchain of issued operations with a callback routine.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "ae786624c27411c1d38823f640b39f3d97412d5a",
      "tree": "87ca33dae521c2c5622ea67dde97611e77d77df8",
      "parents": [
        "d69d235b7da2778891640ee95efcd68075978904"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:43:00 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:43:00 2009 -0700"
      },
      "message": "ioat3: support xor via pq descriptors\n\nIf a platform advertises pq capabilities, but not xor, then use\nioat3_prep_pqxor and ioat3_prep_pqxor_val to simulate xor support.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "d69d235b7da2778891640ee95efcd68075978904",
      "tree": "e7f22d38d8a742ddbca167af123f4987ada8926c",
      "parents": [
        "9de6fc717bdc574cf5faf9d46ce0f9d6265c7952"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:42:59 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:42:59 2009 -0700"
      },
      "message": "ioat3: pq support\n\nioat3.2 adds support for raid6 syndrome generation (xor sum of galois\nfield multiplication products) using up to 8 sources.  It can also\nperform an pq-zero-sum operation to validate whether the syndrome for a\ngiven set of sources matches a previously computed syndrome.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "9de6fc717bdc574cf5faf9d46ce0f9d6265c7952",
      "tree": "55cb18ecfae85033d61f730b5f32d2ac1fb572bc",
      "parents": [
        "b094ad3be564e7cc59cca4ff0256550d3a55dd3b"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:42:58 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:42:58 2009 -0700"
      },
      "message": "ioat3: xor self test\n\nThis adds a hardware specific self test to be called from ioat_probe.\nIn the ioat3 case we will have tests for all the different raid\noperations, while ioat1 and ioat2 will continue to just test memcpy.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "b094ad3be564e7cc59cca4ff0256550d3a55dd3b",
      "tree": "d69f515b2ee6af2b0f12bb3028d7c7f5b3390794",
      "parents": [
        "e61dacaeb3918cd00cd642e8fb0828324ac59819"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:42:57 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:42:57 2009 -0700"
      },
      "message": "ioat3: xor support\n\nioat3.2 adds xor offload support for up to 8 sources.  It can also\nperform an xor-zero-sum operation to validate whether all given sources\nsum to zero, without writing to a destination.  Xor descriptors differ\nfrom memcpy in that one operation may require multiple descriptors\ndepending on the number of sources.  When the number of sources exceeds\n5 an extended descriptor is needed.  These descriptors need to be\naccounted for when updating the DMA_COUNT register.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "e61dacaeb3918cd00cd642e8fb0828324ac59819",
      "tree": "70c4acf1cf33502bdca8da16bd88c0daab2bbc29",
      "parents": [
        "5669e31c5a4874f1634bc0ffba268a6e2fa0cdd2"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:42:57 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:42:57 2009 -0700"
      },
      "message": "ioat3: enable dca for completion writes\n\nTag completion writes for direct cache access to reduce the latency of\nchecking for descriptor completions.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "5669e31c5a4874f1634bc0ffba268a6e2fa0cdd2",
      "tree": "3ef3f6724e7a812ba83b420c3915c4a46762aeb7",
      "parents": [
        "bf40a6869c9198bdf56fe173961feb89e9f0d961"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:42:56 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:42:56 2009 -0700"
      },
      "message": "ioat: add \u0027ioat\u0027 sysfs attributes\n\nExport driver attributes for diagnostic purposes:\n\u0027ring_size\u0027: total number of descriptors available to the engine\n\u0027ring_active\u0027: number of descriptors in-flight\n\u0027capabilities\u0027: supported operation types for this channel\n\u0027version\u0027: Intel(R) QuickData specfication revision\n\nThis also allows some chattiness to be removed from the driver startup\nas this information is now available via sysfs.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "bf40a6869c9198bdf56fe173961feb89e9f0d961",
      "tree": "3d1b6bf44647857997113fe1b036fb46e360d8a7",
      "parents": [
        "2aec048cdc4a5a81163a42a61df903f76a27e737"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:42:55 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:42:55 2009 -0700"
      },
      "message": "ioat3: split ioat3 support to its own file, add memset\n\nUp until this point the driver for Intel(R) QuickData Technology\nengines, specification versions 2 and 3, were mostly identical save for\na few quirks.  Version 3.2 hardware adds many new capabilities (like\nraid offload support) requiring some infrastructure that is not relevant\nfor v2.  For better code organization of the new funcionality move v3\nand v3.2 support to its own file dma_v3.c, and export some routines from\nthe base files (dma.c and dma_v2.c) that can be reused directly.\n\nThe first new capability included in this code reorganization is support\nfor v3.2 memset operations.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "2aec048cdc4a5a81163a42a61df903f76a27e737",
      "tree": "00347decc9b145f4c805c8475b980d2641b8ec11",
      "parents": [
        "128f2d567f906d38b11d993d8d97b9b988848e26"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:42:54 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:42:54 2009 -0700"
      },
      "message": "ioat3: hardware version 3.2 register / descriptor definitions\n\nioat3.2 adds raid5 and raid6 offload capabilities.\n\nSigned-off-by: Tom Picard \u003ctom.s.picard@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "128f2d567f906d38b11d993d8d97b9b988848e26",
      "tree": "523fd4b737bd44bccddb2425ae0b16f78a819e19",
      "parents": [
        "83544ae9f3991bfc7d5e0fe9a3008cd05a8d57b7"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:42:53 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:42:53 2009 -0700"
      },
      "message": "ioat2+: add fence support\n\nIn preparation for adding more operation types to the ioat3 path the\ndriver needs to honor the DMA_PREP_FENCE flag.  For example the async_tx api\nwill hand xor-\u003ememcpy-\u003exor chains to the driver with the \u0027fence\u0027 flag set on\nthe first xor and the memcpy operation.  This flag in turn sets the \u0027fence\u0027\nflag in the descriptor control field telling the hardware that future\ndescriptors in the chain depend on the result of the current descriptor, so\nwait for all writes to complete before starting the next operation.\n\nNote that ioat1 does not prefetch the descriptor chain, so does not\nrequire/support fenced operations.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "a309218acee8606f7e235da20cc826eb06d9b0f6",
      "tree": "abf2cc9830b6a5a52a165e6a736e85cd5d7b36c0",
      "parents": [
        "09c8a5b85e5f1e74a19bdd7c85547429d51df1cd"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 12:02:01 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:38:54 2009 -0700"
      },
      "message": "ioat2,3: dynamically resize descriptor ring\n\nIncrement the allocation order of the descriptor ring every time we run\nout of descriptors up to a maximum of allocation order specified by the\nmodule parameter \u0027ioat_max_alloc_order\u0027.  After each idle period\ndecrement the allocation order to a minimum order of\n\u0027ioat_ring_alloc_order\u0027 (i.e. the default ring size, tunable as a module\nparameter).\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "09c8a5b85e5f1e74a19bdd7c85547429d51df1cd",
      "tree": "9bb255d9f596ab062996de49032875e8b9253971",
      "parents": [
        "ad643f54c8514998333bc6c7b201fda2267496be"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 12:01:49 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:30:24 2009 -0700"
      },
      "message": "ioat: switch watchdog and reset handler from workqueue to timer\n\nIn order to support dynamic resizing of the descriptor ring or polling\nfor a descriptor in the presence of a hung channel the reset handler\nneeds to make progress while in a non-preemptible context.  The current\nworkqueue implementation precludes polling channel reset completion\nunder spin_lock().\n\nThis conversion also allows us to return to opportunistic cleanup in the\nioat2 case as the timer implementation guarantees at least one cleanup\nafter every descriptor is submitted.  This means the worst case\ncompletion latency becomes the timer frequency (for exceptional\ncircumstances), but with the benefit of avoiding busy waiting when the\nlock is contended.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "ad643f54c8514998333bc6c7b201fda2267496be",
      "tree": "c92bbecd74912ada08dfa94662b52e63d4c5df46",
      "parents": [
        "345d852391cf3fdc73f23a9ca522c6e7b5eb5a52"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 12:01:38 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:30:24 2009 -0700"
      },
      "message": "ioat1: trim ioat_dma_desc_sw\n\nSave 4 bytes per software descriptor by transmitting tx_cnt in an unused\nportion of the hardware descriptor.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "345d852391cf3fdc73f23a9ca522c6e7b5eb5a52",
      "tree": "a029ab0c4e66a6ea7c7a7b76c06bcffe92fab5e8",
      "parents": [
        "f6ab95b55735fa03cad8d0f966647e5df206e207"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 12:01:30 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:30:24 2009 -0700"
      },
      "message": "ioat: ___devinit annotate the initialization paths\n\nMark all single use initialization routines with __devinit.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "f6ab95b55735fa03cad8d0f966647e5df206e207",
      "tree": "958127a8b5e171d53d26cd1a40d128e34bf8c7b1",
      "parents": [
        "bb3207863014c7310593146f11fbc6573eab43c8"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 12:01:21 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:30:24 2009 -0700"
      },
      "message": "ioat: preserve chanctrl bits when re-arming interrupts\n\nThe register write in ioat_dma_cleanup_tasklet is unfortunate in two\nways:\n1/ It clears the extra \u0027enable\u0027 bits that we set at alloc_chan_resources time\n2/ It gives the impression that it disables interrupts when it is in\n   fact re-arming interrupts\n\n[ Impact: fix, persist the value of the chanctrl register when re-arming ]\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "bb3207863014c7310593146f11fbc6573eab43c8",
      "tree": "d54da64e459d28969cdd9250cadaaa581cbae43d",
      "parents": [
        "4fb9b9e8d55880523db550043dfb204696dd0422"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 12:01:14 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:30:24 2009 -0700"
      },
      "message": "ioat: ignore reserved bits for chancnt and xfercap\n\nDon\u0027t trust that the reserved bits are always zero, also sanity check\nthe returned value.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "4fb9b9e8d55880523db550043dfb204696dd0422",
      "tree": "733a672aeb819bb8133b16329a6b5088cf9ee693",
      "parents": [
        "6df9183a153291a2585a8dfe67597fc18c201147"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 12:01:04 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:30:24 2009 -0700"
      },
      "message": "ioat: cleanup completion status reads\n\nThe cleanup path makes an effort to only perform an atomic read of the\n64-bit completion address.  However in the 32-bit case it does not\nmatter if we read the upper-32 and lower-32 non-atomically because the\nupper-32 will always be zero.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "6df9183a153291a2585a8dfe67597fc18c201147",
      "tree": "5e5f3b3da9308e20f2dda71c85242460bb7cacfa",
      "parents": [
        "38e12f64a165e83617c21dae3c15972fd8d639f5"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 12:00:55 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:30:23 2009 -0700"
      },
      "message": "ioat: add some dev_dbg() calls\n\nProvide some output for debugging the driver.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "38e12f64a165e83617c21dae3c15972fd8d639f5",
      "tree": "43f0951cf0b91b0d831a469d0147c1c4cdd15dfa",
      "parents": [
        "5cbafa65b92ee4f5b8ba915cddf94b91f186b989"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 12:00:46 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:30:23 2009 -0700"
      },
      "message": "ioat1: kill unused unmap parameters\n\nThe unified ioat1/ioat2 ioat_dma_unmap() implementation derives the\nsource and dest addresses from the unmap descriptor.  There is no longer\na need to track this information in struct ioat_desc_sw.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "5cbafa65b92ee4f5b8ba915cddf94b91f186b989",
      "tree": "f074c9dbcdedf05c5567a4e456a15120895363a6",
      "parents": [
        "dcbc853af6f0c056088e4df0794d9bf36184809e"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Aug 26 13:01:44 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:29:55 2009 -0700"
      },
      "message": "ioat2,3: convert to a true ring buffer\n\nReplace the current linked list munged into a ring with a native ring\nbuffer implementation.  The benefit of this approach is reduced overhead\nas many parameters can be derived from ring position with simple pointer\ncomparisons and descriptor allocation/freeing becomes just a\nmanipulation of head/tail pointers.\n\nIt requires a contiguous allocation for the software descriptor\ninformation.\n\nSince this arrangement is significantly different from the ioat1 chain,\nmove ioat2,3 support into its own file and header.  Common routines are\nexported from driver/dma/ioat/dma.[ch].\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n"
    },
    {
      "commit": "dcbc853af6f0c056088e4df0794d9bf36184809e",
      "tree": "1cbab40167487cff6dc8984a00756cfc39dff3f3",
      "parents": [
        "a6a39ca1badbeafc16941fcf2c1010c8c65c8ddc"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jul 28 14:44:50 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:29:55 2009 -0700"
      },
      "message": "ioat: prepare the code for ioat[12]_dma_chan split\n\nPrepare the code for the conversion of the ioat2 linked-list-ring into a\nnative ring buffer.  After this conversion ioat2 channels will share\nless of the ioat1 infrastructure, but there will still be places where\nsharing is possible.  struct ioat_chan_common is created to house the\nchannel attributes that will remain common between ioat1 and ioat2\nchannels.\n\nFor every routine that accesses both common and hardware specific fields\nthe old unified \u0027ioat_chan\u0027 pointer is split into an \u0027ioat\u0027 and  \u0027chan\u0027\npointer.  Where \u0027chan\u0027 references common fields and \u0027ioat\u0027 the\nhardware/version specific.\n\n[ Impact: pure structure member movement/variable renames, no logic changes ]\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n"
    },
    {
      "commit": "a6a39ca1badbeafc16941fcf2c1010c8c65c8ddc",
      "tree": "1f6e4bf5e5ab831ce9cb6de645a1f03545c8cf0a",
      "parents": [
        "a0587bcf3e64029a4da2a5666cad18df38db0d56"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jul 28 14:44:05 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:29:55 2009 -0700"
      },
      "message": "ioat: fix self test interrupts\n\nIf a callback is to be attached to a descriptor the channel needs to\nknow at -\u003eprep time so it can set the interrupt enable bit.  This is in\npreparation for moving descriptor ioat2 descriptor preparation from\n-\u003esubmit to -\u003eprep.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n"
    },
    {
      "commit": "a0587bcf3e64029a4da2a5666cad18df38db0d56",
      "tree": "475b3a2a7cd102f40d7c16fed431c227576c255a",
      "parents": [
        "c7984f4e4e3af3bf8027d636283ea8658c7f80b9"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jul 28 14:44:04 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:29:55 2009 -0700"
      },
      "message": "ioat1: move descriptor allocation from submit to prep\n\nThe async_tx api assumes that after a successful -\u003eprep a subsequent\n-\u003esubmit will not fail due to a lack of resources.\n\nThis also fixes a bug in the allocation failure case.  Previously the\ndescriptors allocated prior to the allocation failure would not be\nreturned to the free list.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n"
    },
    {
      "commit": "c7984f4e4e3af3bf8027d636283ea8658c7f80b9",
      "tree": "81fb1adc44173505d447aa93142cc96a4bf03044",
      "parents": [
        "77867fff033ea549096c49d863c564ad7d8be36f"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jul 28 14:44:04 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:29:55 2009 -0700"
      },
      "message": "ioat: define descriptor control bit-field\n\nThis cleans up a mess of and\u0027ing and or\u0027ing bit definitions, and allows\nsimple assignments from the specified dma_ctrl_flags parameter.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n"
    },
    {
      "commit": "77867fff033ea549096c49d863c564ad7d8be36f",
      "tree": "d39bce48f29aa9ce6f23f15e73fab8333d91bc75",
      "parents": [
        "f2427e276ffec5ce599c6bc116e0927269a360ef"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jul 28 14:44:04 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:29:54 2009 -0700"
      },
      "message": "ioat: fix type mismatch for -\u003edmacount\n\n-\u003edmacount tracks the sequence number of active descriptors.  It is\nwritten to the DMACOUNT register to update the channel\u0027s view of pending\ndescriptors in the chain.  The register is 16-bits so -\u003edmacount should\nbe unsigned and 16-bit as well.  Also modify -\u003edesccount to maintain\nalignment.\n\nThis was never a problem in practice because we never compared dmacount\nvalues, but this is a bug waiting to happen.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n"
    },
    {
      "commit": "f2427e276ffec5ce599c6bc116e0927269a360ef",
      "tree": "d23b47ad7a00daeba720c25bb900fd96bf226f54",
      "parents": [
        "b31b78f1ab7806759622b703357e39a21f757281"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jul 28 14:42:38 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:29:54 2009 -0700"
      },
      "message": "ioat: split ioat_dma_probe into core/version-specific routines\n\nTowards the removal of ioatdma_device.version split the initialization\npath into distinct versions.  This conversion:\n1/ moves version specific probe code to version specific routines\n2/ removes the need for ioat_device\n3/ turns off the ioat1 msi quirk if the device is reinitialized for intx\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n"
    },
    {
      "commit": "b31b78f1ab7806759622b703357e39a21f757281",
      "tree": "70144a699561184ed9d7bcd0b0f8f2b102204947",
      "parents": [
        "bc3c70258526a635325f1f15138a96297879bc1a"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jul 28 14:42:32 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:29:54 2009 -0700"
      },
      "message": "ioat: kill function prototype ifdef guards\n\nThe only .c files that utilize these protected prototypes depend on\nCONFIG_INTEL_IOATDMA\u003dy, so there is no value gained in providing empty\nprototypes.\n\n[ Impact: pure cleanup ]\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n"
    },
    {
      "commit": "bc3c70258526a635325f1f15138a96297879bc1a",
      "tree": "65ced583f975cb19dc12f498f7e97536033fe74f",
      "parents": [
        "e6c0b69a43150c1a37cf342ce5faedf12583bf79"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jul 28 14:33:42 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:29:54 2009 -0700"
      },
      "message": "ioat: cleanup some long deref chains and 80 column collisions\n\n* reduce device-\u003ecommon. to dma-\u003e in ioat_dma_{probe,remove,selftest}\n* ioat_lookup_chan_by_index to ioat_chan_by_index\n* multi-line function definitions\n* ioat_desc_sw.async_tx to ioat_desc_sw.txd\n* desc-\u003etxd. to tx-\u003e in cleanup routine\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n"
    },
    {
      "commit": "e6c0b69a43150c1a37cf342ce5faedf12583bf79",
      "tree": "955456982fea62d6557ad5992f19ee3e73e64bc2",
      "parents": [
        "1f27adc2f050836c12deb4d99afe507636537a0b"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:29:44 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:29:44 2009 -0700"
      },
      "message": "ioat: convert ioat_probe to pcim/devm\n\nThe driver currently duplicates much of what these routines offer, so\njust use the common code.  For example -\u003eirq_mode tracks what interrupt\nmode was initialized, which duplicates the -\u003emsix_enabled and\n-\u003emsi_enabled handling in pcim_release.\n\nThis also adds a check to the return value of dma_async_device_register,\nwhich can fail.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n"
    },
    {
      "commit": "1f27adc2f050836c12deb4d99afe507636537a0b",
      "tree": "aeb0b1a0896dd1367174a46d29c7ebc18187a4f9",
      "parents": [
        "584ec22759c06cdfc189c03a727f20038526245b"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:29:02 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:29:02 2009 -0700"
      },
      "message": "ioat: move definitions to dma.h\n\nSome of these defines may be useful outside of dma.c and the header is\nprivate so there are no namespace pollution concerns.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n"
    },
    {
      "commit": "584ec22759c06cdfc189c03a727f20038526245b",
      "tree": "54f4ebb99c3f66f62aeb38d091d1840d88e2ee57",
      "parents": [
        "07a2039b8eb0af4ff464efd3dfd95de5c02648c6"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jul 28 14:32:12 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jul 28 14:32:12 2009 -0700"
      },
      "message": "ioat: move to drivers/dma/ioat/\n\nWhen first created the ioat driver was the only inhabitant of\ndrivers/dma/.  Now, it is the only multi-file (more than a .c and a .h)\ndriver in the directory.  Moving it to an ioat/ subdirectory allows the\nnaming convention to be cleaned up, and allows for future splitting of\nthe source files by hardware version (v1, v2, and v3).\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n"
    }
  ]
}