)]}' { "log": [ { "commit": "5a0e3ad6af8660be21ca98a971cd00f331318c05", "tree": "5bfb7be11a03176a87296a43ac6647975c00a1d1", "parents": [ "ed391f4ebf8f701d3566423ce8f17e614cde9806" ], "author": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Wed Mar 24 17:04:11 2010 +0900" }, "committer": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Tue Mar 30 22:02:32 2010 +0900" }, "message": "include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h\n\npercpu.h is included by sched.h and module.h and thus ends up being\nincluded when building most .c files. percpu.h includes slab.h which\nin turn includes gfp.h making everything defined by the two files\nuniversally available and complicating inclusion dependencies.\n\npercpu.h -\u003e slab.h dependency is about to be removed. Prepare for\nthis change by updating users of gfp and slab facilities include those\nheaders directly instead of assuming availability. As this conversion\nneeds to touch large number of source files, the following script is\nused as the basis of conversion.\n\n http://userweb.kernel.org/~tj/misc/slabh-sweep.py\n\nThe script does the followings.\n\n* Scan files for gfp and slab usages and update includes such that\n only the necessary includes are there. ie. if only gfp is used,\n gfp.h, if slab is used, slab.h.\n\n* When the script inserts a new include, it looks at the include\n blocks and try to put the new include such that its order conforms\n to its surrounding. It\u0027s put in the include block which contains\n core kernel includes, in the same order that the rest are ordered -\n alphabetical, Christmas tree, rev-Xmas-tree or at the end if there\n doesn\u0027t seem to be any matching order.\n\n* If the script can\u0027t find a place to put a new include (mostly\n because the file doesn\u0027t have fitting include block), it prints out\n an error message indicating which .h file needs to be added to the\n file.\n\nThe conversion was done in the following steps.\n\n1. The initial automatic conversion of all .c files updated slightly\n over 4000 files, deleting around 700 includes and adding ~480 gfp.h\n and ~3000 slab.h inclusions. The script emitted errors for ~400\n files.\n\n2. Each error was manually checked. Some didn\u0027t need the inclusion,\n some needed manual addition while adding it to implementation .h or\n embedding .c file was more appropriate for others. This step added\n inclusions to around 150 files.\n\n3. The script was run again and the output was compared to the edits\n from #2 to make sure no file was left behind.\n\n4. Several build tests were done and a couple of problems were fixed.\n e.g. lib/decompress_*.c used malloc/free() wrappers around slab\n APIs requiring slab.h to be added manually.\n\n5. The script was run on all .h files but without automatically\n editing them as sprinkling gfp.h and slab.h inclusions around .h\n files could easily lead to inclusion dependency hell. Most gfp.h\n inclusion directives were ignored as stuff from gfp.h was usually\n wildly available and often used in preprocessor macros. Each\n slab.h inclusion directive was examined and added manually as\n necessary.\n\n6. percpu.h was updated not to include slab.h.\n\n7. Build test were done on the following configurations and failures\n were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my\n distributed build env didn\u0027t work with gcov compiles) and a few\n more options had to be turned off depending on archs to make things\n build (like ipr on powerpc/64 which failed due to missing writeq).\n\n * x86 and x86_64 UP and SMP allmodconfig and a custom test config.\n * powerpc and powerpc64 SMP allmodconfig\n * sparc and sparc64 SMP allmodconfig\n * ia64 SMP allmodconfig\n * s390 SMP allmodconfig\n * alpha SMP allmodconfig\n * um on x86_64 SMP allmodconfig\n\n8. percpu.h modifications were reverted so that it could be applied as\n a separate patch and serve as bisection point.\n\nGiven the fact that I had only a couple of failures from tests on step\n6, I\u0027m fairly confident about the coverage of this conversion patch.\nIf there is a breakage, it\u0027s likely to be something in one of the arch\nheaders which should be easily discoverable easily on most builds of\nthe specific arch.\n\nSigned-off-by: Tejun Heo \u003ctj@kernel.org\u003e\nGuess-its-ok-by: Christoph Lameter \u003ccl@linux-foundation.org\u003e\nCc: Ingo Molnar \u003cmingo@redhat.com\u003e\nCc: Lee Schermerhorn \u003cLee.Schermerhorn@hp.com\u003e\n" }, { "commit": "fb8a0d9d1bfd1e4355f307e86a6da7209eefd5f3", "tree": "99f23a4bc7c51343619f63970e5d017d75b5a66f", "parents": [ "81d54ec8479a2c695760da81f05b5a9fb2dbe40a" ], "author": { "name": "Williams, Mitch A", "email": "mitch.a.williams@intel.com", "time": "Wed Feb 10 01:43:04 2010 +0000" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Fri Feb 12 16:56:07 2010 -0800" }, "message": "pci: Add SR-IOV convenience functions and macros\n\nAdd and export pci_num_vf to allow other subsystems to determine how many\nvirtual function devices are associated with an SR-IOV physical function\ndevice.\nAdd macros dev_is_pci, dev_is_ps, and dev_num_vf to make it easier for\nnon-PCI specific code to determine SR-IOV capabilities.\n\nSigned-off-by: Mitch Williams \u003cmitch.a.williams@intel.com\u003e\nSigned-off-by: Jeff Kirsher \u003cjeffrey.t.kirsher@intel.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "5f4d91a1228ac85c75b099efd36fff1a3407335c", "tree": "ed0d13811c60bf3357ef70ea2931e29a358ed023", "parents": [ "7eb776c42e75d17bd8107a1359068d8c742639d1" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 11 14:36:17 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Nov 24 15:25:16 2009 -0800" }, "message": "PCI: use pci_is_pcie() in pci core\n\nChange for PCI core to use pci_is_pcie() instead of checking\npci_dev-\u003eis_pcie.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "6faf17f6f1ffc586d16efc2f9fa2083a7785ee74", "tree": "383d4a10cdc0b02bd8bc3a873613a68a06748cd7", "parents": [ "adda766193ea1cf3137484a9521972d080d0b7af" ], "author": { "name": "Chris Wright", "email": "chrisw@sous-sol.org", "time": "Fri Aug 28 13:00:06 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Sun Aug 30 08:37:25 2009 -0700" }, "message": "PCI SR-IOV: correct broken resource alignment calculations\n\nAn SR-IOV capable device includes an SR-IOV PCIe capability which\ndescribes the Virtual Function (VF) BAR requirements. A typical SR-IOV\ndevice can support multiple VFs whose BARs must be in a contiguous region,\neffectively an array of VF BARs. The BAR reports the size requirement\nfor a single VF. We calculate the full range needed by simply multiplying\nthe VF BAR size with the number of possible VFs and create a resource\nspanning the full range.\n\nThis all seems sane enough except it artificially inflates the alignment\nrequirement for the VF BAR. The VF BAR need only be aligned to the size\nof a single BAR not the contiguous range of VF BARs. This can cause us\nto fail to allocate resources for the BAR despite the fact that we\nactually have enough space.\n\nThis patch adds a thin PCI specific layer over the generic\nresource_alignment() function which is aware of the special nature of\nVF BARs and does sorting and allocation based on the smaller alignment\nrequirement.\n\nI recognize that while resource_alignment is generic, it\u0027s basically a\nPCI helper. An alternative to this patch is to add PCI VF BAR specific\ninformation to struct resource. I opted for the extra layer rather than\nadding such PCI specific information to struct resource. This does\nhave the slight downside that we don\u0027t cache the BAR size and re-read\nfor each alignment query (happens a small handful of times during boot\nfor each VF BAR).\n\nSigned-off-by: Chris Wright \u003cchrisw@sous-sol.org\u003e\nCc: Ivan Kokshaysky \u003cink@jurassic.park.msu.ru\u003e\nCc: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\nCc: Matthew Wilcox \u003cmatthew@wil.cx\u003e\nCc: Yu Zhao \u003cyu.zhao@intel.com\u003e\nCc: stable@kernel.org\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "687d680985b1438360a9ba470ece8b57cd205c3b", "tree": "ae253608531e5c3e823600974c610e722e7de759", "parents": [ "1053414068bad659479e6efa62a67403b8b1ec0a", "008fe148cb0fb51d266baabe2c09997b21cf90c6" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Jun 22 21:38:22 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Jun 22 21:38:22 2009 -0700" }, "message": "Merge git://git.infradead.org/~dwmw2/iommu-2.6.31\n\n* git://git.infradead.org/~dwmw2/iommu-2.6.31:\n intel-iommu: Fix one last ia64 build problem in Pass Through Support\n VT-d: support the device IOTLB\n VT-d: cleanup iommu_flush_iotlb_psi and flush_unmaps\n VT-d: add device IOTLB invalidation support\n VT-d: parse ATSR in DMA Remapping Reporting Structure\n PCI: handle Virtual Function ATS enabling\n PCI: support the ATS capability\n intel-iommu: dmar_set_interrupt return error value\n intel-iommu: Tidy up iommu-\u003egcmd handling\n intel-iommu: Fix tiny theoretical race in write-buffer flush.\n intel-iommu: Clean up handling of \"caching mode\" vs. IOTLB flushing.\n intel-iommu: Clean up handling of \"caching mode\" vs. context flushing.\n VT-d: fix invalid domain id for KVM context flush\n Fix !CONFIG_DMAR build failure introduced by Intel IOMMU Pass Through Support\n Intel IOMMU Pass Through Support\n\nFix up trivial conflicts in drivers/pci/{intel-iommu.c,intr_remapping.c}\n" }, { "commit": "8c1c699fec9e9021bf6ff0285dee086bb27aec90", "tree": "4af7bd96c1b651633ff7b6721959aeacd120e4ee", "parents": [ "c465def6bfe834b62623caa9b98f2d4f4739875a" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Sat Jun 13 15:52:13 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Jun 16 14:30:15 2009 -0700" }, "message": "PCI: cleanup Function Level Reset\n\nThis patch enhances the FLR functions:\n 1) remove disable_irq() so the shared IRQ won\u0027t be disabled.\n 2) replace the 1s wait with 100, 200 and 400ms wait intervals\n for the Pending Transaction.\n 3) replace mdelay() with msleep().\n 4) add might_sleep().\n 5) lock the device to prevent PM suspend from accessing the CSRs\n during the reset.\n 6) coding style fixes.\n\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "4d135dbee7b0a89e946f7ba284f2b957505a2c3a", "tree": "332fb82ad8721cd1c3b8f0260971b2389f76ad5a", "parents": [ "af4c5f985afd8d4cfdf402aaa03677f2cb96e37c" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Wed May 20 17:11:57 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 11 12:04:20 2009 -0700" }, "message": "PCI: fix SR-IOV function dependency link problem\n\nPCIe root complex integrated endpoint does not implement ARI, so this\nkind of endpoint uses 3-bit function number. The function dependency\nlink of the integrated endpoint should be calculated using the device\nnumber plus the value from function dependency link register.\n\nNormal endpoint always implements ARI and the function dependency link\nregister contains 8-bit function number (i.e. `devfn\u0027 from software\u0027s\nperspective).\n\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "e277d2fc79d6abb86fafadb58dca0b9c498a9aa7", "tree": "6f7a6c5bf2b300bec9fa76266eeb9089dc82e651", "parents": [ "302b4215daa0a704c843da40fd2529e5757a72da" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Mon May 18 13:51:33 2009 +0800" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon May 18 11:25:58 2009 +0100" }, "message": "PCI: handle Virtual Function ATS enabling\n\nThe SR-IOV spec requires that the Smallest Translation Unit and\nthe Invalidate Queue Depth fields in the Virtual Function ATS\ncapability are hardwired to 0. If a function is a Virtual Function,\nthen and set its Physical Function\u0027s STU before enabling the ATS.\n\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "302b4215daa0a704c843da40fd2529e5757a72da", "tree": "1bc40108fceafd3fbc9faee38c971fa94d560b13", "parents": [ "dd7264355a203c3456dbba04db471947d3b55e7e" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Mon May 18 13:51:32 2009 +0800" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon May 18 11:25:54 2009 +0100" }, "message": "PCI: support the ATS capability\n\nThe PCIe ATS capability makes the Endpoint be able to request the\nDMA address translation from the IOMMU and cache the translation\nin the device side, thus alleviate IOMMU pressure and improve the\nhardware performance in the I/O virtualization environment.\n\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "52a8873ba4e82d6e87f8478b3e7f9c12d8b37c38", "tree": "0af7af907d29c3af3f5b15f24f069aa4312ff76f", "parents": [ "296ccb086dfb89b5b8d73ef08c795ffdff12a597" ], "author": { "name": "Randy Dunlap", "email": "randy.dunlap@oracle.com", "time": "Wed Apr 01 17:45:30 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Apr 06 11:25:33 2009 -0700" }, "message": "PCI-IOV: fix missing kernel-doc\n\nFix PCI iov kernel-doc warning:\n\nWarning(drivers/pci/iov.c:638): No description found for parameter \u0027nr_virtfn\u0027\n\nSigned-off-by: Randy Dunlap \u003crandy.dunlap@oracle.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "74bb1bcc7dbbc9ddef773bf3395d7ff92aaaad2e", "tree": "38dd25aed251b00a4b34612320beb64f4a058814", "parents": [ "dd7cc44d0bcec5e9c42fe52e88dc254ae62eac8d" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Fri Mar 20 11:25:16 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 10:48:28 2009 -0700" }, "message": "PCI: handle SR-IOV Virtual Function Migration\n\nAdd or remove a Virtual Function after receiving a Migrate In or Out\nRequest.\n\nReviewed-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "dd7cc44d0bcec5e9c42fe52e88dc254ae62eac8d", "tree": "742b2c903580eded1e352988b068c0362eccc634", "parents": [ "480b93b7837fb3cf0579a42f4953ac463a5b9e1e" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Fri Mar 20 11:25:15 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 10:48:26 2009 -0700" }, "message": "PCI: add SR-IOV API for Physical Function driver\n\nAdd or remove the Virtual Function when the SR-IOV is enabled or\ndisabled by the device driver. This can happen anytime rather than\nonly at the device probe stage.\n\nReviewed-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "a28724b0fb909d247229a70761c90bb37b13366a", "tree": "7c5332004a8f52e676076b39aa03aeb45cb03f2a", "parents": [ "8c5cdb6adc6688b9b8fd82ea4a5cf4674dabad79" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Fri Mar 20 11:25:13 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 10:48:24 2009 -0700" }, "message": "PCI: reserve bus range for SR-IOV device\n\nReserve the bus number range used by the Virtual Function when\npcibios_assign_all_busses() returns true.\n\nReviewed-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "8c5cdb6adc6688b9b8fd82ea4a5cf4674dabad79", "tree": "79fbfde0cedf983b87cf6f782c108000d5c5752d", "parents": [ "d1b054da8f599905f3c18a218961dcf17f9d5f13" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Fri Mar 20 11:25:12 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 10:48:24 2009 -0700" }, "message": "PCI: restore saved SR-IOV state\n\nRestore the volatile registers in the SR-IOV capability after the\nD3-\u003eD0 transition.\n\nReviewed-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "d1b054da8f599905f3c18a218961dcf17f9d5f13", "tree": "99b62e6771c3b73142dd0622463bed0e19724342", "parents": [ "8293b0f629095efbe7c7e3f9b437f8c040c19eb5" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Fri Mar 20 11:25:11 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 10:48:22 2009 -0700" }, "message": "PCI: initialize and release SR-IOV capability\n\nIf a device has the SR-IOV capability, initialize it (set the ARI\nCapable Hierarchy in the lowest numbered PF if necessary; calculate\nthe System Page Size for the VF MMIO, probe the VF Offset, Stride\nand BARs). A lock for the VF bus allocation is also initialized if\na PF is the lowest numbered PF.\n\nReviewed-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" } ] }