)]}' { "log": [ { "commit": "45aa23b4cbd37408678c96cd113241860d3321f6", "tree": "be7881f74ca8c7c1571fe42af09d63493fb5a787", "parents": [ "4352aa5bbf1d0080c2dcf904ce1e4be0a1cb5937" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Thu Apr 22 09:02:43 2010 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Apr 22 16:13:16 2010 -0700" }, "message": "PCI: revert broken device warning\n\nThis reverts c519a5a7dab2d. That change added a warning about devices that\ndidn\u0027t respond correctly when sizing BARs, which helped diagnose broken\ndevices. But the test wasn\u0027t specific enough, so it also complained about\nworking devices with zero-size BARs, e.g.,\nhttps://bugzilla.kernel.org/show_bug.cgi?id\u003d15822\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "c519a5a7dab2d8e9a114f003e2d369bcf8e913f3", "tree": "2f0ebf4123b9b66b8068b8532334bad0f5cd0d84", "parents": [ "e1944c6b0fba80a7837c1cbc47dfbf46e1274a4b" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Fri Mar 19 14:56:27 2010 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Mar 24 13:21:36 2010 -0700" }, "message": "PCI: complain about devices that seem to be broken\n\nIf we can tell that a device isn\u0027t working correctly, we should tell\nthe user to make debugging easier. Otherwise, it can take a lot of\nwork to determine whether the problem is in the driver, PCMCIA, PCI,\nhardware, etc., as in http://bugzilla.kernel.org/show_bug.cgi?id\u003d12006\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "7b8ff6da028232aadae6bcc7c7406c8966d0b3c4", "tree": "c0bab7d872f6e8907d6bdf473f7fbedcfaf83081", "parents": [ "99ddd552fef7e6e3b7dc76ba8fee9ea5869d1e14" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Tue Mar 16 15:53:03 2010 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Mar 24 13:21:35 2010 -0700" }, "message": "PCI: make disabled window printk style match the enabled ones\n\nNo functional change; this just tweaks the changes from 349e1823a405\nso the new printks for disabled PCI-to-PCI bridge windows match the\nones for the enabled windows.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nCC: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "99ddd552fef7e6e3b7dc76ba8fee9ea5869d1e14", "tree": "efdfc780d0993ab3e62888000bd3ff5f38508602", "parents": [ "966f3a7570447c5025d67a618d408e68a3ae3167" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Tue Mar 16 15:52:58 2010 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Mar 24 13:21:35 2010 -0700" }, "message": "PCI: break out primary/secondary/subordinate for readability\n\nNo functional change; just add names for the primary/secondary/subordinate\nbus numbers read from config space rather than repeatedly masking/shifting.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "a1e4d72cd3024999bfb6703092ea271438805c89", "tree": "853a289d73ad9ffb04038fc493d209e980a3ef9b", "parents": [ "09c09bc618a4ceec387c57542031b4fc35826e16" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Mon Feb 08 19:16:33 2010 +0100" }, "committer": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Fri Feb 26 20:39:12 2010 +0100" }, "message": "PM: Allow PCI devices to suspend/resume asynchronously\n\nSet power.async_suspend for all PCI devices and PCIe port services,\nso that they can be suspended and resumed in parallel with other\ndevices they don\u0027t depend on in a known way (i.e. devices which are\nnot their parents or children).\n\nThis only affects the \"regular\" suspend and resume stages, which\nmeans in particular that the restoration of the PCI devices\u0027 standard\nconfiguration registers during resume will still be carried out\nsynchronously (at the \"early\" resume stage).\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\n" }, { "commit": "2fe2abf896c1e7a0ee65faaf3ef0ce654848abbd", "tree": "f066d5c94bbed5ca3556b4d2f0c4b3a9795b6eff", "parents": [ "89a74ecccd1f78e51faf6287e5c0e93a92ac096e" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Tue Feb 23 10:24:36 2010 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Feb 23 09:43:37 2010 -0800" }, "message": "PCI: augment bus resource table with a list\n\nPreviously we used a table of size PCI_BUS_NUM_RESOURCES (16) for resources\nforwarded to a bus by its upstream bridge. We\u0027ve increased this size\nseveral times when the table overflowed.\n\nBut there\u0027s no good limit on the number of resources because host bridges\nand subtractive decode bridges can forward any number of ranges to their\nsecondary buses.\n\nThis patch reduces the table to only PCI_BRIDGE_RESOURCE_NUM (4) entries,\nwhich corresponds to the number of windows a PCI-to-PCI (3) or CardBus (4)\nbridge can positively decode. Any additional resources, e.g., PCI host\nbridge windows or subtractively-decoded regions, are kept in a list.\n\nI\u0027d prefer a single list rather than this split table/list approach, but\nthat requires simultaneous changes to every architecture. This approach\nonly requires immediate changes where we set up (a) host bridges with more\nthan four windows and (b) subtractive-decode P2P bridges, and we can\nincrementally change other architectures to use the list.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "2adf75160b10bf3f09ed7d3d04e937f923fc557e", "tree": "db2998c5403f6c12bb207fd80a1e1fca2ec4a1b4", "parents": [ "fa27b2d108fa49685129867a8c5b968344d6e197" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Tue Feb 23 10:24:26 2010 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Feb 23 09:43:25 2010 -0800" }, "message": "PCI: read bridge windows before filling in subtractive decode resources\n\nNo functional change; this fills in the bus subtractive decode resources\nafter reading the bridge window information rather than before. Also,\nprint out the subtractive decode resources as we already do for the\npositive decode windows.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "fa27b2d108fa49685129867a8c5b968344d6e197", "tree": "442356bc1afa2aacf1afc7e53ebc9aca8a14903d", "parents": [ "b16694f70c40ea8d539cdc93a422039771e85870" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Tue Feb 23 10:24:21 2010 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Feb 23 09:43:17 2010 -0800" }, "message": "PCI: split up pci_read_bridge_bases()\n\nNo functional change; this breaks up pci_read_bridge_bases() into separate\npieces for the I/O, memory, and prefetchable memory windows, similar to how\nYinghai recently split up pci_setup_bridge() in 68e84ff3bdc.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "cd81e1ea1a4cda94aa5f3e942301cf0da497c262", "tree": "91f271f961f560e62f1e0790e766f98afc287a00", "parents": [ "568ddef8735d4a51a521ba6af026ee0c32281566" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Fri Jan 22 01:02:22 2010 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:17:21 2010 -0800" }, "message": "PCI: reject mmio ranges starting at 0 on pci_bridge read\n\nWe already track unassigned resources in struct resource, and this\nprevents us from overwriting resource flags and info in the unassigned\ncase.\n\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "4fb88c1a28a8dc302bdc09858e7cdafc97bef794", "tree": "cd2d6ff98626d6d8782edd848c357bc4607ece17", "parents": [ "0bf01c3c86d4b9ea279d6215420484db887f5db5" ], "author": { "name": "Matthew Wilcox", "email": "matthew@wil.cx", "time": "Sun Jan 17 14:01:41 2010 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:17:17 2010 -0800" }, "message": "PCI: Make pci_scan_slot more robust\n\nYinghai pointed out that the new pci_scan_slot() crashes when called\non an ARI-capable slot that is empty. Fix this by exiting early from\npci_scan_slot if there is no device in the slot.\n\nAlso make next_ari_func() robust against devices not existing in case\nthe ARI capability is corrupt. ARI also requires that the devices be\nlisted in order, so if we find a function listed that is out of order,\nstop scanning to prevent loops.\n\nSigned-off-by: Matthew Wilcox \u003cmatthew@wil.cx\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "9dfd97fe12f79ec8b68feb63912a4ef2f31f571a", "tree": "845515c430a3cc48b1d88496d3b8f4d13bd7efb2", "parents": [ "45b4cdd57ef0e57555b2ab61b584784819b39365" ], "author": { "name": "Matthew Wilcox", "email": "matthew@wil.cx", "time": "Sun Dec 13 08:11:35 2009 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:15:19 2010 -0800" }, "message": "PCI: Add support for reporting PCIe 3.0 speeds\n\nAdd the 8.0 GT/s speed.\n\nSigned-off-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "45b4cdd57ef0e57555b2ab61b584784819b39365", "tree": "1e08008e0cdc57252022b5ad1a0e3029c7e96f99", "parents": [ "9be60ca0497a2563662fde4c9007841c3b79a742" ], "author": { "name": "Matthew Wilcox", "email": "matthew@wil.cx", "time": "Sun Dec 13 08:11:34 2009 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:15:19 2010 -0800" }, "message": "PCI: Add support for AGP in cur/max bus speed\n\nTake advantage of some gaps in the table to fit in support for AGP speeds.\n\nSigned-off-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "9be60ca0497a2563662fde4c9007841c3b79a742", "tree": "d31bc38997f7591d818d478ba91a7f07dee9bede", "parents": [ "3749c51ac6c1560aa1cb1520066bed84c6f8152a" ], "author": { "name": "Matthew Wilcox", "email": "matthew@wil.cx", "time": "Sun Dec 13 08:11:33 2009 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:15:18 2010 -0800" }, "message": "PCI: Add support for detection of PCIe and PCI-X bus speeds\n\nBoth PCIe and PCI-X bridges report their secondary bus speed in their\nrespective capabilities.\n\nSigned-off-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "3749c51ac6c1560aa1cb1520066bed84c6f8152a", "tree": "3cbfb6a6d2df821e3e80ccce29ede8011b94246e", "parents": [ "536c8cb49eccd4f753b4782e7e975ef87359cb44" ], "author": { "name": "Matthew Wilcox", "email": "matthew@wil.cx", "time": "Sun Dec 13 08:11:32 2009 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:15:17 2010 -0800" }, "message": "PCI: Make current and maximum bus speeds part of the PCI core\n\nMove the max_bus_speed and cur_bus_speed into the pci_bus. Expose the\nvalues through the PCI slot driver instead of the hotplug slot driver.\nUpdate all the hotplug drivers to use the pci_bus instead of their own\ndata structures.\n\nSigned-off-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f07852d6442c46c50b59c7e2acc8a1b291f9ab6d", "tree": "d855a7bc7df8f3e84f1d267e060537ec011477c6", "parents": [ "bee415ce427d1eab6cfb30221461c7d20cbf1903" ], "author": { "name": "Matthew Wilcox", "email": "matthew@wil.cx", "time": "Sun Dec 13 08:10:02 2009 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:15:16 2010 -0800" }, "message": "PCI: Rewrite pci_scan_slot\n\nThe Alternate Routing-ID Interpretation capability allows a single device\nto have up to 256 functions. They can be populated sparsely, so the\ncurrent technique of scanning every eighth function is not guaranteed\nto find them all. By introducing a \u0027next_fn\u0027 function pointer, we can\nuse the linked list of functions in the ARI capability to scan all the\nfunctions which exist.\n\nWe can then speed up the pci_scan_slot by skipping the scan of subsequent\ndevfns for PCIe devices which are the direct children of Root Ports or\nDownstream Ports. These devices are only permitted to implement device\n0, unless they are ARI devices, in which case they\u0027ll be scanned by the\nARI code above.\n\nSigned-off-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "bb209c8287d2d55ec4a67e3933346e0a3ee0da76", "tree": "2e444f273e631fa4dded4ee13ac779565e5efb43", "parents": [ "b04da8bfdfbbd79544cab2fadfdc12e87eb01600" ], "author": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Tue Jan 26 17:10:03 2010 +0000" }, "committer": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Fri Jan 29 16:51:10 2010 +1100" }, "message": "powerpc/pci: Add calls to set_pcie_port_type() and set_pcie_hotplug_bridge()\n\nWe are missing these when building the pci_dev from scratch off\nthe Open Firmware device-tree\n\nSigned-off-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "5d990b627537e59a3a2f039ff588a4750e9c1a6a", "tree": "8c0e723c3f9146da52b30c087a80fc417df2b41b", "parents": [ "b26a34aa4792b3db2500b8a98cb7702765c1a92e" ], "author": { "name": "Chris Wright", "email": "chrisw@sous-sol.org", "time": "Fri Dec 04 12:15:21 2009 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 16:19:24 2009 -0800" }, "message": "PCI: add pci_request_acs\n\nCommit ae21ee65e8bc228416bbcc8a1da01c56a847a60c \"PCI: acs p2p upsteram\nforwarding enabling\" doesn\u0027t actually enable ACS.\n\nAdd a function to pci core to allow an IOMMU to request that ACS\nbe enabled. The existing mechanism of using iommu_found() in the pci\ncore to know when ACS should be enabled doesn\u0027t actually work due to\ninitialization order; iommu has only been detected not initialized.\n\nHave Intel and AMD IOMMUs request ACS, and Xen does as well during early\ninit of dom0.\n\nCc: Allen Kay \u003callen.m.kay@intel.com\u003e\nCc: David Woodhouse \u003cdwmw2@infradead.org\u003e\nCc: Jeremy Fitzhardinge \u003cjeremy@goop.org\u003e\nCc: Joerg Roedel \u003cjoerg.roedel@amd.com\u003e\nSigned-off-by: Chris Wright \u003cchrisw@sous-sol.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "06a1cbafb253c4c60d6a54a994887f5fbceabcc0", "tree": "e534c369ab1878a5d86996c29d629d1f5d8f9f75", "parents": [ "d7b7e60526d54da4c94afe5f137714cee7d05c41" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 11 14:30:56 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Nov 24 15:25:12 2009 -0800" }, "message": "PCI: use pci_pcie_cap() in pci core\n\nUse pcie_cap() instead of pci_find_capability() to get PCIe capability\noffset in PCI core code. This avoids unnecessary search in PCI\nconfiguration space.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "0efea0006335a2425b1a12a2ad35efad626fe353", "tree": "d139b06a32665ec1227c06f1c0a14b21e3c0d654", "parents": [ "1e5ad9679016275d422e36b12a98b0927d76f556" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Thu Nov 05 12:05:11 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Nov 06 13:59:02 2009 -0800" }, "message": "PCI: cache PCIe capability offset\n\nThere are a lot of codes that searches PCI express capability offset\nin the PCI configuration space using pci_find_capability(). Caching it\nin the struct pci_dev will reduce unncecessary search. This patch adds\nan additional \u0027pcie_cap\u0027 fields into struct pci_dev, which is\ninitialized at pci device scan time (in set_pcie_port_type()).\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "865df576e8fc70daf297b53e61a4fbefc719d065", "tree": "59abb13e1dd402bf8cb4496ab94bbceb2ac2ee2b", "parents": [ "0207c356ef0e2bae6ce4603080d42c130d7debc6" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Wed Nov 04 10:32:57 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 13:06:44 2009 -0800" }, "message": "PCI: improve discovery/configuration messages\n\nThis makes PCI resource management messages more consistent and adds a few\nnew messages to aid debugging.\n\nWhenever we assign resources to a device, update a BAR, or change a\nbridge aperture, it\u0027s worth noting it.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "0207c356ef0e2bae6ce4603080d42c130d7debc6", "tree": "504e801b50b3a0a3782f1749e72468c84e788cf7", "parents": [ "2a6bed8301f8b019717504575a3f9c6cce1fe271" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Wed Nov 04 10:32:52 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 13:06:44 2009 -0800" }, "message": "PCI: replace pr_debug with dev_dbg\n\nSince we have a struct device, we might as well use dev_printk. Note that\nboth pr_debug() and dev_dbg() are completely compiled out unless DEBUG or\nDYNAMIC_DEBUG is defined.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "c7dabef8a2c59e6a3de9d66fc35fb6a43ef7172d", "tree": "0f8b0021e693a0e380ef9026083b59d0909dffc6", "parents": [ "4fd8bdc567e70c02fab7eeaaa7d2a64232add789" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Tue Oct 27 13:26:47 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 13:06:41 2009 -0800" }, "message": "vsprintf: use %pR, %pr instead of %pRt, %pRf\n\nJesse accidentally applied v1 [1] of the patchset instead of v2 [2]. This\nis the diff between v1 and v2.\n\nThe changes in this patch are:\n - tidied vsprintf stack buffer to shrink and compute size more\n accurately\n - use %pR for decoding and %pr for \"raw\" (with type and flags) instead\n of adding %pRt and %pRf\n\n[1] http://lkml.org/lkml/2009/10/6/491\n[2] http://lkml.org/lkml/2009/10/13/441\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "bc577d2bb98cc44371287fce3e892d26ad4050a8", "tree": "801ff1dbf10301bda75879141482eb226192e280", "parents": [ "0584396157ad2d008e2cc76b4ed6254151183a25" ], "author": { "name": "Gabe Black", "email": "gabe.black@ni.com", "time": "Tue Oct 06 10:45:19 2009 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 13:06:36 2009 -0800" }, "message": "PCI: populate subsystem vendor and device IDs for PCI bridges\n\nChange to populate the subsystem vendor and subsytem device IDs for\nPCI-PCI bridges that implement the PCI Subsystem Vendor ID capability.\nPreviously bridges left subsystem vendor IDs unpopulated.\n\nSigned-off-by: Gabe Black \u003cgabe.black@ni.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "0584396157ad2d008e2cc76b4ed6254151183a25", "tree": "8860a033938b1a01cccf9a203208f741758724ac", "parents": [ "8792e11f1c54bcba34412f03959e70ee217f2231" ], "author": { "name": "Matt Domsch", "email": "Matt_Domsch@dell.com", "time": "Mon Nov 02 11:51:24 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 13:06:25 2009 -0800" }, "message": "PCI: PCIe AER: honor ACPI HEST FIRMWARE FIRST mode\n\nFeedback from Hidetoshi Seto and Kenji Kaneshige incorporated. This\ncorrectly handles PCI-X bridges, PCIe root ports and endpoints, and\nprints debug messages when invalid/reserved types are found in the\nHEST. PCI devices not in domain/segment 0 are not represented in\nHEST, thus will be ignored.\n\nToday, the PCIe Advanced Error Reporting (AER) driver attaches itself\nto every PCIe root port for which BIOS reports it should, via ACPI\n_OSC.\n\nHowever, _OSC alone is insufficient for newer BIOSes. Part of ACPI\n4.0 is the new APEI (ACPI Platform Error Interfaces) which is a way\nfor OS and BIOS to handshake over which errors for which components\neach will handle. One table in ACPI 4.0 is the Hardware Error Source\nTable (HEST), where BIOS can define that errors for certain PCIe\ndevices (or all devices), should be handled by BIOS (\"Firmware First\nmode\"), rather than be handled by the OS.\n\nDell PowerEdge 11G server BIOS defines Firmware First mode in HEST, so\nthat it may manage such errors, log them to the System Event Log, and\npossibly take other actions. The aer driver should honor this, and\nnot attach itself to devices noted as such.\n\nFurthermore, Kenji Kaneshige reminded us to disallow changing the AER\nregisters when respecting Firmware First mode. Platform firmware is\nexpected to manage these, and if changes to them are allowed, it could\nbreak that firmware\u0027s behavior.\n\nThe HEST parsing code may be replaced in the future by a more\nfeature-rich implementation. This patch provides the minimum needed\nto prevent breakage until that implementation is available.\n\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nReviewed-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Matt Domsch \u003cMatt_Domsch@dell.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "1ed6743918abbec69c0f0b725fa56e3c3248bbab", "tree": "01ea3d9aaf84746e42c4852c7e3c5295e1b42ce0", "parents": [ "af5a8ee05404112f38fb2904747c688bdc31a746" ], "author": { "name": "Michael S. Tsirkin", "email": "mst@redhat.com", "time": "Thu Oct 29 17:24:59 2009 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 08:59:40 2009 -0800" }, "message": "PCI: fix nit in ROM BAR size probing\n\nWhen probing for ROM BAR size, we should not change bits 1:10 in this\nBAR, because these bits are marked as \"reserved for future use\" in PCI\nspec, so changing them might have side effects.\n\nNo such issue for I/O or memory, as there is an implementation note in\nPCI spec which explicitly allows writing 0xfffffffff there.\n\nSigned-off-by: Michael S. Tsirkin \u003cmst@redhat.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "df0e97c6f1f2fdca686036998fe816cefd8e27d7", "tree": "8cef3a9d3dc141b804507fd8eed195ff8196a7c8", "parents": [ "ae21ee65e8bc228416bbcc8a1da01c56a847a60c" ], "author": { "name": "Allen Kay", "email": "allen.m.kay@intel.com", "time": "Wed Oct 07 10:27:51 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 08:47:26 2009 -0800" }, "message": "PCI: add xen dom0 checking before ACS initialization\n\nThis patch is predicated on Jeremy\u0027s patch in include/xen/xen.h. It\u0027ll\nprevent ACS init unless the platform has both an IOMMU and we\u0027re running\nas dom0.\n\nSigned-off-by: Allen Kay \u003callen.m.kay@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "ae21ee65e8bc228416bbcc8a1da01c56a847a60c", "tree": "cbcd109c764a8fed06f18a0a4bd3d63208405552", "parents": [ "1ccbf5344c3daef046d2323190cc6807c44f1917" ], "author": { "name": "Allen Kay", "email": "allen.m.kay@intel.com", "time": "Wed Oct 07 10:27:17 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 08:47:25 2009 -0800" }, "message": "PCI: acs p2p upsteram forwarding enabling\n\nNote: dom0 checking in v4 has been separated out into 2/2.\n\nThis patch enables P2P upstream forwarding in ACS capable PCIe switches.\nIt solves two potential problems in virtualization environment where a PCIe\ndevice is assigned to a guest domain using a HW iommu such as VT-d:\n\n1) Unintentional failure caused by guest physical address programmed\n into the device\u0027s DMA that happens to match the memory address range\n of other downstream ports in the same PCIe switch. This causes the PCI\n transaction to go to the matching downstream port instead of go to the\n root complex to get translated by VT-d as it should be.\n\n2) Malicious guest software intentionally attacks another downstream\n PCIe device by programming the DMA address into the assigned device\n that matches memory address range of the downstream PCIe port.\n\nWe are in process of implementing device filtering software in KVM/XEN\nmanagement software to allow device assignment of PCIe devices behind a PCIe\nswitch only if it has ACS capability and with the P2P upstream forwarding bits\nenabled. This patch is intended to work for both KVM and Xen environments.\n\nSigned-off-by: Allen Kay \u003callen.m.kay@intel.com\u003e\nReviewed-by: Mathew Wilcox \u003cwilly@linux.intel.com\u003e\nReviewed-by: Chris Wright \u003cchris@sous-sol.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "a369c791e881503a6253dafc0d0ad5e41e5557e5", "tree": "20de1e773f328875afbfaf96fedd3991e9288f68", "parents": [ "fd95541e23e2c9acb1e38cd41fc0c7cc37fceb53" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Tue Oct 06 15:33:44 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 08:47:18 2009 -0800" }, "message": "PCI: print resources consistently with %pRt\n\nThis uses %pRt to print additional resource information (type, size,\nprefetchability, etc.) consistently.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "4b77b0a2ba27d64f58f16d8d4d48d8319dda36ff", "tree": "957f38dc1065e2880197e7ca5ffe1592515010b3", "parents": [ "999cce4a52d5abdda5d2cec6bac241899bc19e4c" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Wed Sep 09 23:49:59 2009 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Sep 14 13:41:46 2009 -0700" }, "message": "PCI: Clear saved_state after the state has been restored\n\nSome PCI devices fail if their standard configuration registers are\nrestored twice in a row. Prevent this from happening by making\npci_restore_state() clear the saved_state flag of the device right\nafter the device\u0027s standard configuration registers have been\npopulated with the previously saved values.\n\nSimplify PCI PM callbacks by removing the direct clearing of\nstate_saved from them, as it shouldn\u0027t be necessary any more (except\nin pci_pm_thaw(), where it has to be cleared, so that the values saved\nduring the \"freeze\" phase of hibernation are not used later by mistake).\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "28760489a3f1e136c5ae8581c0fa8f63511f2f4c", "tree": "a3c890e9c8d9e98385691d56f5c007d280514fe5", "parents": [ "0ba379ec0fb182a87b8891c5754abbcd9c035b4f" ], "author": { "name": "Eric W. Biederman", "email": "ebiederm@aristanetworks.com", "time": "Wed Sep 09 14:09:24 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 14:10:24 2009 -0700" }, "message": "PCI: pcie: Ensure hotplug ports have a minimum number of resources\n\nIn general a BIOS may goof or we may hotplug in a hotplug controller.\nIn either case the kernel needs to reserve resources for plugging\nin more devices in the future instead of creating a minimal resource\nassignment.\n\nWe already do this for cardbus bridges I am just adding a variant\nfor pcie bridges.\n\nv2: Make testing for pcie hotplug bridges based on a flag.\n\n So far we only set the flag for pcie but a header_quirk\n could easily be added for the non-standard pci hotplug\n bridges.\n\nSigned-off-by: Eric W. Biederman \u003cebiederm@aristanetworks.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "d0b8cbed648334924728642eea879878bc930b33", "tree": "2b2efb88e84917b2fa267d8dda97865ca5dca3b7", "parents": [ "6dab62ee5a3bf4f71b8320c09db2e6022a19f40e" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Fri Aug 07 03:53:34 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:29:27 2009 -0700" }, "message": "PCI: print out pref if mmio is prefetchable\n\nWe already print it out for pci bridges, so also print it out for pci devices.\n\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "a7db50405216610c8a0d62b8b400180b6f366733", "tree": "d86aeb344ce4966cf2f7b69c1ec1cd5111372545", "parents": [ "7135a71b19be1faf48b7148d77844d03bc0717d6" ], "author": { "name": "Alex Chiang", "email": "achiang@hp.com", "time": "Mon Jun 22 08:08:07 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:29:18 2009 -0700" }, "message": "PCI: remove pcibios_scan_all_fns()\n\nThis was #define\u0027d as 0 on all platforms, so let\u0027s get rid of it.\n\nThis change makes pci_scan_slot() slightly easier to read.\n\nCc: Yoshinori Sato \u003cysato@users.sourceforge.jp\u003e\nCc: Tony Luck \u003ctony.luck@intel.com\u003e\nCc: David Howells \u003cdhowells@redhat.com\u003e\nCc: \"David S. Miller\" \u003cdavem@davemloft.net\u003e\nCc: Jeff Dike \u003cjdike@addtoit.com\u003e\nCc: Ingo Molnar \u003cmingo@redhat.com\u003e\nCc: Ivan Kokshaysky \u003cink@jurassic.park.msu.ru\u003e\nReviewed-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nAcked-by: Russell King \u003clinux@arm.linux.org.uk\u003e\nAcked-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\nAcked-by: Kyle McMartin \u003ckyle@mcmartin.ca\u003e\nAcked-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nAcked-by: Paul Mundt \u003clethal@linux-sh.org\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\nSigned-off-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "9fc39256508c18d2861de11622183dfb6e79de87", "tree": "75c030716b106de4d79e4828f34b8e6b0592b861", "parents": [ "6e3f36df0ffa433e273c89f1447c94382a9db49e" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Tue May 26 16:06:48 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Jun 16 14:29:31 2009 -0700" }, "message": "PCI: use pci_is_root_bus() in pci_read_bridge_bases()\n\nUse pci_is_root_bus() in pci_read_bridge_bases() to check if the pci\nbus is root, for code consistency.\n\nReviewed-by: Alex Chiang \u003cachiang@hp.com\u003e\nReviewed-by: Grant Grundler \u003cgrundler@parisc-linux.org\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "1f82de10d6b1d845155363c895c552e61b36b51a", "tree": "3e93b9d1c97ae48509133fbbec9c81b4823816a5", "parents": [ "67b5db6502ddd27d65dea43bf036abbd82d0dfc9" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Thu Apr 23 20:48:32 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 11 12:04:06 2009 -0700" }, "message": "PCI/x86: don\u0027t assume prefetchable ranges are 64bit\n\nWe should not assign 64bit ranges to PCI devices that only take 32bit\nprefetchable addresses.\n\nTry to set IORESOURCE_MEM_64 in 64bit resource of pci_device/pci_bridge\nand make the bus resource only have that bit set when all devices under\nit support 64bit prefetchable memory. Use that flag to allocate\nresources from that range.\n\nReported-by: Yannick \u003cyannick.roehlly@free.fr\u003e\nReviewed-by: Ivan Kokshaysky \u003cink@jurassic.park.msu.ru\u003e\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f79b1b146b52765ee38bfb91bb14eb850fa98017", "tree": "6085fffb1442801293b8132b5d3f2aa735d0abdd", "parents": [ "9fa7eb283c5cdc2b0f4a8cfe6387ed82e5e9a3d3" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Thu May 28 00:25:05 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 04 11:29:43 2009 +0100" }, "message": "PCI: use fixed-up device class when configuring device\n\nThe device class may be changed after the fixup, so re-read the class\nvalue from pci_dev when configuring the device. Otherwise some devices\nsuch as JMicron SATA controller won\u0027t work.\n\nReviewed-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nReviewed-by: Grant Grundler \u003cgrundler@parisc-linux.org\u003e\nTested-by: Marc Dionne \u003cmarc.c.dionne@gmail.com\u003e\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "0bb1be3e30bfc3e09fa0ff1e887ac7da4a16c3a2", "tree": "997b7e0dd0579c3aed6337c9ae24106ccab163b7", "parents": [ "044cd80942e47b9de0915b627902adf05c52377f" ], "author": { "name": "Matthew Wilcox", "email": "matthew@wil.cx", "time": "Thu Apr 16 13:31:10 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Apr 22 13:57:36 2009 -0700" }, "message": "x86/PCI: Move set_pci_bus_resources_arch_default into arch/x86\n\nCommit 30a18d6c3f1e774de656ebd8ff219d53e2ba4029 introduced a new\nfunction to set the PCI bus resources. Unfortunately, neither the\nauthor, nor the committers seemed to know that we already have somewhere\nto do that -- pcibios_fixup_bus(). This patch moves the hook (used only\nby the K8 code) into x86-specific code where it should have been in the\nfirst place.\n\nCc: Yinghai Lu \u003cyinghai.lu@sun.com\u003e\nSigned-off-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nAcked-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "5446a6bdb51e71da7a203e395b0b4c668d559a3a", "tree": "ac403024a02a2285defd433da068dc4415af0fbe", "parents": [ "52a8873ba4e82d6e87f8478b3e7f9c12d8b37c38" ], "author": { "name": "Alex Chiang", "email": "achiang@hp.com", "time": "Wed Apr 01 18:24:12 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Apr 06 11:26:07 2009 -0700" }, "message": "PCI: annotate pci_rescan_bus as __ref, not __devinit\n\npci_rescan_bus was annotated as __devinit, which is wrong,\nbecause it will never be part of device initialization.\nHowevever, we can\u0027t simply drop the annotation, because then we\nget section warnings about calling pci_scan_child_bus (which is\ncorrectly marked as __devinit).\n\npci_rescan_bus will only get built when CONFIG_HOTPLUG is set,\nmeaning that __devinit is a nop, so we know that pci_scan_child_bus\nhas not been freed.\n\nAnnotate as __ref to silence modpost.\n\nSigned-off-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "853346e4354c948b50a6fb0002f8af2cf5fbf2ae", "tree": "b577bc1e79a44c471635559f0bcbfce424309f73", "parents": [ "ceb93a9ff16612314d757874b6415ffbb2091576" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Sat Mar 21 22:05:11 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Mar 26 15:50:18 2009 -0700" }, "message": "PCI: fix conflict between SR-IOV and config space sizing\n\nNew pci_cfg_space_size() needs invalid pdev-\u003eclass, put it in the\nright place in the pci_setup_device().\n\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "705b1aaa823e800490f157cd9366ad8cff385f5f", "tree": "634ea8ba227a305074938f49c110fea8e68e8bb3", "parents": [ "3ed4fd96b3188406ac5357d9290bcffa08c65cf6" ], "author": { "name": "Alex Chiang", "email": "achiang@hp.com", "time": "Fri Mar 20 14:56:31 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 14:57:58 2009 -0700" }, "message": "PCI: Introduce /sys/bus/pci/rescan\n\nThis interface allows the user to force a rescan of all PCI buses\nin system, and rediscover devices that have been removed earlier.\n\npci_bus_attrs implementation from Trent Piepho.\n\nThanks to Vegard Nossum for discovering locking issues with the\nsysfs interface.\n\nCc: Trent Piepho \u003cxyzzy@speakeasy.org\u003e\nSigned-off-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "3ed4fd96b3188406ac5357d9290bcffa08c65cf6", "tree": "1e48401b56c35554e84c8d627c6c04e83a999a9e", "parents": [ "9dd90cafa7a712d283e2e0c625b022e19f746762" ], "author": { "name": "Alex Chiang", "email": "achiang@hp.com", "time": "Fri Mar 20 14:56:25 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 14:57:44 2009 -0700" }, "message": "PCI: Introduce pci_rescan_bus()\n\nThis API is used by the PCI core to rescan a bus and rediscover\nnewly added devices.\n\nOver time, it is expected that the various PCI hotplug drivers\nwill migrate to this interface and away from the old\npci_do_scan_bus() interface.\n\nSigned-off-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "74710ded8e16fc8dacbb702a5bac1a493d88549a", "tree": "274171a30a202a708a6aacbf9e0a693a2b5474ad", "parents": [ "1b69dfc649e6658fc38499cf704750d74cabc73d" ], "author": { "name": "Alex Chiang", "email": "achiang@hp.com", "time": "Fri Mar 20 14:56:10 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 14:57:21 2009 -0700" }, "message": "PCI: always scan child buses\n\nWhile scanning bridges, we stop our scan if we encounter a bus\nthat we\u0027ve seen before, to work around some buggy chipsets. This\nis a good idea, but prevents us from fully scanning the PCI bus\nat a future time (to find newly hot-added devices, for example).\n\nChange the logic so that we skip _re-adding_ an existing bus\nthat we\u0027ve seen before, but also allow the scan to descend to\nall child buses.\n\nNow that we\u0027re potentially scanning our child buses again, we\nalso need to be sure not to attempt re-initializing their BARs\nso we avoid that.\n\nThis patch lays the groundwork to allow the user to issue a\nrescan of the PCI bus at any time.\n\nSigned-off-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "1b69dfc649e6658fc38499cf704750d74cabc73d", "tree": "57dd8fff34d6be97a8bb19a733d3dc041ab81d0b", "parents": [ "90bdb3117f4209baa6d712b126f0e7791b24dc3f" ], "author": { "name": "Trent Piepho", "email": "xyzzy@speakeasy.org", "time": "Fri Mar 20 14:56:05 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 14:57:05 2009 -0700" }, "message": "PCI: pci_scan_slot() returns newly found devices\n\npci_scan_slot() has been rewritten to be less complex and will now\nreturn the number of *new* devices found.\n\nExisting callers need not worry because they already assume that\nthey can\u0027t call pci_scan_slot() on an already-scanned slot.\n\nThus, there is no semantic change for existing callers: returning\nnewly found devices (this patch) is exactly equal to returning all\nfound devices (before this patch).\n\nThis patch adds some more groundwork to allow us to rescan the\nPCI bus during runtime to discover newly added devices.\n\nSigned-off-by: Trent Piepho \u003cxyzzy@speakeasy.org\u003e\nReviewed-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "90bdb3117f4209baa6d712b126f0e7791b24dc3f", "tree": "5c2ca7ae062bc8aef2ce0ceb7f49e78b0329fb8a", "parents": [ "79af72d716cf1bb13b175429cf181a6c4d063ee8" ], "author": { "name": "Trent Piepho", "email": "xyzzy@speakeasy.org", "time": "Fri Mar 20 14:56:00 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 14:56:45 2009 -0700" }, "message": "PCI: don\u0027t scan existing devices\n\npci_scan_single_device is supposed to add newly discovered\ndevices to pci_bus-\u003edevices, but doesn\u0027t check to see if the\ndevice has already been added. This can cause problems if we ever\nwant to use this interface to rescan the PCI bus.\n\nIf the device is already added, just return it.\n\nSigned-off-by: Trent Piepho \u003cxyzzy@speakeasy.org\u003e\nSigned-off-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "480b93b7837fb3cf0579a42f4953ac463a5b9e1e", "tree": "39206460a790570d293dc04a64ab3fd3fff736ef", "parents": [ "a28724b0fb909d247229a70761c90bb37b13366a" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Fri Mar 20 11:25:14 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 10:48:25 2009 -0700" }, "message": "PCI: centralize device setup code\n\nMove the device setup stuff into pci_setup_device() which will be used\nto setup the Virtual Function later.\n\nReviewed-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "a28724b0fb909d247229a70761c90bb37b13366a", "tree": "7c5332004a8f52e676076b39aa03aeb45cb03f2a", "parents": [ "8c5cdb6adc6688b9b8fd82ea4a5cf4674dabad79" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Fri Mar 20 11:25:13 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 10:48:24 2009 -0700" }, "message": "PCI: reserve bus range for SR-IOV device\n\nReserve the bus number range used by the Virtual Function when\npcibios_assign_all_busses() returns true.\n\nReviewed-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "d1b054da8f599905f3c18a218961dcf17f9d5f13", "tree": "99b62e6771c3b73142dd0622463bed0e19724342", "parents": [ "8293b0f629095efbe7c7e3f9b437f8c040c19eb5" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Fri Mar 20 11:25:11 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 10:48:22 2009 -0700" }, "message": "PCI: initialize and release SR-IOV capability\n\nIf a device has the SR-IOV capability, initialize it (set the ARI\nCapable Hierarchy in the lowest numbered PF if necessary; calculate\nthe System Page Size for the VF MMIO, probe the VF Offset, Stride\nand BARs). A lock for the VF bus allocation is also initialized if\na PF is the lowest numbered PF.\n\nReviewed-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "dfadd9edff498d767008edc6b2a6e86a7a19934d", "tree": "155d439bb862292307b88975bf11cfd9b78d7df2", "parents": [ "745be2e700cdddd5da4e402854a484242c3628df" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Sun Mar 08 21:35:37 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 10:48:17 2009 -0700" }, "message": "PCI/x86: detect host bridge config space size w/o using quirks\n\nMany host bridges support a 4k config space, so check them directy\ninstead of using quirks to add them.\n\nWe only need to do this extra check for host bridges at this point,\nbecause only host bridges are known to have extended address space\nwithout also having a PCI-X/PCI-E caps. Other devices with this\nproperty could be done with quirks (if there are any).\n\nAs a bonus, we can remove the quirks for AMD host bridges with family\n10h and 11h since they\u0027re not needed any more.\n\nWith this patch, we can get correct pci cfg size of new Intel CPUs/IOHs\nwith host bridges.\n\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nAcked-by: H. Peter Anvin \u003chpa@zytor.com\u003e\nReviewed-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nCc: \u003cstable@kernel.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "6a3b3e26803fc823058fbb05abb5e0d92a52e1bd", "tree": "f868b0ef9c3d5d69f693fb73346f7f71266db092", "parents": [ "32a9a682bef2f6fce7026bd94d1ce20028b0e52d" ], "author": { "name": "Geert Uytterhoeven", "email": "geert@linux-m68k.org", "time": "Sun Mar 15 20:14:37 2009 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 10:48:15 2009 -0700" }, "message": "PCI: Use kzalloc() in pci_create_bus()\n\nSigned-off-by: Geert Uytterhoeven \u003cgeert@linux-m68k.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f92d4e29d785f1d4217dee7f1ae6ff7140547ed5", "tree": "55e272ffb250af61e3de804565d538b0cb92b0eb", "parents": [ "151ab36a2ea0b3181d103f7244636e0d16e685de" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Tue Feb 17 14:15:16 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 10:48:04 2009 -0700" }, "message": "PCI: fix wrong assumption in pci_read_bridge_bases\n\nCurrent pci_read_bridge_bases() has an assumption that pci_bus-\u003eself\nis NULL on the pci root bus (It checks pci_bus-\u003eself to see if the pci\nbus is root bus). But is might not true on some platforms. We must\ncheck pci_bus-\u003eparent instead.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "4e9b1c184cadbece3694603de5f880b6e35bd7a7", "tree": "8ae2ab8a4eaab4d46b4460284fd5ee475ce9a42d", "parents": [ "0176260fc30842e358cf34afa7dcd9413db44822", "36c401a44abcc389a00f9cd14892c9cf9bf0780d" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sat Jan 10 06:12:18 2009 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sat Jan 10 06:12:18 2009 -0800" }, "message": "Merge branch \u0027cpus4096-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip\n\n* \u0027cpus4096-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:\n [IA64] fix typo in cpumask_of_pcibus()\n x86: fix x86_32 builds for summit and es7000 arch\u0027s\n cpumask: use work_on_cpu in acpi-cpufreq.c for read_measured_perf_ctrs\n cpumask: use work_on_cpu in acpi-cpufreq.c for drv_read and drv_write\n cpumask: use cpumask_var_t in acpi-cpufreq.c\n cpumask: use work_on_cpu in acpi/cstate.c\n cpumask: convert struct cpufreq_policy to cpumask_var_t\n cpumask: replace CPUMASK_ALLOC etc with cpumask_var_t\n x86: cleanup remaining cpumask_t ops in smpboot code\n cpumask: update pci_bus_show_cpuaffinity to use new cpumask API\n cpumask: update local_cpus_show to use new cpumask API\n ia64: cpumask fix for is_affinity_mask_valid()\n" }, { "commit": "eb9c39d031bbcfd4005bd7e0337c3fd3909c1bf7", "tree": "1549b3fb7eb08296b7f7fe72582d7067098059db", "parents": [ "876e501ab25dcd683574a5d3d56d8fe450083ed6" ], "author": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Dec 17 12:10:05 2008 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Jan 07 11:13:07 2009 -0800" }, "message": "PCI: set device wakeup capable flag if platform support is present\n\nWhen PCI devices are initialized, we check whether they support PCI PM\ncaps and set the device can_wakeup flag if so. However, some devices\nmay have platform provided wakeup events rather than PCI PME signals, so\nwe need to set can_wakeup in that case too. Doing so should allow\nwakeups from many more devices, especially on cost constrained systems.\n\nReported-by: Alan Stern \u003cstern@rowland.harvard.edu\u003e\nTested-by: Joseph Chan \u003cJosephChan@via.com.tw\u003e\nAcked-by: \"Rafael J. Wysocki\" \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "3789fa8a2e534523c896a32a9f27f78d52ad7d82", "tree": "1bed5285a1188bf2455554118616403a8f929637", "parents": [ "0b400c7ed4d027e02f6231afa39852a2d48e6f25" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Sat Nov 22 02:41:07 2008 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Jan 07 11:13:03 2009 -0800" }, "message": "PCI: allow pci_alloc_child_bus() to handle a NULL bridge\n\nAllow pci_alloc_child_bus() to allocate buses without bridge devices.\nSome SR-IOV devices can occupy more than one bus number, but there is no\nexplicit bridges because that have internal routing mechanism.\n\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "0b400c7ed4d027e02f6231afa39852a2d48e6f25", "tree": "976e87d95aefac36b14c8407ff3ba9aa34f0cd03", "parents": [ "bc5f5a8277cb353161454b6704b3186ebcf3a2a3" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Sat Nov 22 02:40:40 2008 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Jan 07 11:13:02 2009 -0800" }, "message": "PCI: export __pci_read_base()\n\nExport __pci_read_base() so it can be used by whole PCI subsystem.\n\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "fde09c6d8f92de0c9f75698a75f0989f2234c517", "tree": "7d01ac3c194e87897185a2bf015f6d3b472e7601", "parents": [ "14add80b5120966fe0659d61815b9e9b4b68fdc5" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Sat Nov 22 02:39:32 2008 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Jan 07 11:13:01 2009 -0800" }, "message": "PCI: define PCI resource names in an \u0027enum\u0027\n\nThis patch moves all definitions of the PCI resource names to an \u0027enum\u0027,\nand also replaces some hard-coded resource variables with symbol\nnames. This change eases introduction of device specific resources.\n\nReviewed-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "63f4898ace2788a89ed685672aab092e1c3e50e6", "tree": "ed57eeeb486466697c3d97feaf34396dd2a2b992", "parents": [ "894886e5d3de0bde2eded8a39bf7e76023fbd791" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Sun Dec 07 22:02:58 2008 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Jan 07 11:12:40 2009 -0800" }, "message": "PCI: handle PCI state saving with interrupts disabled\n\nSince interrupts will soon be disabled at PCI resume time, we need to\npre-allocate memory to save/restore PCI config space (or use GFP_ATOMIC,\nbut this is safer).\n\nReported-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\nSigned-off-by: \"Rafael J. Wysocki\" \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "1a9271331ab663f3c7cda78d86b884f2ea86d4d7", "tree": "8d9334c0f1108fd785d5026a7eb9f6a2e95d3975", "parents": [ "bfb0f330a6c833fd12c35b907434256b4211a1dc" ], "author": { "name": "Kay Sievers", "email": "kay.sievers@vrfy.org", "time": "Thu Oct 30 02:17:49 2008 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Jan 07 11:12:23 2009 -0800" }, "message": "PCI: struct device - replace bus_id with dev_name(), dev_set_name()\n\nThis patch is part of a larger patch series which will remove\nthe \"char bus_id[20]\" name string from struct device. The device\nname is managed in the kobject anyway, and without any size\nlimitation, and just needlessly copied into \"struct device\".\n\nTo set and read the device name dev_name(dev) and dev_set_name(dev)\nmust be used. If your code uses static kobjects, which it shouldn\u0027t\ndo, \"const char *init_name\" can be used to statically provide the\nname the registered device should have. At registration time, the\ninit_name field is cleared, to enforce the use of dev_name(dev) to\naccess the device name at a later time.\n\nWe need to get rid of all occurrences of bus_id in the entire tree\nto be able to enable the new interface. Please apply this patch,\nand possibly convert any remaining remaining occurrences of bus_id.\n\nAcked-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\nSigned-Off-By: Kay Sievers \u003ckay.sievers@vrfy.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "588235bb53f2c215f0d4b08fd30b461fedc3338e", "tree": "0fbced18632ec129c9d4d7a6ff90e886078a389f", "parents": [ "3be83050d0143b515c5effe9c9d54edc41f1a2fa" ], "author": { "name": "Mike Travis", "email": "travis@sgi.com", "time": "Sun Jan 04 05:18:02 2009 -0800" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Sun Jan 04 15:39:26 2009 +0100" }, "message": "cpumask: update pci_bus_show_cpuaffinity to use new cpumask API\n\nImpact: use new cpumask API to reduce stack usage\n\nReplace the local cpumask_t variable with a pointer to the\nconst cpumask that needs to be printed.\n\nSigned-off-by: Mike Travis \u003ctravis@sgi.com\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "29c0177e6a4ac094302bed54a1d4bbb6b740a9ef", "tree": "d8ee57c5b40baa3f53d607b719344dd20f8c85a0", "parents": [ "98a79d6a50181ca1ecf7400eda01d5dc1bc0dbf0" ], "author": { "name": "Rusty Russell", "email": "rusty@rustcorp.com.au", "time": "Sat Dec 13 21:20:25 2008 +1030" }, "committer": { "name": "Rusty Russell", "email": "rusty@rustcorp.com.au", "time": "Sat Dec 13 21:20:25 2008 +1030" }, "message": "cpumask: change cpumask_scnprintf, cpumask_parse_user, cpulist_parse, and cpulist_scnprintf to take pointers.\n\nImpact: change calling convention of existing cpumask APIs\n\nMost cpumask functions started with cpus_: these have been replaced by\ncpumask_ ones which take struct cpumask pointers as expected.\n\nThese four functions don\u0027t have good replacement names; fortunately\nthey\u0027re rarely used, so we just change them over.\n\nSigned-off-by: Rusty Russell \u003crusty@rustcorp.com.au\u003e\nSigned-off-by: Mike Travis \u003ctravis@sgi.com\u003e\nAcked-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nCc: paulus@samba.org\nCc: mingo@redhat.com\nCc: tony.luck@intel.com\nCc: ralf@linux-mips.org\nCc: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\nCc: cl@linux-foundation.org\nCc: srostedt@redhat.com\n" }, { "commit": "a491913ff22c2b69d937d14296db6fa34dbff068", "tree": "9024125fb0c86166932e5258127c3e3968ed3e22", "parents": [ "be7bce250a88fbbb5a67204eb148bce8b798780a" ], "author": { "name": "Zhao, Yu", "email": "yu.zhao@intel.com", "time": "Mon Oct 13 21:02:27 2008 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Oct 23 16:17:47 2008 -0700" }, "message": "PCI: remove unused resource assignment in pci_read_bridge_bases()\n\nThis cleanup removes the resource assignment in pci_read_bridge_bases()\nsince it has taken care by pci_alloc_child_bus() when allocating the bus:\n\n /* Set up default resource pointers and names.. */\n for (i \u003d 0; i \u003c PCI_BRIDGE_RES_NUM; i++) {\n child-\u003eresource[i] \u003d \u0026bridge-\u003eresource[PCI_BRIDGE_RESOURCES+i];\n child-\u003eresource[i]-\u003ename \u003d child-\u003ename;\n }\n\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "a1c19894b786f10c76ac40e93c6b5d70c9b946d2", "tree": "4a03c1d7b9958c6fe328eeea13ee31a0edbb4478", "parents": [ "0b8b0dca9aad94878adaf4520f3f12bf9813f329" ], "author": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Tue Oct 21 10:06:29 2008 +1100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Oct 22 16:42:44 2008 -0700" }, "message": "PCI: Workaround invalid P2P bridge bus numbers\n\nSome firmware fail to properly configure P2P bridges, leaving them\nwith invalid bus numbers. In some cases, this happens on some embedded\n4xx boards as the result of the kernel allocating different bus space\nthan the firmware does to host bridges while not setting\npcibios_assign_all_busses() for various reasons. In other cases, it can\njust be bogus firmware.\n\nThis adds some sanity checking to the PCI probing code. If a bridge is\nfound whose primary bus number doesn\u0027t match the bus it\u0027s sitting on,\nor whose secondary bus number not strictly above it\u0027s primary bus\nnumber, then the bridge bus numbers are deconfigured in the first pass\nof pci_scan_bridge() to be re-assigned in the second pass.\n\nTested-by: \"Ayman El-Khashab\" \u003cAymanE@tanisys.com\u003e\nSigned-off-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f19aeb1f3638b7bb4ca21eb361f004fac2bfe259", "tree": "2990881affb22ba426149e8d4c317fe9df9992c7", "parents": [ "f393d9b130423a7a47c751b26df07ceaa5dc76a9" ], "author": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Fri Oct 03 19:49:32 2008 +1000" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Oct 20 11:01:46 2008 -0700" }, "message": "PCI: Add ability to mmap legacy_io on some platforms\n\nThis adds the ability to mmap legacy IO space to the legacy_io files\nin sysfs on platforms that support it. This will allow to clean up\nX to use this instead of /dev/mem for legacy IO accesses such as\nthose performed by Int10.\n\nWhile at it I moved pci_create/remove_legacy_files() to pci-sysfs.c\nwhere I think they belong, thus making more things statis in there\nand cleaned up some spurrious prototypes in the ia64 pci.h file\n\nSigned-off-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f393d9b130423a7a47c751b26df07ceaa5dc76a9", "tree": "c29cada52d6fce41d90a03c371861a7034cdded8", "parents": [ "58c3a727cb73b75a9104d295f096cca12959a5a5" ], "author": { "name": "Vincent Legoll", "email": "vincent.legoll@gmail.com", "time": "Sun Oct 12 12:26:12 2008 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Oct 20 11:01:45 2008 -0700" }, "message": "PCI: probing debug message uniformization\n\nThis patch uniformizes PCI probing debug boot messages with dev_printk()\nintead of manual printk()\n\nIt changes adress range output from [%llx, %llx] to [%#llx-%#llx], like\nin pci_request_region().\n\nFor example, it goes from the mixed-style:\n\nPCI: 0000:00:1b.0 reg 10 64bit mmio: [f4280000, f4283fff]\npci 0000:00:1b.0: PME# supported from D0 D3hot D3cold\n\nto uniform:\n\npci 0000:00:1b.0: reg 10 64bit mmio: [0xf4280000-0xf4283fff]\npci 0000:00:1b.0: PME# supported from D0 D3hot D3cold\n\nThis patch has been runtime tested, boot log messages diffed, everything\nlooks OK.\n\nAcked-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Vincent Legoll \u003cvincent.legoll@gmail.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "58c3a727cb73b75a9104d295f096cca12959a5a5", "tree": "70f1fe31f1ec12021777b6c6c49167356a864749", "parents": [ "201de56eb22f1ff3f36804bc70cbff220b50f067" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Tue Oct 14 14:02:53 2008 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Oct 20 10:54:32 2008 -0700" }, "message": "PCI: support PCIe ARI capability\n\nThis patch adds support for PCI Express Alternative Routing-ID\nInterpretation (ARI) capability.\n\nThe ARI capability extends the Function Number field of the PCI Express\nEndpoint by reusing the Device Number which is otherwise hardwired to 0.\nWith ARI, an Endpoint can have up to 256 functions.\n\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "201de56eb22f1ff3f36804bc70cbff220b50f067", "tree": "3613a9485bee233ab62bc9d747b40aa3b11eeec7", "parents": [ "280c73d3691fb182fa55b0160737c2c0feb79471" ], "author": { "name": "Zhao, Yu", "email": "yu.zhao@intel.com", "time": "Mon Oct 13 19:49:55 2008 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Oct 20 10:54:31 2008 -0700" }, "message": "PCI: centralize the capabilities code in probe.c\n\nThis patch centralizes the initialization and release functions of\nvarious PCI capabilities in probe.c, which makes the introduction\nof new capability support functions cleaner in the future.\n\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "e354597cce8d219d135d65e585dc4f30323486b9", "tree": "dbf2a270f874c5ef56250021927de9ce56392e35", "parents": [ "557848c3c03ad1d1e66cb3b5b06698e3a9ebc33c" ], "author": { "name": "Peter Chubb", "email": "peterc@gelato.unsw.edu.au", "time": "Mon Oct 13 11:49:04 2008 +1100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Oct 20 10:54:30 2008 -0700" }, "message": "PCI: fix 64-vbit prefetchable memory resource BARs\n\nSince patch 6ac665c63dcac8fcec534a1d224ecbb8b867ad59 my infiniband\ncontroller hasn\u0027t worked. This is because it has 64-bit prefetchable\nmemory, which was mistakenly being taken to be 32-bit memory. The\nresource flags in this case are PCI_BASE_ADDRESS_MEM_TYPE_64 |\nPCI_BASE_ADDRESS_MEM_PREFETCH.\n\nThis patch checks only for the PCI_BASE_ADDRESS_MEM_TYPE_64 bit; thus\nwhether the region is prefetchable or not is ignored. This fixes my\nInfiniband.\n\nReviewed-by: Matthew Wilcox \u003cmatthew@wil.cx\u003e\nSigned-off-by: Peter Chubb \u003cpeterc@gelato.unsw.edu.au\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "557848c3c03ad1d1e66cb3b5b06698e3a9ebc33c", "tree": "f244d69c332d3bbbef9f924fb1f0892abba7e1ff", "parents": [ "022edd86d7c864bc8fadc3c8ac4e6a464472ab05" ], "author": { "name": "Zhao, Yu", "email": "yu.zhao@intel.com", "time": "Mon Oct 13 19:18:07 2008 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Oct 20 10:54:29 2008 -0700" }, "message": "PCI: replace cfg space size (256/4096) by macros.\n\nThis is a cleanup that changes all PCI configuration space size\nrepresentations to the macros (PCI_CFG_SPACE_SIZE and\nPCI_CFG_SPACE_EXP_SIZE). And the macros are also moved from\ndrivers/pci/probe.c to drivers/pci/pci.h.\n\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "cef354db0d7a7207ea78c716753d9216a9c2b7e1", "tree": "bd8c0c6356f852b10117a166b67d2b017445ce2b", "parents": [ "93ff68a55aa92180a765d6c51c3303f6200167a6" ], "author": { "name": "Alex Chiang", "email": "achiang@hp.com", "time": "Tue Sep 02 09:40:51 2008 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Oct 20 10:53:52 2008 -0700" }, "message": "PCI: connect struct pci_dev to struct pci_slot\n\nThe introduction of struct pci_slot (f46753c5e354b857b20ab8e0fe7b25)\nadded a struct pci_slot pointer to struct pci_dev, but we forgot to\nassociate the two.\n\nConnect the two structs together; the interesting portions of the object\nlifetimes are:\n\n\t- when a new pci_slot is created, connect it to the appropriate\n\t pci_dev\u0027s. A single pci_slot may be associated with multiple\n\t pci_dev\u0027s, e.g. any multi-function PCI device.\n\n\t- when a pci_slot is released, look for all the pci_dev\u0027s it was\n\t associated with, and set their pci_slot pointers to NULL\n\n\t- when a pci_dev is created, look for slots to associate with.\n\nNote -- when a pci_dev is released, we don\u0027t need to do any bookkeeping,\nsince pci_slot\u0027s do not have pointers to pci_dev\u0027s.\n\nSigned-off-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "34a2e15e95fce6d6f4d30162f53a0ceb25d5bbaf", "tree": "878e3c7ac9dabd8fa7faca870bc01c1972218602", "parents": [ "d768cb6929773060171eee8397a63883f60ddc07" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Mon Aug 25 15:45:20 2008 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Oct 20 10:53:43 2008 -0700" }, "message": "PCI: follow lspci device/vendor style\n\nUse \"[%04x:%04x]\" for PCI vendor/device IDs to follow the format\nused by lspci(8).\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "096e6f673dc02a6394dc9a7d8f8735c6978f5b91", "tree": "50e9f463b089dc1b62c3f260a27d500040534525", "parents": [ "332d2e7834986a9326ec3fa6a91641daef81746c" ], "author": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Mon Oct 20 15:07:37 2008 +1100" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Oct 20 09:12:32 2008 -0700" }, "message": "pci: Use new %pR to print resource ranges\n\nThis converts things in drivers/pci to use %pR to printout the\ncontent of a struct resource instead of hand-casted %llx or\nother variants.\n\nSigned-off-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "99178b036c97293a65004ff5ec5cff9f833aaecd", "tree": "c83ac6855710038ad9846f79b952b7fdcca528f8", "parents": [ "26853ab6f9a4c482be4b638477335704724d4854" ], "author": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Tue Aug 26 11:00:57 2008 -0500" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Thu Oct 16 09:24:52 2008 -0700" }, "message": "Driver core: add bus_sort_breadthfirst() function\n\nThe PCI core wants to reorder the devices in the bus list. So move this\nfunctionality out of the pci core and into the driver core so that\nanyone else can also do this if needed. This also lets us change how\nstruct device is attached to drivers in the future without messing with\nthe PCI core.\n\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n" }, { "commit": "395a125c6237802b19bf22b41017c99ff57f1024", "tree": "9a2ca5bf2508fa865ab1ed973a997f15eb2be419", "parents": [ "a5827f40afafc864f57a1c44915f0bfaf3d94f53" ], "author": { "name": "Yinghai Lu", "email": "yhlu.kernel@gmail.com", "time": "Tue Sep 09 12:27:52 2008 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Sep 12 16:34:46 2008 -0700" }, "message": "PCI: re-add debug prints for unmodified BARs\n\nPrint out for device BAR values before the kernel tries to update them.\nAlso make related output use KERN_DEBUG.\n\nSigned-off-by: Yinghai Lu \u003cyhlu.kernel@gmail.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "4ca8a7726fb0e8094fdb56f2ae2d69fcf9254eae", "tree": "17d2a4de82ee1ec9024a15b006ff9edf87a94673", "parents": [ "cbda1ba898647aeb4ee770b803c922f595e97731" ], "author": { "name": "Johann Felix Soden", "email": "johfel@users.sourceforge.net", "time": "Fri Aug 22 20:46:59 2008 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Sep 09 11:43:32 2008 -0700" }, "message": "PCI: Fix printk warnings in probe.c\n\nThe cleaned up resource code in probe.c introduced some warnings:\ndrivers/pci/probe.c: In function \u0027pci_read_bridge_bases\u0027:\ndrivers/pci/probe.c:386: warning: format \u0027%llx\u0027 expects type \u0027long long unsigned int\u0027, but argument 3 has type \u0027resource_size_t\u0027\ndrivers/pci/probe.c:386: warning: format \u0027%llx\u0027 expects type \u0027long long unsigned int\u0027, but argument 4 has type \u0027resource_size_t\u0027\ndrivers/pci/probe.c:398: warning: format \u0027%llx\u0027 expects type \u0027long long unsigned int\u0027, but argument 3 has type \u0027resource_size_t\u0027\ndrivers/pci/probe.c:398: warning: format \u0027%llx\u0027 expects type \u0027long long unsigned int\u0027, but argument 4 has type \u0027resource_size_t\u0027\ndrivers/pci/probe.c:434: warning: format \u0027%llx\u0027 expects type \u0027long long unsigned int\u0027, but argument 4 has type \u0027resource_size_t\u0027\ndrivers/pci/probe.c:434: warning: format \u0027%llx\u0027 expects type \u0027long long unsigned int\u0027, but argument 5 has type \u0027resource_size_t\u0027\n\nSo fix them up.\n\nSigned-off-by: Johann Felix Soden \u003cjohfel@users.sourceforge.net\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "ce6754235b423610e91f5300e1555c2e4ee1c03a", "tree": "75233676c8145a4974dee0ec71a9bba2df33a704", "parents": [ "89499759dc0dd300528510f465b0bf532fc79a2a", "a83fe32fa668c0a17b3f99a1480b006f7d649924" ], "author": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Aug 18 09:54:13 2008 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Aug 18 09:54:13 2008 -0700" }, "message": "Merge branch \u0027pci-for-jesse\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip into x86-merge\n\nConflicts:\n\n\tdrivers/pci/probe.c\n" }, { "commit": "a844158a642ffe8b3b29964a88ee802c2834ed0a", "tree": "05ab9fe0a7b31af7f2885fd07ef1bfda50b977ba", "parents": [ "abad2ec98f2ef357d62026cbc3989dabf33f2435" ], "author": { "name": "Simon Horman", "email": "horms@verge.net.au", "time": "Thu Aug 07 14:56:34 2008 +1000" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Aug 07 09:49:07 2008 -0700" }, "message": "PCI: check the return value of device_create_bin_file() in pci_create_bus()\n\nCheck the return value of device_create_bin_file in pci_create_bus and\nunwind if necessary. Don\u0027t propagate error to caller, as failure to create\nthese files shouldn\u0027t prevent PCI from being initialised. Instead, just\nlog a warning.\n\nCc: Sven Wegener \u003csven.wegener@stealer.net\u003e\nCc: Michael Ellerman \u003cmichael@ellerman.id.au\u003e\nCc: Matthew Wilcox \u003cmatthew@wil.cx\u003e\nSigned-off-by: Simon Horman \u003chorms@verge.net.au\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "149e16372a2066c5474d8a8db9b252afd57eb427", "tree": "075a46f0672739fdab18d2f1e5f06080160de8b0", "parents": [ "5fde244d39b88625ac578d83e6625138714de031" ], "author": { "name": "Shaohua Li", "email": "shaohua.li@intel.com", "time": "Wed Jul 23 10:32:31 2008 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Jul 28 14:56:57 2008 -0700" }, "message": "PCI: disable ASPM on pre-1.1 PCIe devices\n\nDisable ASPM on pre-1.1 PCIe devices, as many of them don\u0027t implement it\ncorrectly.\n\nTested-by: Jack Howarth \u003chowarth@bromo.msbb.uc.edu\u003e\nSigned-off-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "cc5499c3a607a392e8a7adb934aaf14b2c6a3519", "tree": "d7ab414b929fed34d9b15bf0c636e9591c4673dd", "parents": [ "6ac665c63dcac8fcec534a1d224ecbb8b867ad59" ], "author": { "name": "Matthew Wilcox", "email": "matthew@wil.cx", "time": "Mon Jul 28 13:39:00 2008 -0400" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Jul 28 14:29:04 2008 -0700" }, "message": "PCI: handle 64-bit resources better on 32-bit machines\n\nIf the kernel is configured to support 64-bit resources on a 32-bit\nmachine, we can support 64-bit BARs properly. Just change the condition\nto check sizeof(resource_size_t) instead of BITS_PER_LONG.\n\nSigned-off-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "6ac665c63dcac8fcec534a1d224ecbb8b867ad59", "tree": "c331b97a2a7a5dfc6353f2538e5fd66a0d9a854d", "parents": [ "37139074233a5bbec54ae01ab580e5788a248cc3" ], "author": { "name": "Matthew Wilcox", "email": "matthew@wil.cx", "time": "Mon Jul 28 13:38:59 2008 -0400" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Jul 28 14:28:53 2008 -0700" }, "message": "PCI: rewrite PCI BAR reading code\n\nFactor out the code to read one BAR from the loop in pci_read_bases into\na new function, __pci_read_base. The new code is slightly more\nreadable, better commented and removes the ifdef.\n\nSigned-off-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "0679c2f47d50651018dd5e0bf35330f6e6ae35ec", "tree": "2df65ebb958f930abf0b7ad35fd6e528398b1679", "parents": [ "76fbc263ff7e42ce8b21b8aee176e3c74b45f81a", "5b664cb235e97afbf34db9c4d77f08ebd725335e" ], "author": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Fri Jul 18 22:39:59 2008 +0200" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Fri Jul 18 22:39:59 2008 +0200" }, "message": "Merge branch \u0027linus\u0027 into pci-for-jesse\n" }, { "commit": "eb9d0fe40e313c0a74115ef456a2e43a6c8da72f", "tree": "7a90a68b8dc152d49a38469fd6a6a7840954bac2", "parents": [ "0af4b8c4fb31193dc666f4893107a18fef82baab" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Mon Jul 07 03:34:48 2008 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Jul 07 16:26:28 2008 -0700" }, "message": "PCI ACPI: Rework PCI handling of wake-up\n\n* Introduce function acpi_pm_device_sleep_wake() for enabling and\n disabling the system wake-up capability of devices that are power\n manageable by ACPI.\n\n* Introduce function acpi_bus_can_wakeup() allowing other (dependent)\n subsystems to check if ACPI is able to enable the system wake-up\n capability of given device.\n\n* Introduce callback .sleep_wake() in struct pci_platform_pm_ops and\n for the ACPI PCI \u0027driver\u0027 make it use acpi_pm_device_sleep_wake().\n\n* Introduce callback .can_wakeup() in struct pci_platform_pm_ops and\n for the ACPI \u0027driver\u0027 make it use acpi_bus_can_wakeup().\n\n* Move the PME# handlig code out of pci_enable_wake() and split it\n into two functions, pci_pme_capable() and pci_pme_active(),\n allowing the caller to check if given device is capable of\n generating PME# from given power state and to enable/disable the\n device\u0027s PME# functionality, respectively.\n\n* Modify pci_enable_wake() to use the new ACPI callbacks and the new\n PME#-related functions.\n\n* Drop the generic .platform_enable_wakeup() callback that is not\n used any more.\n\n* Introduce device_set_wakeup_capable() that will set the\n power.can_wakeup flag of given device.\n\n* Rework PCI device PM initialization so that, if given device is\n capable of generating wake-up events, either natively through the\n PME# mechanism, or with the help of the platform, its\n power.can_wakeup flag is set and its power.should_wakeup flag is\n unset as appropriate.\n\n* Make ACPI set the power.can_wakeup flag for devices found to be\n wake-up capable by it.\n\n* Make the ACPI wake-up code enable/disable GPEs for devices that\n have the wakeup.flags.prepared flag set (which means that their\n wake-up power has been enabled).\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "eebfcfb52ce753eaaa8525078bda6b539586066c", "tree": "8c1c841c5365fe12051a3c1f043bb3c528d50a90", "parents": [ "80be038593dba7aa46fb24a14f0ba83e5ade0edb" ], "author": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Wed Jul 02 13:24:49 2008 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jul 03 12:30:59 2008 -0700" }, "message": "PCI: handle pci_name() being const\n\nThis changes pci_setup_device to handle pci_name() now returning a\nconstant string.\n\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "8b285ce84bbc719e363a796f466404576b840d36", "tree": "05fb0faca73afc594f9dca60f4b2be742b0d60ae", "parents": [ "9433f6dd3a4677e9b92c6e1cd7f98b11598b7c2c" ], "author": { "name": "David Howells", "email": "dhowells@redhat.com", "time": "Fri Jun 27 13:23:20 2008 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jun 27 13:09:02 2008 -0700" }, "message": "PCI: fix pci_setup_device()\u0027s sprinting into a const buffer\n\nMake pci_setup_device() write the bus ID directly into the allotted storage,\nrather than using pci_name() as the address as that now returns a const\npointer.\n\nSigned-off-by: David Howells \u003cdhowells@redhat.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "80ccba1186d48fa728dc4b1456cc07ffb07da501", "tree": "b58826b8d0e42e2a41e5f5632bf95e52f9dfc676", "parents": [ "b86ec7ed2877f560ff069e8ed1b433a9005619c6" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Fri Jun 13 10:52:11 2008 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Jun 25 16:05:13 2008 -0700" }, "message": "PCI: use dev_printk when possible\n\nConvert printks to use dev_printk().\n\nI converted pr_debug() to dev_dbg(). Both use KERN_DEBUG and are enabled\nonly when DEBUG is defined.\n\nI converted printk(KERN_DEBUG) to dev_printk(KERN_DEBUG), not to dev_dbg(),\nbecause dev_dbg() is only enabled when DEBUG is defined.\n\nI converted DBG(KERN_INFO) (only in setup-bus.c) to dev_info(). The DBG()\nname makes it sound like debug, but it\u0027s been enabled forever, so dev_info()\npreserves the previous behavior.\n\nI tried to make the resource assignment formats more consistent, e.g.,\n \"BAR %d: got res [%#llx-%#llx] bus [%#llx-%#llx] flags %#lx\\n\"\ninstead of sometimes using \"start-end\" and sometimes using \"size@start\".\nI\u0027m not attached to one or the other; I\u0027d just like them consistent.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "9bf8a1a79d549a0cf3b26c88d1ac8cdf07deafee", "tree": "a4916a9e8e6be55be0893d9b45dc6147fd161509", "parents": [ "066519068ad2fbe98c7f45552b1f592903a9c8c8" ], "author": { "name": "Yinghai Lu", "email": "yhlu.kernel@gmail.com", "time": "Mon Jun 23 20:33:06 2008 +0200" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Mon Jun 23 21:57:19 2008 +0200" }, "message": "pci: debug extra pci resources range\n\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "f46753c5e354b857b20ab8e0fe7b2579831dc369", "tree": "efffdb4dfec5e1f6fd624f17aa36d7d350bb1e6c", "parents": [ "fe99740cac117f208707488c03f3789cf4904957" ], "author": { "name": "Alex Chiang", "email": "achiang@hp.com", "time": "Tue Jun 10 15:28:50 2008 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Jun 10 14:37:03 2008 -0700" }, "message": "PCI: introduce pci_slot\n\nCurrently, /sys/bus/pci/slots/ only exposes hotplug attributes when a\nhotplug driver is loaded, but PCI slots have attributes such as address,\nspeed, width, etc. that are not related to hotplug at all.\n\nIntroduce pci_slot as the primary data structure and kobject model.\nHotplug attributes described in hotplug_slot become a secondary\nstructure associated with the pci_slot.\n\nThis patch only creates the infrastructure that allows the separation of\nPCI slot attributes and hotplug attributes. In this patch, the PCI\nhotplug core remains the only user of this infrastructure, and thus,\n/sys/bus/pci/slots/ will still only become populated when a hotplug\ndriver is loaded.\n\nA later patch in this series will add a second user of this new\ninfrastructure and demonstrate splitting the task of exposing pci_slot\nattributes from hotplug_slot attributes.\n\n - Make pci_slot the primary sysfs entity. hotplug_slot becomes a\n subsidiary structure.\n o pci_create_slot() creates and registers a slot with the PCI core\n o pci_slot_add_hotplug() gives it hotplug capability\n\n - Change the prototype of pci_hp_register() to take the bus and\n slot number (on parent bus) as parameters.\n\n - Remove all the -\u003eget_address methods since this functionality is\n now handled by pci_slot directly.\n\n[achiang@hp.com: rpaphp-correctly-pci_hp_register-for-empty-pci-slots]\nTested-by: Badari Pulavarty \u003cpbadari@us.ibm.com\u003e\nAcked-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\n[akpm@linux-foundation.org: build fix]\n[akpm@linux-foundation.org: make headers_check happy]\n[akpm@linux-foundation.org: nuther build fix]\n[akpm@linux-foundation.org: fix typo in #include]\nSigned-off-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Matthew Wilcox \u003cmatthew@wil.cx\u003e\nCc: Greg KH \u003cgreg@kroah.com\u003e\nCc: Kristen Carlson Accardi \u003ckristen.c.accardi@intel.com\u003e\nCc: Len Brown \u003clenb@kernel.org\u003e\nAcked-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "49db139955d3392c6c4facf987905d0a9afed581", "tree": "a6add566bb0fefbddd09d53e26b680be3ccd3a9b", "parents": [ "e1a2a51e684bfe9d6165992d4a065439617a3107" ], "author": { "name": "Zhao Yakui", "email": "yakui.zhao@intel.com", "time": "Tue May 13 11:15:05 2008 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Jun 10 10:59:47 2008 -0700" }, "message": "PCI: Disable PME during PCI scan\n\nIf a device supports #PME and can generate PME events from D0, we may see\nsuperfluous events before a driver is loaded (drivers should only enable PME as\nneeded), preventing suspend from working if the corresponding GPE was enabled.\n\nLikewise, if the ACPI device has the _PRW object, the _PSW/_DSW object will be\ncalled in order to disable the wakeup functionality. But when it is allowed to\nwake up the sleeping state, OSPM will enable it again.\n\nSo we should disable PME in the course of scanning PCI devices and enable it\nagain only when PME events are actually required to be generated from the\nrequested PCI state (for example, D3_hot or D3_cold). It is also safe to\ndisable PME again when the PME is disabled for the PCI devices.\n\nSigned-off-by: Zhao Yakui \u003cyakui.zhao@intel.com\u003e\nSigned-off-by: Li Shaohua \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "70b9f7dc1435412ca2b89b13a8353bd9915a7189", "tree": "1ba8594fd9a26386654f800b9db5ce0183a0e33b", "parents": [ "98db6f193c93e9b4729215af2c9101210e11d26c" ], "author": { "name": "Yinghai Lu", "email": "yhlu.kernel.send@gmail.com", "time": "Mon Apr 28 16:27:23 2008 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Apr 29 15:34:05 2008 -0700" }, "message": "x86/pci: remove flag in pci_cfg_space_size_ext\n\nso let pci_cfg_space_size call it directly without flag.\n\nSigned-off-by: Yinghai Lu \u003cyhlu.kernel@gmail.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "30a18d6c3f1e774de656ebd8ff219d53e2ba4029", "tree": "22aad98a32fc182736f78193938a24175a168b81", "parents": [ "35ddd068fb94b187e94a3fc497ccecf27bdda9ae" ], "author": { "name": "Yinghai Lu", "email": "Yinghai.Lu@Sun.COM", "time": "Tue Feb 19 03:21:20 2008 -0800" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Sat Apr 26 23:41:04 2008 +0200" }, "message": "x86: multi pci root bus with different io resource range, on 64-bit\n\nscan AMD opteron io/mmio routing to make sure every pci root bus get correct\nresource range. Thus later pci scan could assign correct resource to device\nwith unassigned resource.\n\nthis can fix a system without _CRS for multi pci root bus.\n\nSigned-off-by: Yinghai Lu \u003cyinghai.lu@sun.com\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "0d358f22f6c8f03ab215eee8d52b74f78cc3c7db", "tree": "a60a05c5b5a2727ef6e82b273aafe2121373d93d", "parents": [ "d39398a333ddc490f842ccdd4b76c9674682aa5d" ], "author": { "name": "Yinghai Lu", "email": "Yinghai.Lu@Sun.COM", "time": "Tue Feb 19 03:20:41 2008 -0800" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Sat Apr 26 23:41:04 2008 +0200" }, "message": "driver core: try parent numa_node at first before using default\n\nin the device_add, we try to use use parent numa_node.\nneed to make sure pci root bus\u0027s bridge device numa_node is set.\nthen we could use device-\u003enuma_node direclty for all device.\nand don\u0027t need to call pcibus_to_node().\n\nSigned-off-by: Yinghai Lu \u003cyinghai.lu@sun.com\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "57741a779070e0b141b6148136b420c8d35ccbce", "tree": "779acceb9fbb746346385be6d5402d1834974f54", "parents": [ "05c58b8ac77639c17205f0b2a2d9eb1971dc47ad" ], "author": { "name": "Yinghai Lu", "email": "Yinghai.Lu@Sun.COM", "time": "Fri Feb 15 01:32:50 2008 -0800" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Sat Apr 26 23:41:03 2008 +0200" }, "message": "x86_64: set cfg_size for AMD Family 10h in case MMCONFIG\n\nreuse pci_cfg_space_size but skip check pci express and pci-x CAP ID.\n\nSigned-off-by: Yinghai Lu \u003cyinghai.lu@sun.com\u003e\nCc: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nAcked-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n" }, { "commit": "bda0c0afa7a694bb1459fd023515aca681e4d79a", "tree": "cd8b9d9811463de2065cbe79d59689082d6c53cf", "parents": [ "904e0ab54b7591b9cb01cfc0dbbedcc8bc0d949b", "af40b485ea2d957ae2f237ab0e33539ae8f29562" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Apr 21 15:58:35 2008 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Apr 21 15:58:35 2008 -0700" }, "message": "Merge git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/pci-2.6\n\n* git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/pci-2.6: (42 commits)\n PCI: Change PCI subsystem MAINTAINER\n PCI: pci-iommu-iotlb-flushing-speedup\n PCI: pci_setup_bridge() mustn\u0027t be __devinit\n PCI: pci_bus_size_cardbus() mustn\u0027t be __devinit\n PCI: pci_scan_device() mustn\u0027t be __devinit\n PCI: pci_alloc_child_bus() mustn\u0027t be __devinit\n PCI: replace remaining __FUNCTION__ occurrences\n PCI: Hotplug: fakephp: Return success, not ENODEV, when bus rescan is triggered\n PCI: Hotplug: Fix leaks in IBM Hot Plug Controller Driver - ibmphp_init_devno()\n PCI: clean up resource alignment management\n PCI: aerdrv_acpi.c: remove unneeded NULL check\n PCI: Update VIA CX700 quirk\n PCI: Expose PCI VPD through sysfs\n PCI: iommu: iotlb flushing\n PCI: simplify quirk debug output\n PCI: iova RB tree setup tweak\n PCI: parisc: use generic pci_enable_resources()\n PCI: ppc: use generic pci_enable_resources()\n PCI: powerpc: use generic pci_enable_resources()\n PCI: ia64: use generic pci_enable_resources()\n ...\n" }, { "commit": "7f7b5de2c0e10aa35ad9909edb1af9f2aed2f5d0", "tree": "fc73e811e2abe970970e216eeef4e61e3ba9bacc", "parents": [ "cbd4e055fc8f09db82d31a5ff6cec3c083cc97a8" ], "author": { "name": "Adrian Bunk", "email": "bunk@kernel.org", "time": "Fri Apr 18 13:53:55 2008 -0700" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Sun Apr 20 21:47:12 2008 -0700" }, "message": "PCI: pci_scan_device() mustn\u0027t be __devinit\n\nWARNING: drivers/pci/built-in.o(.text+0x150f): Section mismatch in reference from the function pci_scan_single_device() to the function .devinit.text:pci_scan_device()\n\nSigned-off-by: Adrian Bunk \u003cbunk@kernel.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n" }, { "commit": "cbd4e055fc8f09db82d31a5ff6cec3c083cc97a8", "tree": "ed245f6575243928865df0acdf0a7302418e2139", "parents": [ "66bef8c059015ba2b36bb5759080336feb01e680" ], "author": { "name": "Adrian Bunk", "email": "bunk@kernel.org", "time": "Fri Apr 18 13:53:55 2008 -0700" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Sun Apr 20 21:47:11 2008 -0700" }, "message": "PCI: pci_alloc_child_bus() mustn\u0027t be __devinit\n\nWARNING: drivers/pci/built-in.o(.text+0xc4c): Section mismatch in reference from the function pci_add_new_bus() to the function .devinit.text:pci_alloc_child_bus()\n\nSigned-off-by: Adrian Bunk \u003cbunk@kernel.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n" }, { "commit": "884525655d07fdee9245716b998ecdc45cdd8007", "tree": "975cbf2b5079430240d3496323df1a266be95d27", "parents": [ "d75b305295c38ba9610ff3b2200f7d1989dc55fd" ], "author": { "name": "Ivan Kokshaysky", "email": "ink@jurassic.park.msu.ru", "time": "Sun Mar 30 19:50:14 2008 +0400" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Sun Apr 20 21:47:08 2008 -0700" }, "message": "PCI: clean up resource alignment management\n\nDone per Linus\u0027 request and suggestions. Linus has explained that\nbetter than I\u0027ll be able to explain:\n\nOn Thu, Mar 27, 2008 at 10:12:10AM -0700, Linus Torvalds wrote:\n\u003e Actually, before we go any further, there might be a less intrusive\n\u003e alternative: add just a couple of flags to the resource flags field (we\n\u003e still have something like 8 unused bits on 32-bit), and use those to\n\u003e implement a generic \"resource_alignment()\" routine.\n\u003e\n\u003e Two flags would do it:\n\u003e\n\u003e - IORESOURCE_SIZEALIGN: size indicates alignment (regular PCI device\n\u003e resources)\n\u003e\n\u003e - IORESOURCE_STARTALIGN: start field is alignment (PCI bus resources\n\u003e during probing)\n\u003e\n\u003e and then the case of both flags zero (or both bits set) would actually be\n\u003e \"invalid\", and we would also clear the IORESOURCE_STARTALIGN flag when we\n\u003e actually allocate the resource (so that we don\u0027t use the \"start\" field as\n\u003e alignment incorrectly when it no longer indicates alignment).\n\u003e\n\u003e That wouldn\u0027t be totally generic, but it would have the nice property of\n\u003e automatically at least add sanity checking for that whole \"res-\u003estart has\n\u003e the odd meaning of \u0027alignment\u0027 during probing\" and remove the need for a\n\u003e new field, and it would allow us to have a generic \"resource_alignment()\"\n\u003e routine that just gets a resource pointer.\n\nBesides, I removed IORESOURCE_BUS_HAS_VGA flag which was unused for ages.\n\nSigned-off-by: Ivan Kokshaysky \u003cink@jurassic.park.msu.ru\u003e\nCc: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\nCc: Gary Hade \u003cgaryhade@us.ibm.com\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n" }, { "commit": "94e6108803469a37ee1e3c92dafdd1d59298602f", "tree": "7f3ee30721411cca238f8eea5971d5bebbb70a55", "parents": [ "5e0d2a6fc094a9b5047998deefeb1254c66856ee" ], "author": { "name": "Ben Hutchings", "email": "bhutchings@solarflare.com", "time": "Wed Mar 05 16:52:39 2008 +0000" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Sun Apr 20 21:47:07 2008 -0700" }, "message": "PCI: Expose PCI VPD through sysfs\n\nVital Product Data (VPD) may be exposed by PCI devices in several\nways. It is generally unsafe to read this information through the\nexisting interfaces to user-land because of stateful interfaces.\n\nThis adds:\n- abstract operations for VPD access (struct pci_vpd_ops)\n- VPD state information in struct pci_dev (struct pci_vpd)\n- an implementation of the VPD access method specified in PCI 2.2\n (in access.c)\n- a \u0027vpd\u0027 binary file in sysfs directories for PCI devices with VPD\n operations defined\n\nIt adds a probe for PCI 2.2 VPD in pci_scan_device() and release of\nVPD state in pci_release_dev().\n\nSigned-off-by: Ben Hutchings \u003cbhutchings@solarflare.com\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n" }, { "commit": "7d715a6c1ae5785d00fb9a876b5abdfc43abc44b", "tree": "58ec6d1969739a590e0c6c976bfebf04c8e9f31e", "parents": [ "657472e9ccd9fccb82b775eb691c4b25b27451da" ], "author": { "name": "Shaohua Li", "email": "shaohua.li@intel.com", "time": "Mon Feb 25 09:46:41 2008 +0800" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Sun Apr 20 21:47:03 2008 -0700" }, "message": "PCI: add PCI Express ASPM support\n\nPCI Express ASPM defines a protocol for PCI Express components in the D0\nstate to reduce Link power by placing their Links into a low power state\nand instructing the other end of the Link to do likewise. This\ncapability allows hardware-autonomous, dynamic Link power reduction\nbeyond what is achievable by software-only controlled power management.\nHowever, The device should be configured by software appropriately.\nEnabling ASPM will save power, but will introduce device latency.\n\nThis patch adds ASPM support in Linux. It introduces a global policy for\nASPM, a sysfs file /sys/module/pcie_aspm/parameters/policy can control\nit. The interface can be used as a boot option too. Currently we have\nbelow setting:\n -default, BIOS default setting\n -powersave, highest power saving mode, enable all available ASPM\nstate and clock power management\n -performance, highest performance, disable ASPM and clock power\nmanagement\nBy default, the \u0027default\u0027 policy is used currently.\n\nIn my test, power difference between powersave mode and performance mode\nis about 1.3w in a system with 3 PCIE links.\n\nNote: some devices might not work well with aspm, either because chipset\nissue or device issue. The patch provide API (pci_disable_link_state),\ndriver can disable ASPM for specific device.\n\nSigned-off-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n" }, { "commit": "cb3576fa34e36907e292f408cb6c258f4fd112ad", "tree": "39756b6a25ba477e0f58e3a4efd125d0953d4296", "parents": [ "21c6847406784fde73ad5ea47c2c3434714d58d1" ], "author": { "name": "Gary Hade", "email": "garyhade@us.ibm.com", "time": "Fri Feb 08 14:00:52 2008 -0800" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Sun Apr 20 21:47:03 2008 -0700" }, "message": "PCI: Include PCI domain in PCI bus names on x86/x86_64\n\nThe PCI bus names included in /proc/iomem and /proc/ioports are\nof the form \u0027PCI Bus #XX\u0027 where XX is the bus number. This patch\nchanges the naming to \u0027PCI Bus XXXX:YY\u0027 where XXXX is the domain\nnumber and YY is the bus number. For example, PCI bus 14 in\ndomain 0 will show as \u0027PCI Bus 0000:14\u0027 instead of \u0027PCI Bus #14\u0027.\nThis change makes the naming consistent with other architectures\nsuch as ia64 where multiple PCI domain support has been around\nlonger.\n\nSigned-off-by: Gary Hade \u003cgaryhade@us.ibm.com\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n" }, { "commit": "5ff580c10ec06fd296bd23d4570c1a95194094a0", "tree": "fc00b4a107824519ae452c264674e5b8c2768d8e", "parents": [ "c71c68a04ba7672b9373ef04173114c211bb9f88" ], "author": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Thu Feb 14 14:56:56 2008 -0800" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Sun Apr 20 21:47:02 2008 -0700" }, "message": "PCI: remove global list of PCI devices\n\nThis patch finally removes the global list of PCI devices. We are\nrelying entirely on the list held in the driver core now, and do not\nneed a separate \"shadow\" list as no one uses it.\n\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n" }, { "commit": "8a1bc9013a03d41a0e36ee413bb6f97281b30bd1", "tree": "83c01850e1779e37be1d9db0f87436b09b89f3fe", "parents": [ "70308923d317f2ad4973c30d90bb48ae38761317" ], "author": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Thu Feb 14 14:56:56 2008 -0800" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Sun Apr 20 21:47:00 2008 -0700" }, "message": "PCI: add is_added flag to struct pci_dev\n\nThis lets us check if the device is really added to the driver core or\nnot, which is what we need when walking some of the bus lists. The flag\nis there in anticipation of getting rid of the other PCI device list,\nwhich is what we used to check in this situation.\n\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n" }, { "commit": "70308923d317f2ad4973c30d90bb48ae38761317", "tree": "b49daa7440e68c952e88617b3a36577d5c85a87b", "parents": [ "1ba6ab11d8fbd8d29afec4e39236e1255ae0339a" ], "author": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Wed Feb 13 22:30:39 2008 -0800" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Sun Apr 20 21:46:59 2008 -0700" }, "message": "PCI: make no_pci_devices() use the pci_bus_type list\n\nno_pci_devices() should use the driver core list of PCI devices, not our\n\"separate\" one.\n\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n" }, { "commit": "39106dcf85285e78f3b290022122c76f851379b8", "tree": "7fe93aaf6a433920b1c31725f42db30799deaa55", "parents": [ "fb0f330e62d71f7c535251438068199af320cf73" ], "author": { "name": "Mike Travis", "email": "travis@sgi.com", "time": "Tue Apr 08 11:43:03 2008 -0700" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Sat Apr 19 19:44:59 2008 +0200" }, "message": "cpumask: use new cpus_scnprintf function\n\n * Cleaned up references to cpumask_scnprintf() and added new\n cpulist_scnprintf() interfaces where appropriate.\n\n * Fix some small bugs (or code efficiency improvments) for various uses\n of cpumask_scnprintf.\n\n * Clean up some checkpatch errors.\n\nSigned-off-by: Mike Travis \u003ctravis@sgi.com\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" } ], "next": "0ab2b57f8db8a1bcdf24089074f5d2856a3ffb42" }