)]}'
{
  "log": [
    {
      "commit": "90b54929b626c80056262d9d99b3f48522e404d0",
      "tree": "d5cb91ff7bd0ac9ffeab5f7bf68235e8b35d050c",
      "parents": [
        "a03fa955576af50df80bec9127b46ef57e0877c0"
      ],
      "author": {
        "name": "Ivan Kokshaysky",
        "email": "ink@jurassic.park.msu.ru",
        "time": "Tue Jun 07 04:07:02 2005 +0400"
      },
      "committer": {
        "name": "Greg Kroah-Hartman",
        "email": "gregkh@suse.de",
        "time": "Fri Jul 01 13:35:50 2005 -0700"
      },
      "message": "[PATCH] PCI: handle subtractive decode pci-pci bridge better\n\nWith the number of PCI bus resources increased to 8, we can\nhandle the subtractive decode PCI-PCI bridge like a normal\nbridge, taking into account standard PCI-PCI bridge windows\n(resources 0-2). This helps to avoid problems with peer-to-peer DMA\nbehind such bridges, poor performance for MMIO ranges outside bridge\nwindows and prefetchable vs. non-prefetchable memory issues.\n\nTo reflect the fact that such bridges do forward all addresses to\nthe secondary bus (transparency), remaining bus resources 3-7 are\nlinked to resources 0-4 of the primary bus. These resources will be\nused as fallback by resource management code if allocation from\nstandard bridge windows fails for some reason.\n\nSigned-off-by: Ivan Kokshaysky \u003cink@jurassic.park.msu.ru\u003e\nAcked-by: Dominik Brodowski \u003clinux@dominikbrodowski.net\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n"
    },
    {
      "commit": "26f674ae0e37190bf61c988e52911e4372fdb5f5",
      "tree": "625b05e5edd627a5cce0289e78057ca5ccf2290c",
      "parents": [
        "ef6689eff4b58273fed9e54293a3da983b321e9a"
      ],
      "author": {
        "name": "Greg Kroah-Hartman",
        "email": "gregkh@suse.de",
        "time": "Thu Jun 02 15:41:48 2005 -0700"
      },
      "committer": {
        "name": "Greg Kroah-Hartman",
        "email": "gregkh@suse.de",
        "time": "Fri Jul 01 13:35:49 2005 -0700"
      },
      "message": "[PATCH] PCI: Fix up PCI routing in parent bridge\n\nWhen the cardbus bridge is behind another bridge change the routing\nin the parent bridge for new cards.  This fixes Cardbus on various AMD64\nlaptops.\n\nSigned-off-by: Andi Kleen \u003cak@suse.de\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n"
    },
    {
      "commit": "6ef6f0e33c4645fc8d23201ad5a6a289b4303cbb",
      "tree": "ff7861a550b5eea24788ccc07ca0df5294f9067b",
      "parents": [
        "e4ea9bb7e9f177e03a917b1f1213de0315f819ee"
      ],
      "author": {
        "name": "Rajesh Shah",
        "email": "rajesh.shah@intel.com",
        "time": "Thu Apr 28 00:25:49 2005 -0700"
      },
      "committer": {
        "name": "Greg Kroah-Hartman",
        "email": "gregkh@suse.de",
        "time": "Mon Jun 27 21:52:40 2005 -0700"
      },
      "message": "[PATCH] acpi bridge hotadd: Link newly created pci child bus to its parent on creation\n\nWhen a pci child bus is created, add it to the parent\u0027s children list\nimmediately rather than waiting till pci_bus_add_devices().  For hot-plug\nbridges/devices, pci_bus_add_devices() may be called much later, after they\nhave been properly configured.  In the meantime, this allows us to use the\nnormal pci bus search functions for the hot-plug bridges/buses.\n\nSigned-off-by: Rajesh Shah \u003crajesh.shah@intel.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n"
    },
    {
      "commit": "e4ea9bb7e9f177e03a917b1f1213de0315f819ee",
      "tree": "482599b5f367e997dfe30590860091bb06219882",
      "parents": [
        "cc57450f5c044270d2cf1dd437c1850422262109"
      ],
      "author": {
        "name": "Rajesh Shah",
        "email": "rajesh.shah@intel.com",
        "time": "Thu Apr 28 00:25:48 2005 -0700"
      },
      "committer": {
        "name": "Greg Kroah-Hartman",
        "email": "gregkh@suse.de",
        "time": "Mon Jun 27 21:52:40 2005 -0700"
      },
      "message": "[PATCH] acpi bridge hotadd: Take the PCI lock when modifying pci bus or device lists\n\nWith root bridge and pci bridge hot-plug, new buses and devices can be added\nor removed at run time.  Protect the pci bus and device lists with the pci\nlock when doing so.\n\nSigned-off-by: Rajesh Shah \u003crajesh.shah@intel.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n"
    },
    {
      "commit": "cc57450f5c044270d2cf1dd437c1850422262109",
      "tree": "418c7546c443cfc80601da045731f6b5a9f23442",
      "parents": [
        "71c3511c22e8e0648094672abec898b3bf84c18b"
      ],
      "author": {
        "name": "Rajesh Shah",
        "email": "rajesh.shah@intel.com",
        "time": "Thu Apr 28 00:25:47 2005 -0700"
      },
      "committer": {
        "name": "Greg Kroah-Hartman",
        "email": "gregkh@suse.de",
        "time": "Mon Jun 27 21:52:40 2005 -0700"
      },
      "message": "[PATCH] acpi bridge hotadd: Prevent duplicate bus numbers when scanning PCI bridge\n\nWhen hot-plugging a root bridge, as we try to assign bus numbers we may find\nthat the hotplugged hieratchy has more PCI to PCI bridges (i.e.  bus\nrequirements) than available.  Make sure we don\u0027t step over an existing bus\nwhen that happens.\n\nSigned-off-by: Rajesh Shah \u003crajesh.shah@intel.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n"
    },
    {
      "commit": "c431ada45d65b305a6aab4557067e564b23ce5a5",
      "tree": "3fefb8a354860d9c39781dbbf042c992da5a9cd5",
      "parents": [
        "efe1ec27837d6639eae82e1f5876910ba6433c3f"
      ],
      "author": {
        "name": "Rajesh Shah",
        "email": "rajesh.shah@intel.com",
        "time": "Thu Apr 28 00:25:45 2005 -0700"
      },
      "committer": {
        "name": "Greg Kroah-Hartman",
        "email": "gregkh@suse.de",
        "time": "Mon Jun 27 21:52:39 2005 -0700"
      },
      "message": "[PATCH] acpi bridge hotadd: ACPI based root bridge hot-add\n\nWhen you hot-plug a (root) bridge hierarchy, it may have p2p bridges and\ndevices attached to it that have not been configured by firmware.  In this\ncase, we need to configure the devices before starting them.  This patch\nseparates device start from device scan so that we can introduce the\nconfiguration step in the middle.\n\nI kept the existing semantics for pci_scan_bus() since there are a huge number\nof callers to that function.\n\nAlso, I have no way of testing the changes I made to the parisc files, so this\nneeds review by those folks.  Sorry for the massive cross-post, this touches\nfiles in many different places.\n\nSigned-off-by: Rajesh Shah \u003crajesh.shah@intel.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n"
    },
    {
      "commit": "f797f9cc5485b50c35c106b462e1bc432ec37f90",
      "tree": "283443fcdeb709c768ed5cd481203459b5222441",
      "parents": [
        "a3c77c67a443e631febf708bb0c376caede31657"
      ],
      "author": {
        "name": "Olof Johansson",
        "email": "olof@lixom.net",
        "time": "Mon Jun 13 15:52:27 2005 -0700"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@ppc970.osdl.org",
        "time": "Mon Jun 13 20:58:58 2005 -0700"
      },
      "message": "[PATCH] Fix PCI BAR size interpretation on 64-bit arches\n\nOn 64-bit machines, PCI_BASE_ADDRESS_MEM_MASK and other mask constants\npassed to pci_size() are 64-bit (for example ~0x0fUL).  However, pci_size\ndoes comparisons between the u32 arguments and the mask, which will fail\neven though any result from pci_size is still just 32-bit.\n\nChanging the mask argument to u32 seems the obvious thing to do, since all\narithmetic in the function is 32-bit and having a larger mask makes no\nsense.\n\nThis triggered on a PPC64 system here where an adapter (VGA, as it\nhappened) had a memory region base of 0xfe000000 and a sz of the same,\nmatching the if (max \u003d\u003d maxbase ...) test at the bottom of pci_size but\nfailing the mask comparison.  Quite a corner case which I guess explains\nwhy we haven\u0027t seen it until now.\n\nSigned-off-by: Olof Johansson \u003colof@lixom.net\u003e\nAcked-by: Greg KH \u003cgreg@kroah.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n"
    },
    {
      "commit": "bc56b9e01190b9f1ad6b7c5c694b61bfe34c7aa5",
      "tree": "9979aed502d987538c51d9820be9c288462f9996",
      "parents": [
        "92df516e6264f9caff4be49718926d6884fa50ed"
      ],
      "author": {
        "name": "Greg KH",
        "email": "gregkh@suse.de",
        "time": "Fri Apr 08 14:53:31 2005 +0900"
      },
      "committer": {
        "name": "Greg KH",
        "email": "gregkh@suse.de",
        "time": "Tue May 03 23:45:14 2005 -0700"
      },
      "message": "[PATCH] PCI: Clean up a lot of sparse \"Should it be static?\" warnings.\n\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n"
    },
    {
      "commit": "1da177e4c3f41524e886b7f1b8a0c1fc7321cac2",
      "tree": "0bba044c4ce775e45a88a51686b5d9f90697ea9d",
      "parents": [],
      "author": {
        "name": "Linus Torvalds",
        "email": "torvalds@ppc970.osdl.org",
        "time": "Sat Apr 16 15:20:36 2005 -0700"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@ppc970.osdl.org",
        "time": "Sat Apr 16 15:20:36 2005 -0700"
      },
      "message": "Linux-2.6.12-rc2\n\nInitial git repository build. I\u0027m not bothering with the full history,\neven though we have it. We can create a separate \"historical\" git\narchive of that later if we want to, and in the meantime it\u0027s about\n3.2GB when imported into git - space that would just make the early\ngit days unnecessarily complicated, when we don\u0027t have a lot of good\ninfrastructure for it.\n\nLet it rip!\n"
    }
  ]
}