)]}' { "log": [ { "commit": "298cf9beb9679522de995e249eccbd82f7c51999", "tree": "cabbc9c696a063982aea9a24d8caa667daa33a1a", "parents": [ "18ee49ddb0d242ed1d0e273038d5e4f6de7379d3" ], "author": { "name": "Lennert Buytenhek", "email": "buytenh@marvell.com", "time": "Wed Oct 08 16:29:57 2008 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Wed Oct 08 16:29:57 2008 -0700" }, "message": "phylib: move to dynamic allocation of struct mii_bus\n\nThis patch introduces mdiobus_alloc() and mdiobus_free(), and\nmakes all mdio bus drivers use these functions to allocate their\nstruct mii_bus\u0027es dynamically.\n\nSigned-off-by: Lennert Buytenhek \u003cbuytenh@marvell.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\nAcked-by: Andy Fleming \u003cafleming@freescale.com\u003e\n" }, { "commit": "90079ce89aa65e17f36ac2b09110720c51d874f4", "tree": "3ea630f89d77fb404cebe235d0a83516dae087f5", "parents": [ "a40c24a13366e324bc0ff8c3bb107db89312c984" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Thu Sep 11 04:52:51 2008 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Thu Sep 11 04:52:51 2008 -0700" }, "message": "tg3: Use SKB DMA helper functions for TX.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "4ba526ced990f4d61ee8d65fe8a6f0745e8e455c", "tree": "8b20fe7ea098ff1f6d04282adc82b779e403e02b", "parents": [ "bc7959b2cbb57393b625b423c73e6fd07610257f" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Fri Aug 15 14:10:04 2008 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Fri Aug 15 14:10:04 2008 -0700" }, "message": "tg3: Fix firmware event timeouts\n\nThe git commit 7c5026aa9b81dd45df8d3f4e0be73e485976a8b6 (\"tg3: Add\nlink state reporting to UMP firmware\") introduced code that waits for\nprevious firmware events to be serviced before attempting to submit a\nnew event. Unfortunately that patch contained a bug that cause the\ndriver to wait 2.5 seconds, rather than 2.5 milliseconds as intended.\nThis patch fixes that bug.\n\nThis bug revealed that not all firmware versions service driver events\nthough. Since we do not know which versions of the firmware do and don\u0027t\nservice these events, the driver needs some way to minimize the effects\nof the delay. This patch solves the problem by recording a jiffies\ntimestamp when it submits an event to the hardware. If the jiffies\ncounter shows that 2.5 milliseconds have already passed, a wait is not\nneeded and the driver can proceed to submit a new event.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "3bda12589646caa22b2ed4ef7cf82d17ea59d7a6", "tree": "abe2d161b442821ac245a61833e24b61fae954b1", "parents": [ "731fd79c133dc04cabee17ecfa7661189a8df5c8" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Fri Aug 15 14:08:22 2008 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Fri Aug 15 14:08:22 2008 -0700" }, "message": "tg3: Preserve register settings for DASH\n\nBroadcom\u0027s DASH (Desktop and mobile Architecture for System Hardware)\nimplementation requires that the driver preserve particular register\nsettings. If the driver does not preserve them, communication with\nthe DASH firmware will be lost.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "77b483f132ba25edf4ef455dd87a91ab7bbf4170", "tree": "8cb8f8444de1228cafed26784923e1045aba64c7", "parents": [ "c6153b5b77650879d78dec76414213c76dd8d574" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Fri Aug 15 14:07:24 2008 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Fri Aug 15 14:07:24 2008 -0700" }, "message": "tg3: Add APE register access locking\n\nIf the driver resets the chip while the APE is performing a register\naccess, that register access will never complete and the APE will hang\nindefinitely. To prevent this race condition, the driver must acquire\nan APE mutex before resetting the chip. The APE will not attempt a\nregister access until it acquires this lock.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "a9daf36746b1fb5c2db8d164ca70c30c63a0d7b2", "tree": "766a1f2ce9925b1d409a8d55fa26a953c2f3da31", "parents": [ "57e6983cbde91b4569b4014b933f3a16e12b99fd" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Sun May 25 23:49:44 2008 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Thu May 29 01:38:46 2008 -0700" }, "message": "tg3: Add shmem options.\n\nThis patch adds some options obtained through shared memory.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: Benjamin Li \u003cbenli@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "57e6983cbde91b4569b4014b933f3a16e12b99fd", "tree": "d5f06b5b0afcb465ebf60ee3c6b84413f4ded4ad", "parents": [ "b02fd9e3ac118037549baeb86fbe0718561db17f" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Sun May 25 23:48:31 2008 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Thu May 29 01:38:33 2008 -0700" }, "message": "tg3: Add 5785 ASIC revision\n\nThis patch added the 5785 device ID and ASIC revision to the code.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: Benjamin Li \u003cbenli@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "b02fd9e3ac118037549baeb86fbe0718561db17f", "tree": "858f7c763fe0e88a4a9f261eb7ae284413b310db", "parents": [ "158d7abdae85e9ac43d99780c372d79c119f7626" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Sun May 25 23:47:41 2008 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Thu May 29 01:38:24 2008 -0700" }, "message": "tg3: Add libphy support.\n\nThis patch introduces the libphy support.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: Benjamin Li \u003cbenli@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "158d7abdae85e9ac43d99780c372d79c119f7626", "tree": "8cca893ab0ab854217249ddeea49b1280ee0361a", "parents": [ "dd47700310ff929b439223105364c9ee3db81511" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Thu May 29 01:37:54 2008 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Thu May 29 01:37:54 2008 -0700" }, "message": "tg3: Add mdio bus registration\n\nThis patch introduces code to register and unregister the tg3 mdio bus\nwith the system.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: Benjamin Li \u003cbenli@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "dd47700310ff929b439223105364c9ee3db81511", "tree": "fd7bc416e9cb9ee5f93d9668d8ccaaaa35293b59", "parents": [ "f51f3562d1c7df6c5a4ffee2185d713e98e76aa0" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Sun May 25 23:45:58 2008 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Thu May 29 01:36:32 2008 -0700" }, "message": "tg3: Add TG3_FLG3_USE_PHYLIB\n\nThis patch introduces the TG3_FLG3_USE_PHYLIB flag and applies it to\nsome select places. This work makes later patches a little easier to\nread.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: Benjamin Li \u003cbenli@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "f51f3562d1c7df6c5a4ffee2185d713e98e76aa0", "tree": "3b50309595f33cfefafbf50b90d2d1ef6226c097", "parents": [ "95e2869adc13041baf3beecb97ab8e38c01525ae" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Sun May 25 23:45:08 2008 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Thu May 29 01:36:14 2008 -0700" }, "message": "tg3: Code cleanup.\n\nThis patch applies cleanups that would otherwise clutter later\npatches.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: Benjamin Li \u003cbenli@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "7c5026aa9b81dd45df8d3f4e0be73e485976a8b6", "tree": "09b0e14566d630f1b8d3225b6fda0c2a862519e9", "parents": [ "109115e1991824b88306b374b763d6857b292aeb" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Fri May 02 16:49:29 2008 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Fri May 02 16:49:29 2008 -0700" }, "message": "tg3: Add link state reporting to UMP firmware\n\nAll variants of the 5714, 5715, and 5780 offer a feature called the\n\"Universal Management Port\". This feature is implemented in firmware\nand is largely transparent to the driver, except...\n\nIt turns out that the UMP firmware needs to know the current status\nof the link. Because the firmware cannot touch the PHY registers while\nthe driver is in control of the device, it needs the driver to report\nlink status changes through an additional handshaking mechanism.\nWithout this handshake, it has been observed in the field that the UMP\nfirmware will not operate correctly.\n\nThis patch implements the new handshake with the UMP firmware. Since\nthe handshake uses the same mechanism ASF heartbeats use, code was\nadded to detect and wait for completion of a pending previous event.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "fd1122a2593d0bbe19856e3943c859ebfe563583", "tree": "75be50b8a959ef7f772612643d5d60104e9ccceb", "parents": [ "8ef214288622bf523a3b3096958292a1c63132ad" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Fri May 02 16:48:36 2008 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Fri May 02 16:48:36 2008 -0700" }, "message": "tg3: Fix 5761 NVRAM sizes\n\nThe 5761 NVRAM sizes assigned to the nvram_size member are half as big\nas they should be. This patch corrects the NVRAM sizes and replaces\nthe hardcoded constants with preprocessor constants for readability.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "8ef214288622bf523a3b3096958292a1c63132ad", "tree": "a9c1139ca15d642ec14a423d1ea163be81fbbce9", "parents": [ "026672d0997c911c9bef9aabe862884fc0add106" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Fri May 02 16:47:53 2008 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Fri May 02 16:47:53 2008 -0700" }, "message": "tg3: Use constant 500KHz MI clock on adapters with a CPMU\n\nThe MI clock is not configured correctly on adapters with the CPMU\npresent. The tg3 driver has code which statically sets the MI clock to\nbe a fraction of the speed at which the core clock is running.\nHowever, the CPMU can change the adapter\u0027s core clock frequency based\non operating conditions. Consequently, the MI will run slow when the\ncore\u0027s clock has been slowed down.\n\nThere is a new 500KHz constant frequency clock available on adapters\nwith a CPMU. This patch removes the static core clock scaling and\nconfigures the MI clock to use this new 500KHz clock instead.\n\nRunning the MI clock at slower speeds will not directly result in data\ncorruption, but it does challenge the PHY read and write routine timeouts.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "41588ba1ae166eaba0a70abf2d7ff064ad9331d3", "tree": "4ec3ef51db69aa0f9b6446435580115aa68098f7", "parents": [ "36ef408061da9e012375547d69b27cc1f537b044" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Sat Apr 19 18:12:33 2008 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sat Apr 19 18:12:33 2008 -0700" }, "message": "tg3: 5701 DMA corruption fix\n\nHerbert Xu\u0027s commit fb93134dfc2a6e6fbedc7c270a31da03fce88db9, entitled\n\"[TCP]: Fix size calculation in sk_stream_alloc_pskb\", has triggered a\nbug in the 5701 where the 5701 DMA engine will corrupt outgoing\npackets. This problem only happens when the starting address of the\npacket matches a certain range of offsets and only when the 5701 is\nplaced downstream of a particular Intel bridge.\n\nThis patch detects the problematic bridge and if present, readjusts the\nstarting address of the packet data to a dword aligned boundary.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "b2a5c19ca0315723cecb9489ff8b67c4f17367b4", "tree": "e218cd12701ef2a180e283b99697a277ab0f70c0", "parents": [ "61407f80f72970d52d4339f81c6c3cd03f4ca0f0" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Thu Apr 03 21:44:44 2008 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Thu Apr 03 21:44:44 2008 -0700" }, "message": "[TG3]: Add PHY workaround for 5784\n\nThe 5784 B step and newer chips require the PHY DSPs to be fine-tuned\nbased on one-time programmable values stored in the chip. This is\nessential to achieve optimal PHY operations especially when using\nlong cables. We also need to properly handle the 10Mbit RX bit in the\nCPMU_CTRL register during PHY reset.\n\nUpdate version to 3.89.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "c98f6e3be1d1b9bc9299d84da4f0b1ea9a50f392", "tree": "6b40c900dad3d38e755f1a5a37acea08f98d3b0d", "parents": [ "ba4d07a8483e6ec0de3194960f8aca862711454c" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Thu Dec 20 20:08:32 2007 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Mon Jan 28 14:59:32 2008 -0800" }, "message": "[TG3]: Replace some magic 5704S constants\n\nThis patch replaces magic values with preprocessor definitions for\nthe sg_dig_ctrl and sg_dig_status registers. This is preparatory work\nfor the next patch.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "8d018621085b8d00511768c343d941676bd77ee9", "tree": "0649c902e48609a0af8391bcb99cc7ff5080ff97", "parents": [ "a43d8994b959a6daeeadcd1be6d4a9045b7029ac" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Thu Dec 20 20:05:44 2007 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Mon Jan 28 14:59:29 2008 -0800" }, "message": "[TG3]: Separate requested and actual flow control parameters\n\nThis patch removes the TX and RX flow control flags from tg3_flags and\nadds two new flow control variables, flowctrl and active_flowctrl.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "b5af7126ea7586eb8f030280c027611c42a6a9c7", "tree": "f84c51317a8471bfbc1cbc6fba8307f27704b72f", "parents": [ "5f5c51e3d473d8ddc0c32156c2b27e2fe92b9b57" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Mon Nov 12 21:22:02 2007 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Mon Nov 12 21:22:02 2007 -0800" }, "message": "[TG3]: Add A1 revs\n\nThis patch adds the A1 revision of 5784, 5764, and 5761, and applies all\nprevious bugfixes. In places where the list of devices gets too long,\nthe patch uses a new TG3_FLG3_5761_5784_AX_FIXES flag instead.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "aa6c91fe5913faa2cd2a62de993a3130799412b1", "tree": "e3b320593d68b4542beedf496b365378519fb2d2", "parents": [ "5f60891b80f1a0f0a0015b084f4838ae8b9637c7" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Mon Nov 12 21:18:04 2007 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Mon Nov 12 21:18:04 2007 -0800" }, "message": "[TG3]: Prescaler fix\n\nInternal hardware timers become inaccurate after link events. Clock\nfrequency switches performed by the CPMU fail to adjust timer\nprescalers. The fix is to detect core clock frequency changes during\nlink events and adjust the timer prescalers accordingly.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "662f38d242488cfdcda7b3684ac610d3e4d568a7", "tree": "e4557b5d2ec89f5d9b858e29ca40215eade01cef", "parents": [ "e875093c9659d2a9f3923aa9ee1b89ef40cf95b9" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Mon Nov 12 21:16:17 2007 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Mon Nov 12 21:16:17 2007 -0800" }, "message": "[TG3]: Disable GPHY autopowerdown\n\nNew CPMU devices contend with the GPHY for power management. The GPHY\nautopowerdown feature is enabled by default in the PHY and thus needs to\nbe disabled after every PHY reset.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "a5767dec1980463aef5614b7ad8a800bb4f4c353", "tree": "be204ff73acbaf61f0f95e4530fdc0ff615943c6", "parents": [ "9acb961e7d780291659bf950b3b718ff9e085620" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Mon Nov 12 21:10:58 2007 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Mon Nov 12 21:10:58 2007 -0800" }, "message": "[TG3]: Fix nvram selftest failures\n\nNewer devices contain bootcode in the chip\u0027s private ROM area. This\nbootcode is called selfboot. Selfboot can be patched in the device\u0027s\nNVRAM and the patches can have several formats. In one particular\nformat, the checksum calculation needs to be slightly modified. This\npatch adjusts the NVRAM test code for that case, and add support for the\nmissing formats.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "9acb961e7d780291659bf950b3b718ff9e085620", "tree": "4d85bccc795eae5ba9d4061de8a73cb443e708c8", "parents": [ "84af67fdf07c4fce664dbca87a8d5e2802901bff" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Mon Nov 12 21:10:06 2007 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Mon Nov 12 21:10:06 2007 -0800" }, "message": "[TG3]: 5784 / 5764 DMA engine lockup fix\n\n5784 and 5764 devices lock up when the link speed is 10Mbps, the CPMU\nlink speed mode is enabled, and the MAC clock is running at 1.5Mhz. The\nfix is to run the MAC clock at faster speeds.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "ce057f01956bfcb3cb8588091000ae546be78e00", "tree": "6438c33bcdde387ab191912e970b2fb65696b0a0", "parents": [ "c88864df27590b80fca4a991e0c257d1757cec41" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Mon Nov 12 21:08:03 2007 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Mon Nov 12 21:08:03 2007 -0800" }, "message": "[TG3]: 5784 / 5764 GPHY power down fix\n\n5784 and 5764 devices fail to link / pass traffic after one load /\nunload cycle. This happens because of a hardware bug in the new CPMU.\nDuring normal operation, the MAC depends on the PHY clock being\navailable. When the PHY is powered down, the clock the MAC depends on\nis disabled. The fix is to switch the MAC clock to an alternate source\nbefore powering down the PHY, and to restore the MAC clock to the PHY\nsource upon device resume.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "8a6eac90e21633e054e17d21454a2c26824aeb18", "tree": "0d9bce8b6c5f359d6532f854467c71eb83356d90", "parents": [ "9c8a620e7f85fff050a54697da44bbd1a66e8e0b" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Sun Oct 21 16:17:55 2007 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Oct 22 02:59:51 2007 -0700" }, "message": "[TG3]: PCI command adjustment\n\nThis patch changes the way the driver works with the PCI command\nregister. It adjusts the access size from dwords to words. This patch\nis done both as a PCI configuration space cleanup and as preparatory\nwork for PCI error recovery.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "9c8a620e7f85fff050a54697da44bbd1a66e8e0b", "tree": "340bf6ddc4f38fcb2aea3bad90b3fd4a6cd13ba8", "parents": [ "6c7af27c8a2e8b85cb235a2409d3b2093b18f77d" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Sun Oct 21 16:16:08 2007 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Oct 22 02:59:50 2007 -0700" }, "message": "[TG3]: Add management FW version to ethtool report\n\nThis patch appends the management firmware version to the bootcode\nfirmware string reported through ethtool.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "0527ba358aa7594731e627842d493ae7f009dd57", "tree": "bb81d22c87aabc3e511b7a0ad6841ace4fda3476", "parents": [ "9936bcf68a7e4d33f080bba9ee03d156c75c91ee" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Wed Oct 10 18:03:30 2007 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Wed Oct 10 18:03:30 2007 -0700" }, "message": "[TG3]: WOL defaults\n\nThis patch enables WOL by default if out-of-box WOL is enabled in the\nNVRAM.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "9936bcf68a7e4d33f080bba9ee03d156c75c91ee", "tree": "304371f919a53ee6be7c7bf0b672078ab123eb71", "parents": [ "0d3031d9e674cddd4c09731123ad252294cdf15f" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Wed Oct 10 18:03:07 2007 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Wed Oct 10 18:03:07 2007 -0700" }, "message": "[TG3]: Add 5761 support\n\nThis patch adds rest of the miscellaneous code required to support the\n5761.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "0d3031d9e674cddd4c09731123ad252294cdf15f", "tree": "fdcfc596ef8c5a996808cf1e701883c6383a7e3f", "parents": [ "6b91fa02796292c322b20572188c74c1ef5bb02b" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Wed Oct 10 18:02:43 2007 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Wed Oct 10 18:02:43 2007 -0700" }, "message": "[TG3]: Add 5761 APE support\n\nThis patch adds support for the new APE block, present in 5761 chips.\nAPE stands for Application Processing Engine. The primary function of\nthe APE is to process manageability traffic, such as ASF.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "6b91fa02796292c322b20572188c74c1ef5bb02b", "tree": "dee1577ca9507e256302dc6b33dfb057fb267481", "parents": [ "227b60f5102cda4e4ab792b526a59c8cb20cd9f8" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Wed Oct 10 18:01:09 2007 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Wed Oct 10 18:01:09 2007 -0700" }, "message": "[TG3]: Add new 5761 NVRAM decode routines\n\nThis patch adds a new 5761-specific NVRAM strapping decode routine.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n\n" }, { "commit": "d30cdd28fba556143a4bb0d1a6097ebcc2891477", "tree": "00a6548cbd6cdf13a88427c66c520456444c3a6b", "parents": [ "795d01c523dd9f22acc70fe86ed30e605e00024d" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Sun Oct 07 23:28:35 2007 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Oct 10 16:54:45 2007 -0700" }, "message": "[TG3]: Add 5784 and 5764 support.\n\nThis patch adds the support for 5784 and 5764 devices.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "795d01c523dd9f22acc70fe86ed30e605e00024d", "tree": "2ef37449a25c1ab68537fe4c2ddce4bb9fe8805a", "parents": [ "9974a356b204833b32173210ca25edfdc24dcdd5" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Sun Oct 07 23:28:17 2007 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Oct 10 16:54:45 2007 -0700" }, "message": "[TG3]: ASIC decoding and basic CPMU support.\n\nNewer products change the way the ASIC revision is obtained. This patch\nimplements how the driver will extract the revision number.\n\nThis patch also adds preliminary CPMU support. CPMU stands for Central\nPower Management Unit. The CPMU\u0027s role is to put the chip into lower\npower states when the operating conditions allow it.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "9974a356b204833b32173210ca25edfdc24dcdd5", "tree": "1b6a4d69ec46c01934fb5ff2cf4d76d57a103752", "parents": [ "8658251dc3fed54b09991a2c5e0a7084755157d7" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Sun Oct 07 23:27:28 2007 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Oct 10 16:54:44 2007 -0700" }, "message": "[TG3]: Walk PCI capability lists.\n\nNewer tg3 devices shuffle around the registers in PCI configuration\nspace. This patch changes the way the driver accesses the PCI\ncapabilities registers. Hardcoded register locations are replaced with\noffsets from pci_find_capability() return values.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "bea3348eef27e6044b6161fd04c3152215f96411", "tree": "f0990b263e5ce42505d290a4c346fe990bcd4c33", "parents": [ "dde4e47e8fe333a5649a3fa0e7db1fa7c08d6158" ], "author": { "name": "Stephen Hemminger", "email": "shemminger@linux-foundation.org", "time": "Wed Oct 03 16:41:36 2007 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Oct 10 16:47:45 2007 -0700" }, "message": "[NET]: Make NAPI polling independent of struct net_device objects.\n\nSeveral devices have multiple independant RX queues per net\ndevice, and some have a single interrupt doorbell for several\nqueues.\n\nIn either case, it\u0027s easier to support layouts like that if the\nstructure representing the poll is independant from the net\ndevice itself.\n\nThe signature of the -\u003epoll() call back goes from:\n\n\tint foo_poll(struct net_device *dev, int *budget)\n\nto\n\n\tint foo_poll(struct napi_struct *napi, int budget)\n\nThe caller is returned the number of RX packets processed (or\nthe number of \"NAPI credits\" consumed if you want to get\nabstract). The callee no longer messes around bumping\ndev-\u003equota, *budget, etc. because that is all handled in the\ncaller upon return.\n\nThe napi_struct is to be embedded in the device driver private data\nstructures.\n\nFurthermore, it is the driver\u0027s responsibility to disable all NAPI\ninstances in it\u0027s -\u003estop() device close handler. Since the\nnapi_struct is privatized into the driver\u0027s private data structures,\nonly the driver knows how to get at all of the napi_struct instances\nit may have per-device.\n\nWith lots of help and suggestions from Rusty Russell, Roland Dreier,\nMichael Chan, Jeff Garzik, and Jamal Hadi Salim.\n\nBug fixes from Thomas Graf, Roland Dreier, Peter Zijlstra,\nJoseph Fannin, Scott Wood, Hans J. Koch, and Michael Chan.\n\n[ Ported to current tree and all drivers converted. Integrated\n Stephen\u0027s follow-on kerneldoc additions, and restored poll_list\n handling to the old style to fix mutual exclusion issues. -DaveM ]\n\nSigned-off-by: Stephen Hemminger \u003cshemminger@linux-foundation.org\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "ee6a99b539a50b4e9398938a0a6d37f8bf911550", "tree": "51547e0b9c299be15cc3f54ff3c33b6e3e9c346c", "parents": [ "7dc12d6dd6cc1aa489c6f3e34a75e8023c945da8" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Wed Jul 18 21:49:10 2007 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Wed Jul 18 21:49:10 2007 -0700" }, "message": "[TG3]: Fix msi issue with kexec/kdump.\n\nTina Yang \u003ctina.yang@oracle.com\u003e discovered an MSI related problem\nwhen doing kdump. The problem is that the kexec kernel is booted\nwithout going through system reset, and as a result, MSI may already\nbe enabled when tg3_init_one() is called. tg3_init_one() calls\npci_save_state() which will save the stale MSI state. Later on in\ntg3_open(), we call pci_enable_msi() to reconfigure MSI on the chip\nbefore we reset the chip. After chip reset, we call\npci_restore_state() which will put the stale MSI address/data back\nonto the chip.\n\nThis is no longer a problem in the latest kernel because\npci_restore_state() has been changed to restore MSI state from\ninternal data structures which will guarantee restoring the proper\nMSI state.\n\nBut I think we should still fix it. Our save and restore sequence\ncan still cause very subtle problems down the road. The fix is to\nhave our own functions save and restore precisely what we need. We\nalso change it to save and restore state inside tg3_chip_reset() in a\nmore straight forward way.\n\nThanks to Tina for helping to test and debug the problem.\n\n[ Bump driver version and release date. -DaveM ]\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "70b65a2d628d2e66bbf044bb764be64949f3580c", "tree": "15f39fbf9e6b216bf8d4e1f961a54deb5203ac29", "parents": [ "9ef8ca99749784644602535691f8cf201ee2a225" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Wed Jul 11 19:48:50 2007 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Wed Jul 11 19:48:50 2007 -0700" }, "message": "[TG3]: Add missing NVRAM strapping.\n\nThis patch adds a missing NVRAM strapping for 5755 devices.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "9ef8ca99749784644602535691f8cf201ee2a225", "tree": "7836b055d04f88203b8cf563272696d6fe972e95", "parents": [ "e8f3f6cad7e423253090887bc4afe7bc844162da" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Wed Jul 11 19:48:29 2007 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Wed Jul 11 19:48:29 2007 -0700" }, "message": "[TG3]: Enable auto MDI.\n\nThis patch adds automatic MDI crossover support when autonegotiation is\nturned off. Automatic MDI crossover allows link to be established\nwithout the use of a crossover cable.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "2b3cb2e778811a1df99e37fd7c359837501ab103", "tree": "736b6e149fababf75b1bd0d94a316b790e7f59ae", "parents": [ "19a75d83ffeab004cfcfac64024ad3997bac7220" ], "author": { "name": "Andrew Morton", "email": "akpm@osdl.org", "time": "Wed May 09 02:33:57 2007 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Wed May 09 12:30:51 2007 -0700" }, "message": "tg3: use flush_work_keventd()\n\nConvert tg3 over to flush_work_keventd(). Remove nasty now-unneeded deadlock\navoidance logic.\n\n(akpm: bypassed maintainers, sorry. There are other patches which depend on\nthis)\n\nCc: \"Maciej W. Rozycki\" \u003cmacro@linux-mips.org\u003e\nCc: David Howells \u003cdhowells@redhat.com\u003e\nCc: \"David S. Miller\" \u003cdavem@davemloft.net\u003e\nCc: Michael Chan \u003cmchan@broadcom.com\u003e\nCc: Jeff Garzik \u003cjeff@garzik.org\u003e\nCc: Oleg Nesterov \u003coleg@tv-sign.ru\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "8ed5d97e5e0be0fb1aebad16f4c464613a0e472d", "tree": "4088096e3fbc02e671980db1a2f26e1068dec532", "parents": [ "15700770ef7c5d12e2f1659d2ddbeb3f658d9f37" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Mon May 07 00:25:49 2007 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Mon May 07 00:25:49 2007 -0700" }, "message": "[TG3]: Add ASPM workaround.\n\nThis patch adds workaround to fix performance problems caused by slow\nPCIE L1-\u003eL0 transitions on ICH8 platforms.\n\nChanged all magic numbers to constants as suggested by Jeff Garzik.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "7544b0972c1fc1a0e6c54baa1f44c81019743daa", "tree": "90c8ca52ab4bb01b83c51f2c6ea91b1a6854a1a1", "parents": [ "98efd8a6be79550767f5a9be6f3db8e7e9b747da" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Sat May 05 13:08:32 2007 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sat May 05 13:08:32 2007 -0700" }, "message": "[TG3]: Add TG3_FLAG_SUPPORT_MSI flag.\n\nAnd fix up the code to always allow MSI on 5714 A2.\n\nCall tg3_find_peer() earlier because we need that information before\nwe can determine whether we can set TG3_FLAG_SUPPORT_MSI or not.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "98efd8a6be79550767f5a9be6f3db8e7e9b747da", "tree": "c2117eb3b6099333594245d81a8d192912f18706", "parents": [ "5cf64b8a7399999439f0d6748babb1ccb6bcad7c" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Sat May 05 12:47:25 2007 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sat May 05 12:47:25 2007 -0700" }, "message": "[TG3]: Eliminate the TG3_FLAG_5701_REG_WRITE_BUG flag.\n\nThis patch removes the use of the TG3_FLAG_5701_REG_WRITE_BUG flag.\nIt\u0027s logic is only used to set a function pointer and thus the\nlogic can be collapsed and the flag removed.\n\n[ Comment tidy by Christoph Hellwig. -DaveM ]\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\n" }, { "commit": "5cf64b8a7399999439f0d6748babb1ccb6bcad7c", "tree": "6357ac40ddf95f171ed8c5f9bdae2ad8755981f1", "parents": [ "986e0aeb9ae09127b401c3baa66f15b7a31f354c" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Sat May 05 12:11:21 2007 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sat May 05 12:11:21 2007 -0700" }, "message": "[TG3]: Eliminate the TG3_FLAG_GOT_SERDES_FLOWCTL flag.\n\nThis flag does not do anything useful.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "a85feb8cfc53c08b6f0d770f930ca9cc6885f414", "tree": "f5806132fb6e60fd7c68a281680e5f05014d5933", "parents": [ "aaf84465fc994e9a840a8c0c6fa842b54cdb3426" ], "author": { "name": "Gary Zambrano", "email": "zambrano@broadcom.com", "time": "Sat May 05 11:52:19 2007 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sat May 05 11:52:19 2007 -0700" }, "message": "[TG3]: WoL fixes.\n\nChange TG3_FLAG_SERDES_WOL_CAP to TG3_FLAG_WOL_CAP to make it easier\nto manage WoL. This flag is now used consistently during ethtool WoL\nsetup and power setting changes.\n\nSigned-off-by: Gary Zambrano \u003czambrano@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "d18edcb212d7dc864a59e6aa9b6b9826299e0210", "tree": "341955faabd7db53af392f4bdbd856dcbe6f8d11", "parents": [ "1c46ae05d96f77f349ae60c799acb6ac6ddf07a8" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Sat Mar 24 20:57:11 2007 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sun Mar 25 18:48:08 2007 -0700" }, "message": "[TG3]: Exit irq handler during chip reset.\n\nOn most tg3 chips, the memory enable bit in the PCI command register\ngets cleared during chip reset and must be restored before accessing\nPCI registers using memory cycles. The chip does not generate\ninterrupt during chip reset, but the irq handler can still be called\nbecause of irq sharing or irqpoll. Reading a register in the irq\nhandler can cause a master abort in this scenario and may result in a\ncrash on some architectures.\n\nUse the TG3_FLAG_CHIP_RESETTING flag to tell the irq handler to exit\nwithout touching any registers. The checking of the flag is in the\n\"slow\" path of the irq handler and will not affect normal performance.\nThe msi handler is not shared and therefore does not require checking\nthe flag.\n\nThanks to Bernhard Walle \u003cbwalle@suse.de\u003e for reporting the problem.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "1c46ae05d96f77f349ae60c799acb6ac6ddf07a8", "tree": "74179101bea9c624cbb7cd96d3b366c21743614c", "parents": [ "f11e6659ce9058928d73ff440f9b40a818d628ab" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Sat Mar 24 20:54:37 2007 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sun Mar 25 18:48:06 2007 -0700" }, "message": "[TG3]: Eliminate the unused TG3_FLAG_SPLIT_MODE flag.\n\nThis flag to support multiple PCIX split completions was never used\nbecause of hardware bugs. This will make room for a new flag.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "7f62ad5d37f4e43c841e92c6f159c93dcf2d2cdd", "tree": "f8d0e5d2dcc5e7783ace1f966b9e008278357067", "parents": [ "ad930650c0e694233971c56e8de8e78b896e2613" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Tue Feb 20 23:25:40 2007 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Feb 26 11:42:47 2007 -0800" }, "message": "[TG3]: TSO workaround fixes.\n\n1. Add race condition check after netif_stop_queue(). tg3_tx() runs\n without netif_tx_lock and can race with tg3_start_xmit_dma_bug() -\u003e\n tg3_tso_bug().\n\n2. Firmware TSO in 5703/5704/5705 also have the same TSO limitation,\n i.e. they cannot handle TSO headers bigger than 80 bytes. Rename\n TG3_FL2_HW_TSO_1_BUG to TG3_FL2_TSO_BUG and set this flag on\n these chips as well.\n\n3. Update version to 3.74.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "569a5df8597deeaa39867be73c7305fd82522f57", "tree": "a49d58a45867f7255faf3c08d00830618b4d73c3", "parents": [ "5129724aa5de3a71fc70e71ca49d542ca1a5aa1e" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Tue Feb 13 12:18:15 2007 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Feb 13 12:18:15 2007 -0800" }, "message": "[TG3]: Use constant for PHY register 0x1e.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "c1d2a1965a00693bddaddf75d57488a0d8e891af", "tree": "5658caed34980b6edb302b3fc0103a5d61e7dbb4", "parents": [ "d6aa4acebafe3acb0aade7704ec5b2f03742ea14" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Mon Jan 08 19:57:20 2007 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Tue Jan 09 00:30:06 2007 -0800" }, "message": "[TG3]: Add PHY workaround for 5755M.\n\nSome PHY trim values need to be fine-tuned on 5755M to be\nIEEE-compliant.\n\nUpdate version to 3.72.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "60189ddff03ffce1f0442a7591b2abafdf47e6a3", "tree": "25d3c5c8211fd57942ae0a57d82c66ad4b2110c5", "parents": [ "c49a1561ee4b663d2819b5bea3e4684eae217b19" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Sun Dec 17 17:08:07 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sun Dec 17 21:59:22 2006 -0800" }, "message": "[TG3]: Power down/up 5906 PHY correctly.\n\nThe 5906 PHY requires a special register bit to power down and up the\nPHY.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "9d26e213423923c9e033ccd373705118131827c9", "tree": "182ec37041687479c2e4697463e77a1b195b9d26", "parents": [ "676917d488212303ce4a7d033815ce8799201010" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Thu Dec 07 00:21:14 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Thu Dec 07 00:21:14 2006 -0800" }, "message": "[TG3]: Add TG3_FLG2_IS_NIC flag.\n\nAdd Tg3_FLG2_IS_NIC flag to unambiguously determine whether the\ndevice is NIC or onboard. Previously, the EEPROM_WRITE_PROT flag was\noverloaded to also mean onboard. With the separation, we can\nsupport some devices that are onboard but do not use eeprom write\nprotect.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "b16250e3d1c55820f08f0296624a423122ea9805", "tree": "9559f4acd5e740b727c42e635699b7427f21d3c3", "parents": [ "715116a12610b67c1d301a9b845ce95f7247dad3" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Wed Sep 27 16:10:14 2006 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Sep 28 18:01:42 2006 -0700" }, "message": "[TG3]: Add 5709 self-test support.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "715116a12610b67c1d301a9b845ce95f7247dad3", "tree": "1f9b680e4cfc32cc7759b82481f104eae6e22f24", "parents": [ "b5d3772ccbe0bc5ac8ffbb5356b74ca698aee28c" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Wed Sep 27 16:09:25 2006 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Sep 28 18:01:41 2006 -0700" }, "message": "[TG3]: Add 5709 PHY support.\n\nAdd support for the 5709 10/100 PHY.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "b5d3772ccbe0bc5ac8ffbb5356b74ca698aee28c", "tree": "ef5f1e64d6e656a4931e22efed5809eb42d0e39f", "parents": [ "7a6f4369449a471a6e5718a87c53ac75a46960ba" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Wed Sep 27 16:06:21 2006 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Sep 28 18:01:40 2006 -0700" }, "message": "[TG3]: Add basic 5906 support.\n\nAdd support for the new 5709 device. This is a new 10/100 Mbps chip.\nThe mailbox access and firmware interface are quite different from\nall other tg3 chips.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "126a336822a6594662f5898f1ddf33e6d048fcc7", "tree": "b8bf224c080868d0f2e89c55eef1b23e2b6a2bc9", "parents": [ "3f7045c1f28bedd44389b9392b54c6fdb83ee5c6" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Wed Sep 27 16:03:07 2006 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Sep 28 18:01:38 2006 -0700" }, "message": "[TG3]: Add 5722 and 5756 support.\n\nAdd IDs to support 5722 and 5756.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "130b8e4d0e4edadcecee9fdff2c32f33d77c4fe9", "tree": "1c0f165309fa5a6b5d23fdad038ae932470d0cf9", "parents": [ "3d3ebe741b2c06fe3df67739d09f6ef0e25ee41a" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Wed Sep 27 16:00:40 2006 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Sep 28 18:01:35 2006 -0700" }, "message": "[TG3]: Improve ASF heartbeat.\n\nChange to a different ASF heartbeat message code to improve\nreliability.\n\nThere were some reports of unintended resets on real time kernels\nwhere the timer may be slow and cause the heartbeat to be late.\nNetpoll will also have the same problem because the timer irq will\nbe unavailable.\n\nUsing the new heartbeat code, the ASF firmware will also check the\nring condition before resetting the chip when the heartbeat is\nexpiring.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "3d3ebe741b2c06fe3df67739d09f6ef0e25ee41a", "tree": "f9112f5b5beac57673a26563a3a50517c5c96798", "parents": [ "6ac59344ef25d5f0ebadb5663cf700d25d2a3886" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Wed Sep 27 15:59:15 2006 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Sep 28 18:01:34 2006 -0700" }, "message": "[TG3]: Improve 5704S autoneg.\n\nImprove 5704S autoneg logic by using a serdes_counter field to keep\ntrack of the transient states. This eliminates a 200 msec busy\nloop in the code. Autoneg will take its course without the driver\nbusy waiting for it to finish.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "1b2a720506ccf7c30baaeda5d990c29b31e21726", "tree": "5990f56e364077c83563566ed64beae95b855a9f", "parents": [ "bd37a088596ccdb2b2dd3299e25e333bca7a9a34" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Mon Aug 07 21:46:02 2006 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Mon Aug 07 21:46:02 2006 -0700" }, "message": "[TG3]: Fix tx race condition\n\nFix a subtle race condition between tg3_start_xmit() and tg3_tx()\ndiscovered by Herbert Xu \u003cherbert@gondor.apana.org.au\u003e:\n\nCPU0\t\t\t\t\tCPU1\ntg3_start_xmit()\n\tif (tx_ring_full) {\n\t\ttx_lock\n\t\t\t\t\ttg3_tx()\n\t\t\t\t\t\tif (!netif_queue_stopped)\n\t\tnetif_stop_queue()\n\t\tif (!tx_ring_full)\n\t\t\t\t\t\tupdate_tx_ring \n\t\t\tnetif_wake_queue()\n\t\ttx_unlock\n\t}\n\nEven though tx_ring is updated before the if statement in tg3_tx() in\nprogram order, it can be re-ordered by the CPU as shown above. This\nscenario can cause the tx queue to be stopped forever if tg3_tx() has\njust freed up the entire tx_ring. The possibility of this happening\nshould be very rare though.\n\nThe following changes are made:\n\n1. Add memory barrier to fix the above race condition.\n\n2. Eliminate the private tx_lock altogether and rely solely on\nnetif_tx_lock. This eliminates one spinlock in tg3_start_xmit()\nwhen the ring is full.\n\n3. Because of 2, use netif_tx_lock in tg3_tx() before calling\nnetif_wake_queue().\n\n4. Change TX_BUFFS_AVAIL to an inline function with a memory barrier.\nHerbert and David suggested using the memory barrier instead of\nvolatile.\n\n5. Check for the full wake queue condition before getting\nnetif_tx_lock in tg3_tx(). This reduces the number of unnecessary\nspinlocks when the tx ring is full in a steady-state condition.\n\n6. Update version to 3.65.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nAcked-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "52c0fd834ea0e7c6ef8616ce0a1f85bac4233ed7", "tree": "92897bedf97906699f654fd94985fbada0497daa", "parents": [ "1661394e78b3b2cc868cd0e89c1066974302aaca" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Thu Jun 29 20:15:54 2006 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Fri Jun 30 14:11:57 2006 -0700" }, "message": "[TG3]: Add TSO workaround using GSO\n\nUse GSO to workaround a rare TSO bug on some chips. This hardware\nbug may be triggered when the TSO header size is greater than 80\nbytes. When this condition is detected in a TSO packet, the driver\nwill use GSO to segment the packet to workaround the hardware bug.\n\nThanks to Juergen Kreileder \u003cjk@blackdown.de\u003e for reporting the\nproblem and collecting traces to help debug the problem.\n\nAnd thanks to Herbert Xu \u003cherbert@gondor.apana.org.au\u003e for providing\nthe GSO mechanism that happens to be the perfect workaround for this\nproblem.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "1661394e78b3b2cc868cd0e89c1066974302aaca", "tree": "bdbbe205062b8bb2ae2edc5aab2d224c58ca862b", "parents": [ "f92905deb9bc89834dac247ca1a0d905ebcf629b" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Thu Jun 29 20:15:13 2006 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Fri Jun 30 14:11:55 2006 -0700" }, "message": "[TG3]: Turn on hw fix for ASF problems\n\nClear a bit to enable a hardware fix for some ASF related problem.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "f92905deb9bc89834dac247ca1a0d905ebcf629b", "tree": "63d3eb18e3dd5426791726eed8004087cfa7fbb4", "parents": [ "29315e8770c20cbfe607ad962d87867115a44555" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Thu Jun 29 20:14:29 2006 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Fri Jun 30 14:11:52 2006 -0700" }, "message": "[TG3]: Add rx BD workaround\n\nAdd workaround to limit the burst size of rx BDs being DMA\u0027ed to the\nchip. This works around hardware errata on a number of 5750, 5752,\nand 5755 chips.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "00b7050426da8e7e58c889c5c80a19920d2d41b3", "tree": "55a07464fdf81b23fced966feca2b041af77c6f6", "parents": [ "c71302d61f844f766a44e1b04258086cc41f624e" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Sat Jun 17 21:58:45 2006 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sat Jun 17 21:58:45 2006 -0700" }, "message": "[TG3]: Convert to non-LLTX\n\nHerbert Xu pointed out that it is unsafe to call netif_tx_disable()\nfrom LLTX drivers because it uses dev-\u003exmit_lock to synchronize\nwhereas LLTX drivers use private locks.\n\nConvert tg3 to non-LLTX to fix this issue. tg3 is a lockless driver\nwhere hard_start_xmit and tx completion handling can run concurrently\nunder normal conditions. A tx_lock is only needed to prevent\nnetif_stop_queue and netif_wake_queue race condtions when the queue\nis full.\n\nSo whether we use LLTX or non-LLTX, it makes practically no\ndifference.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "df3e6548186f0baa727cd6d3a492891854bd31f2", "tree": "525617b51451b730b0723d57258c6a8bf7f53d09", "parents": [ "30b6c28d2aca4669f2e609ad5d77ea2a6cf0dd3a" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Fri May 26 17:48:07 2006 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sat Jun 17 21:26:26 2006 -0700" }, "message": "[TG3]: Add recovery logic when MMIOs are re-ordered\n\nAdd recovery logic when we suspect that the system is re-ordering\nMMIOs. Re-ordered MMIOs to the send mailbox can cause bogus tx\ncompletions and hit BUG_ON() in the tx completion path.\n\ntg3 already has logic to handle re-ordered MMIOs by flushing the MMIOs\nthat must be strictly ordered (such as the send mailbox). Determining\nwhen to enable the flush is currently a manual process of adding known\nchipsets to a list.\n\nThe new code replaces the BUG_ON() in the tx completion path with the\ncall to tg3_tx_recover(). It will set the TG3_FLAG_MBOX_WRITE_REORDER\nflag and reset the chip later in the workqueue to recover and start\nflushing MMIOs to the mailbox.\n\nA message to report the problem will be printed. We will then decide\nwhether or not to add the host bridge to the list of chipsets that do\nre-ordering.\n\nWe may add some additional code later to print the host bridge\u0027s ID so\nthat the user can report it more easily.\n\nThe assumption that re-ordering can only happen on x86 systems is also\nremoved.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "f49639e643e69ff233b14966b8d48541d2e17517", "tree": "8faeabd3bfc855f0a0a5a5a37d9fdbeed27a3f20", "parents": [ "5224e6cc3ab5ae03895bbb67f4a26ce72e62ce58" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Fri Jun 09 11:58:36 2006 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Fri Jun 09 12:03:51 2006 -0700" }, "message": "[TG3]: Handle Sun onboard tg3 chips more correctly.\n\nGet rid of all the SUN_570X logic and instead:\n\n1) Make sure MEMARB_ENABLE is set when we probe the SRAM\n for config information. If that is off we will get\n timeouts.\n\n2) Always try to sync with the firmware, if there is no\n firmware running do not treat it as an error and instead\n just report it the first time we notice this condition.\n\n3) If there is no valid SRAM signature, assume the device\n is onboard by setting TG3_FLAG_EEPROM_WRITE_PROT.\n\nUpdate driver version and release date.\n\nWith help from Michael Chan and Fabio Massimo Di Nitto.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "c424cb249dae10fb7f118f89091f1329b62b92f4", "tree": "71fec6de971313c0add0b0c0b7580c736e0f12cb", "parents": [ "c8e1e82b6a97ad44517517aa58b7b794ead0bf33" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Sat Apr 29 18:56:34 2006 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sat Apr 29 18:56:34 2006 -0700" }, "message": "[TG3]: Add phy workaround\n\nAdd some PHY workaround code to reduce jitter on some PHYs.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "bbadf503d7c7e6efe0a4cd731f8855ba08276215", "tree": "1af228388f7f511525b7ef1d4b4777f4e258b2de", "parents": [ "d2d746f83b74022a50d28f7f0f496842c9cde330" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Thu Apr 06 21:46:34 2006 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sun Apr 09 22:25:46 2006 -0700" }, "message": "[TG3]: Speed up SRAM access (2nd version)\n\nSpeed up SRAM read and write functions if possible by using MMIO\ninstead of config. cycles. With this change, the post reset signature\ndone at the end of D3 power change must now be moved before the D3\npower change.\n\nIBM reported a problem on powerpc blades during ethtool self test that\nwas caused by the memory test taking excessively long. Config. cycles\nare very slow on powerpc and the memory test can take more than 10\nseconds to complete using config. cycles.\n\nDavid Miller informed me that an earlier version of the patch caused\nproblems on sparc64 systems with built-in tg3 chips. This version\nfixes the problem by excluding all SUN built-in tg3 chips from doing\nMMIO SRAM access.\n\nTG3_FLAG_EEPROM_WRITE_PROT is also set unconditionally when\nTG3_FLG2_SUN_570X is set. This should be sane as all SUN chips are\nbuilt-in and do not require Vaux switching.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "d2d746f83b74022a50d28f7f0f496842c9cde330", "tree": "4298a55e428e09a2643a53125e34caa6797b5f1e", "parents": [ "7a43c9955178f1cc88374abe1186c0f2ef21e040" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Thu Apr 06 21:45:39 2006 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sun Apr 09 22:25:44 2006 -0700" }, "message": "[TG3]: Kill some less useful flags\n\nKill the TG3_FLAG_NO_{TX|RX}_PSEUDO_CSUM flags because they are not\nvery useful. This will free up some bits for new flags.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "d3c7b886978bef42f5ea487dec376c482d3cd7e3", "tree": "0776fcc78eb223beccc5af0a88b991a7d0284677", "parents": [ "af36e6b6d7f4ad7a5ccfd14dfa71ec941255f93d" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Thu Mar 23 01:28:25 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Thu Mar 23 01:28:25 2006 -0800" }, "message": "[TG3]: Add 5755 nvram support\n\nAdd 5755 nvram support.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "af36e6b6d7f4ad7a5ccfd14dfa71ec941255f93d", "tree": "879c0f2f8be1e6bcd9d64fa4ee952ee959d35357", "parents": [ "b30bd282cbf5c46247a279a2e8d2aae027d9f1bf" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Thu Mar 23 01:28:06 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Thu Mar 23 01:28:06 2006 -0800" }, "message": "[TG3]: Add 5755 support\n\nAdd support for new chip 5755 which is very similar to 5787.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "c4e6575c78b83928c470d81b271909084a2efd37", "tree": "387a32bbd915bfb6d72d297bd86597c9e543e201", "parents": [ "1820180b0e59cc48019414018b180518059f50d3" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Mon Mar 20 22:29:32 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Mon Mar 20 22:29:32 2006 -0800" }, "message": "[TG3]: Add firmware version info\n\nAdd fw_version information to ethtool -i.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "fcfa0a32c767219c1bdad621ef4a3aff1904cbbd", "tree": "0b40b3432cc90af0e2b22da056baab173d163d65", "parents": [ "9c27dbdf64cba05d0cacc343118a7fd01d4b82f7" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Mon Mar 20 22:28:41 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Mon Mar 20 22:28:41 2006 -0800" }, "message": "[TG3]: Add new one-shot MSI handler\n\nSupport one-shot MSI on 5787.\n\nThis one-shot MSI idea is credited to David Miller. In this mode, MSI\ndisables itself automatically after it is generated, saving the driver\na register access to disable it for NAPI.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "5a6f3074c2ea5a7b4ff5b18f0e1fd9b1257e1a29", "tree": "4bc683f620e3176ae70932f5f865fe47423eb083", "parents": [ "1b27777a9b9b2b6d1c06000b7a31262d198b4238" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Mon Mar 20 22:28:05 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Mon Mar 20 22:28:05 2006 -0800" }, "message": "[TG3]: Add new hard_start_xmit\n\nSupport 5787 hardware TSO using a new flag TG3_FLG2_HW_TSO_2.\n\nSince the TSO interface is slightly different and these chips have\nfinally fixed the 4GB DMA problem and do not have the 40-bit DMA\nproblem, a new hard_start_xmit is used for these chips. All previous\nchips will use the old hard_start_xmit that is now renamed\ntg3_start_xmit_dma_bug().\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "1b27777a9b9b2b6d1c06000b7a31262d198b4238", "tree": "4690a8fe70231e4b09171957a5d3e8a7b4ccb00c", "parents": [ "d9ab5ad12b0d865bdb1b750d81192d34465541e9" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Mon Mar 20 22:27:48 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Mon Mar 20 22:27:48 2006 -0800" }, "message": "[TG3]: Add 5787 nvram support\n\nSupport additional nvrams and new nvram format for 5787 and 5754.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "d9ab5ad12b0d865bdb1b750d81192d34465541e9", "tree": "0bc4b3e9139836b39e5cab3affe9090bae4b11c7", "parents": [ "6cb153cab92a6dc8771d496b10a50cd066fa7f71" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Mon Mar 20 22:27:35 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Mon Mar 20 22:27:35 2006 -0800" }, "message": "[TG3]: Add 5787 and 5754 basic support\n\nAdd basic support for 2 new chips 5787 and 5754.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "4a29cc2e503b33a1e96db4c3f9a94165f153f259", "tree": "74645b5ef3a92ad9857ed63d6446e2be0535060c", "parents": [ "c7c694d196a39af6e644e24279953d04f30362db" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Sun Mar 19 13:21:12 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sun Mar 19 13:21:12 2006 -0800" }, "message": "[TG3]: 40-bit DMA workaround part 2\n\nThe 40-bit DMA workaround recently implemented for 5714, 5715, and\n5780 needs to be expanded because there may be other tg3 devices\nbehind the EPB Express to PCIX bridge in the 5780 class device.\n\nFor example, some 4-port card or mother board designs have 5704 behind\nthe 5714.\n\nAll devices behind the EPB require the 40-bit DMA workaround.\n\nThanks to Chris Elmquist again for reporting the problem and testing\nthe patch.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "7faa006f94fda56a587242b2a22fa19abf840222", "tree": "b1354b391829bc3f1d83fd3121167318f8472147", "parents": [ "3f330317ab4973178423aba750d6d0ca5ce0024a" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Thu Feb 02 17:29:28 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Thu Feb 02 17:29:28 2006 -0800" }, "message": "[TG3]: Flush tg3_reset_task()\n\nMake sure tg3_reset_task() is flushed in the close and suspend paths\nas noted by Jeff Garzik.\n\nIn the close path, calling flush_scheduled_work() may cause deadlock\nif linkwatch_event() is on the workqueue. linkwatch_event() will try\nto get the rtnl_lock() which is already held by tg3_close(). So\ninstead, we set a flag in tg3_reset_task() and tg3_close() polls\nthe flag until it is cleared.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "ec41c7dfd525468decb9da9281dbc9ed82d98c98", "tree": "02ac7f0b1318c69d53a2405972f8a6880dc8b7c6", "parents": [ "f0daaa654af68c1651add9d21188d81c19672551" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Tue Jan 17 02:40:55 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jan 17 02:40:55 2006 -0800" }, "message": "[TG3]: Refine nvram locking\n\nAdd nvram lock count so that calls to tg3_nvram_lock()/unlock() can\nbe nested. Add error checking to all callers of tg3_nvram_lock()\nwhere appropriate. To prevent nvram lock failures after halting the\nfirmware, it is also necessary to release firmware\u0027s nvram lock in\ntg3_halt_cpu().\n\nUpdate version to 3.48.\n\nBased on David Miller\u0027s initial patch.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "091465d7514893a55dcf63e420698b21159c39a7", "tree": "cbfaedb45164d21d0d2f4af5efad2fc78dd37f92", "parents": [ "67dbb4ea33731415fe09c62149a34f472719ac1d" ], "author": { "name": "Chris Elmquist", "email": "chrise@sgi.com", "time": "Tue Dec 20 13:25:19 2005 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Dec 28 13:04:52 2005 -0800" }, "message": "[TG3]: ethtool -d hangs PCIe systems\n\nResubmitting after recommendation to use GET_REG32_1() instead of\nGET_REG32_LOOP(..., 1). Retested. Problem remains fixed.\n\nPrevent tg3_get_regs() from reading reserved and undocumented registers\nat RX_CPU_BASE and TX_CPU_BASE offsets which caused hostile behavior\non PCIe platforms.\n\nAcked-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "6921d201f77e14848df2eaa597e26525f468abea", "tree": "cef66b131fd1cb980d209c5ecb590a0783fdf985", "parents": [ "16fe9d74f14ed74af778c5db7f9129e29916f4a7" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Tue Dec 13 21:15:53 2005 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Dec 13 21:15:53 2005 -0800" }, "message": "[TG3]: Fix low power state\n\nFix the following bugs in tg3_set_power_state():\n\n1. Both WOL and ASF flags require switching to aux power.\n\n2. Add a missing handshake with firmware to enable WOL.\n\n3. Turn off the PHY if both WOL and ASF are disabled.\n\n4. Add nvram arbitration before halting the firmware.\n\n5. Fix tg3_setup_copper_phy() to switch to 100Mbps when\n changing to low power state.\n\nUpdate revision and date.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "28fbef78a420acdea20570d31f3bdcbfa0cac0d2", "tree": "ef68381a6e776a802038e39529e89a0d1390fae0", "parents": [ "a4e2b347848bf626b822599329933887dc90e50f" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Wed Oct 26 15:48:35 2005 -0700" }, "committer": { "name": "Jeff Garzik", "email": "jgarzik@pobox.com", "time": "Fri Oct 28 16:07:30 2005 -0400" }, "message": "[PATCH] tg3: fix ASF heartbeat\n\nChange the ASF heart beat to 5 seconds for faster detection of system\ncrash. The driver sends the heartbeat every 2 seconds and the ASF\nfirmware will timeout and reset the device if no heartbeat is received\nafter 5 seconds. The old scheme of 2 minutes is ineffective.\n\ntg3_write_mem_fast() is added to speed up the IO to send the heartbeat.\nWhen no workaround is needed, it will use direct MMIO to memory space\nto write to memory.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: Jeff Garzik \u003cjgarzik@pobox.com\u003e\n" }, { "commit": "a4e2b347848bf626b822599329933887dc90e50f", "tree": "414564393157868b8c6d708bfb2c750cf49b1f6b", "parents": [ "5fadd053d9bb4345ec6f405d24db4e7eb49cf81e" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Wed Oct 26 15:46:52 2005 -0700" }, "committer": { "name": "Jeff Garzik", "email": "jgarzik@pobox.com", "time": "Fri Oct 28 16:07:29 2005 -0400" }, "message": "[PATCH] tg3: add 5714/5715 support\n\nAdd complete support for 5714/5715. These chips are very similar to\n5780 so the changes are very trivial. A TG3_FLG2_5780_CLASS flag is\nadded to identify these chips.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: Jeff Garzik \u003cjgarzik@pobox.com\u003e\n" }, { "commit": "c94e39418ab6eccf863581f4e0d847da0080b2d3", "tree": "d7b38279d14d93160ffaed214898973fb2062061", "parents": [ "667347f1ca7e099f6833551f194cf2bcc778871b" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Tue Sep 27 12:12:42 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Sep 27 12:12:42 2005 -0700" }, "message": "[TG3]: 5780 PHY fixes\n\nFix 5780 PHY related problems:\n\n1. MAC_RX_MODE reset must be done before setting up the MAC_MODE\n register on 5705_PLUS chips or the chip will stop receiving after\n a while. The MAC_RX_MODE reset is needed to prevent intermittently\n losing the first receive packet on serdes chips.\n\n2. Skip MAC loopback test on 5780 because of hardware errata. Normal\n traffic including PHY loopback is not affected by the errata.\n\n3. PHY loopback fails intermittently on 5708S and this is fixed by\n putting the PHY in loopback mode first before programming the MAC\n mode register. A MAC_RX_MODE reset is also added.\n\n4. Return -EINVAL in tg3_nway_reset() if device is in TBI mode. Allow\n nway_reset if 5780S is in parallel detect mode.\n\n5. Add missing PHY IDs in KNOWN_PHY_ID() macro.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "6892914fb7980d844f2bac859f4095df9ebd18da", "tree": "ddeb1904b798bb69ed248840f25477bf8891d250", "parents": [ "09ee929cccfd0b56ea3724b3c6299fbbe813df43" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Tue Aug 09 20:17:14 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Aug 29 15:50:42 2005 -0700" }, "message": "[TG3]: Add indirect register method for 5703 behind ICH\n\nThis patch adds the new workaround for 5703 A1/A2 if it is behind\ncertain ICH bridges. The workaround disables memory and uses config.\ncycles only to access all registers. The 5702/03 chips can mistakenly\ndecode the special cycles from the ICH chipsets as memory write cycles,\ncausing corruption of register and memory space. Only certain ICH\nbridges will drive special cycles with non-zero data during the address\nphase which can fall within the 5703\u0027s address range. This is not an ICH\nbug as the PCI spec allows non-zero address during special cycles.\nHowever, only these ICH bridges are known to drive non-zero addresses\nduring special cycles.\n\nThe indirect_lock is also changed to spin_lock_irqsave from spin_lock_bh\nbecause it is used in irq handler when using the indirect method to\ndisable interrupts.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "09ee929cccfd0b56ea3724b3c6299fbbe813df43", "tree": "52d0002518d41a6eea12859f9134c17d2af6c473", "parents": [ "1ee582d8e49a1c9dd43b2599f1cd26507182a8d4" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Tue Aug 09 20:17:00 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Aug 29 15:50:38 2005 -0700" }, "message": "[TG3]: Add mailbox read method\n\nThis patch adds the mailbox read method and also adds an inline function\ntw32_mailbox_f() for mailbox writes that require read flush.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "2009493065e01b1fe27c1b98ffbcfab98e185f72", "tree": "8a8981461a4f84a007f4725a027f3185055737ea", "parents": [ "757f612e091e7d13707eedc3ff71f1a9b53f5537" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Tue Aug 09 20:16:32 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Aug 29 15:50:12 2005 -0700" }, "message": "[TG3]: Add basic register access function pointers\n\nThis patch adds the basic function pointers to do register accesses in\nthe fast path. This was suggested by David Miller. The idea is that\nvarious register access methods for different hardware errata can easily\nbe implemented with these function pointers and performance will not be\ndegraded on chips that use normal register access methods.\n\nThe various register read write macros (e.g. tw32, tr32, tw32_mailbox)\nare redefined to call the function pointers.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "747e8f8bff56955374521fa4d488e702d4b0c04f", "tree": "66ab6d67818338a0421ef1e374ff15666c85dfa6", "parents": [ "ef7f5ec0deb2bcdc005f30f6f75f79c65c577cf5" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Mon Jul 25 12:33:22 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Mon Jul 25 12:33:22 2005 -0700" }, "message": "[TG3]: add 5780 fiber support\n\nAdd 5780S support by adding a new tg3_setup_fiber_mii_phy() function and\na timer function for parallel link detection. 5780S uses standard MII\nregisters for 1000BaseX and runs in GMII mode as opposed to TBI mode on\nolder serdes chips.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "fdfec1726b14b4b2121adcfcbba98d4cc1a61751", "tree": "7cb407d307526b41165f974ee318c36b92e04a9e", "parents": [ "7e72aad48c3790636bfa006f3b0027852ccad47e" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Mon Jul 25 12:31:48 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Mon Jul 25 12:31:48 2005 -0700" }, "message": "[TG3]: consolidate all DMA water mark settings\n\nConsolidate all DMA watermark settings for standard and jumbo frames on\nall chips in tg3_init_bufmgr_config() and add new settings for 5780.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "7e72aad48c3790636bfa006f3b0027852ccad47e", "tree": "ba2f201b4554f95b3e432f75f6cc7a2cbb296f70", "parents": [ "0f893dc6ec890058d926224c8aa254d8621e0ea3" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Mon Jul 25 12:31:17 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Mon Jul 25 12:31:17 2005 -0700" }, "message": "[TG3]: add variable buffer size for standard ring\n\nAdd a new rx_pkt_buf_sz to the tg3 structure to support variable buffer\nsizes on the standard ring.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "0f893dc6ec890058d926224c8aa254d8621e0ea3", "tree": "9a9c42335bac0c05aed89ed7139a22d022f5d064", "parents": [ "4cf78e4fb678807e3f8265c9e9031a84f5c601f0" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Mon Jul 25 12:30:38 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Mon Jul 25 12:30:38 2005 -0700" }, "message": "[TG3]: add 5780 basic jumbo frame support\n\nAdd basic jumbo frames support for 5780. This chip supports jumbo frames\non the standard receive ring without the jumbo ring. The\nTG3_FLAG_JUMBO_ENABLE is changed to TG3_FLAG_JUMBO_RING_ENABLE to\nindicate using the jumbo ring on 5704 and older chips. A new\nTG3_FLG2_JUMBO_CAPABLE flag is added to indicate jumbo frames support\nwith or without the jumbo ring.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "4cf78e4fb678807e3f8265c9e9031a84f5c601f0", "tree": "e5acc4451c7e9f59125119174b05ca95c652c2df", "parents": [ "6b6a93c6876ea1c530d5d3f68e3678093a27fab0" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Mon Jul 25 12:29:19 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Mon Jul 25 12:29:19 2005 -0700" }, "message": "[TG3]: add 5780 basic support\n\nAdd 5780 PCI IDs, chip IDs, and other basic support.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "d244c892c8e23d6baba88af88f78f7201a224d39", "tree": "03e79b06198f0e12bbf8d4bf25cfb93ee3c31eba", "parents": [ "e2ed4052aa662e7cfb22a1793b9d8158603be6d7" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Tue Jul 05 14:42:33 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jul 05 14:42:33 2005 -0700" }, "message": "[TG3]: support for ethtool -C\n\nAdd support for ethtool -C with verification of user parameters.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "f47c11eeccc8820010992eb32dbe7370a08f8bd3", "tree": "7cd6308a1796fae227c61208545593b79b12f21a", "parents": [ "cd024c8baf9756759c57f0a19be639da8d3d4f8c" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Fri Jun 24 20:18:35 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Fri Jun 24 20:18:35 2005 -0700" }, "message": "[TG3]: Eliminate all hw IRQ handler spinlocks.\n\nMove all driver spinlocks to be taken at sw IRQ\ncontext only.\n\nThis fixes the skb_copy() we were doing with hw\nIRQs disabled (which is illegal and triggers a\nBUG() with HIGHMEM enabled). It also simplifies\nthe locking all over the driver tremendously.\n\nWe accomplish this feat by creating a special\nsequence to synchronize with the hw IRQ handler\nusing a binary state and synchronize_irq().\nThis idea is from Herbert Xu.\n\nThanks to Michael Chan for helping to track down\nall of the race conditions in initial versions\nof this code.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "15f9850d3c2d46f5851a424d2990a18b5bb5ebfd", "tree": "a96514f0f797e0a315e12450279d103a888d1083", "parents": [ "fac9b83ea79aa3112ed245d9a4fc2a5c3ec2b7ec" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Wed May 18 22:49:26 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Wed May 18 22:49:26 2005 -0700" }, "message": "[TG3]: Set minimal hw interrupt mitigation.\n\nEven though we do software interrupt mitigation\nvia NAPI, it still helps to have some minimal\nhw assisted mitigation.\n\nThis helps, particularly, on systems where register\nI/O overhead is much greater than the CPU horsepower.\n\nFor example, it helps on NUMA systems. In such cases\nthe PIO overhead to disable interrupts for NAPI accounts\nfor the majority of the packet processing cost. The\nCPU is fast enough such that only a single packet is\nprocessed by each NAPI poll call.\n\nThanks to Michael Chan for reviewing this patch.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "fac9b83ea79aa3112ed245d9a4fc2a5c3ec2b7ec", "tree": "14749e6e5e0abdfb707b41dad714e36246e6cff8", "parents": [ "05d3794aa8bd3b2c9f7920a05003c331cdeb75c5" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Wed May 18 22:46:34 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Wed May 18 22:46:34 2005 -0700" }, "message": "[TG3]: Add tagged status support.\n\nWhen supported, use the TAGGED interrupt processing support\nthe chip provides. In this mode, instead of a \"on/off\" binary\nsemaphore, an incrementing tag scheme is used to ACK interrupts.\n\nAll MSI supporting chips support TAGGED mode, so the tg3_msi()\ninterrupt handler uses it unconditionally. This invariant is\nverified when MSI support is tested.\n\nSince we can invoke tg3_poll() multiple times per interrupt under\nhigh packet load, we fetch a new copy of the tag value in the\nstatus block right before we actually do the work.\n\nAlso, because the tagged status tells the chip exactly which\nwork we have processed, we can make two optimizations:\n\n1) tg3_restart_ints() need not check tg3_has_work()\n2) the tg3_timer() need not poke the chip 10 times per\n second to keep from losing interrupt events\n\nBased upon valuable feedback from Michael Chan \u003cmchan@broadcom.com\u003e\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "88b06bc26b87cf0490b0e3faea7fefc7549dd75d", "tree": "ffba7c235ad94e3c1e0074cb209504e6ea25afe3", "parents": [ "1c8594b48b00a98d12477355e944e165a5f64cd5" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Thu Apr 21 17:13:25 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Apr 21 17:13:25 2005 -0700" }, "message": "[TG3]: Add msi support\n\nAdd MSI support for 5751 C0 and 5752.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "e6af301be3c129adbc8a7c8ffb76e62533ad9575", "tree": "02b2fd5de20468f5966cf3e73fbfa5e6f86baa63", "parents": [ "361b4ac29bc651c7612d4bf21434ae6fe06b78e4" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Thu Apr 21 17:12:05 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Apr 21 17:12:05 2005 -0700" }, "message": "[TG3]: Add nvram lock-out support for 5752 TPM\n\nAdd support for the NVRAM lock-out feature for TPM in 5752. If lock-out\nis enabled, certain NVRAM registers cannot be written to.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "361b4ac29bc651c7612d4bf21434ae6fe06b78e4", "tree": "a0d1b0a7f89a7d45c63b269bef5eeacf6f8dc734", "parents": [ "3e7d83bc96d59013792e5546e7832668d3adbce7" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Thu Apr 21 17:11:21 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Apr 21 17:11:21 2005 -0700" }, "message": "[TG3]: Add nvram detection for 5752\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "3e7d83bc96d59013792e5546e7832668d3adbce7", "tree": "e622228e8fd43e1461ea525afa453fbcddc39125", "parents": [ "ff645bec523819fa4d28d7e0de7d998e3edb0c57" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Thu Apr 21 17:10:36 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Apr 21 17:10:36 2005 -0700" }, "message": "[TG3]: Add GPIO3 for 5752\n\nAdd bit definitions for the new GPIO3 in 5752. GPIO3 must be driven as\noutput when it is unused.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "ff645bec523819fa4d28d7e0de7d998e3edb0c57", "tree": "b1f7bff1f67465f53adf9906d73d87412edfa876", "parents": [ "8c6bda1a89c148f3a28edc09a76dac9bff57d8ee" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Thu Apr 21 17:09:53 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Apr 21 17:09:53 2005 -0700" }, "message": "[TG3]: Workaround 5752 A0 chip ID\n\nThe 5752 A0 chip ID is wrong in hardware. The simplest way to workaround\nit is to change it to the correct value in tp-\u003epci_chip_rev_id. This\nway, it is easier to check for the ASIC_REV_5752 in the rest of the\ndriver.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "85e94cedc44d1c2c1663b5b18f703ca5e7316e59", "tree": "0e28e8b073f7ecefd2916dd40d248b914d1a6c0b", "parents": [ "053d78000be4906fac6446ad517ca3897dc6cd84" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Thu Apr 21 17:05:28 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Apr 21 17:05:28 2005 -0700" }, "message": "[TG3]: Minor 5752 fixes\n\nSome minor 5752 fixes mostly for correctness and add 5752 PHY ID.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "053d78000be4906fac6446ad517ca3897dc6cd84", "tree": "3ba4a5f488457ce6432d956b2363e3a3806396f6", "parents": [ "1b440c568e28186956ef765c69ab124401088663" ], "author": { "name": "John W. Linville", "email": "linville@tuxdriver.com", "time": "Thu Apr 21 17:03:52 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Apr 21 17:03:52 2005 -0700" }, "message": "[TG3]: add support for bcm5752 rev a1\n\nReplace existing ASIC_REV_5752 definition with ASIC_REV_5752_A0,\nand add definition for ASIC_REV_5752_A1. Then, add ASIC_REV_5752_A1\nto check for setting TG3_FLG2_5750_PLUS in tg3_get_invariants.\n\nSigned-off-by: John W. Linville \u003clinville@tuxdriver.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" } ], "next": "6708e5cc103ba045fca035b4d8df236ca31fb8bc" }