)]}' { "log": [ { "commit": "6dec3a10a7a6093af10cef7ac56021150afd6451", "tree": "f4d8511f023e3e0c203baf889d4a0f3925882381", "parents": [ "29308333fbe2cc61258c1c470f9403960428beb2", "10a010f6953b5a14ba2f0be40a4fce1bea220875" ], "author": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Sat Jul 26 16:29:23 2008 +0200" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Sat Jul 26 16:29:23 2008 +0200" }, "message": "Merge branch \u0027x86/x2apic\u0027 into x86/core\n\nConflicts:\n\n\tinclude/asm-x86/i8259.h\n\tinclude/asm-x86/msidef.h\n\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "77ef50a522717fa040636ee1017179ceba12ff62", "tree": "57b082ad5b314605d5d9dab50068737f324cae60", "parents": [ "a656c8efb40a8700046df20da2195f8aa39ce38a" ], "author": { "name": "Vegard Nossum", "email": "vegard.nossum@gmail.com", "time": "Wed Jun 18 17:08:48 2008 +0200" }, "committer": { "name": "Vegard Nossum", "email": "vegard.nossum@gmail.com", "time": "Tue Jul 22 21:31:34 2008 +0200" }, "message": "x86: consolidate header guards\n\nThis patch is the result of an automatic script that consolidates the\nformat of all the headers in include/asm-x86/.\n\nThe format:\n\n1. No leading underscore. Names with leading underscores are reserved.\n2. Pathname components are separated by two underscores. So we can\n distinguish between mm_types.h and mm/types.h.\n3. Everything except letters and numbers are turned into single\n underscores.\n\nSigned-off-by: Vegard Nossum \u003cvegard.nossum@gmail.com\u003e\n" }, { "commit": "75c46fa61bc5b4ccd20a168ff325c58771248fcd", "tree": "ff5abfe689fe732ad73a198e1f3e56b8c4ca6024", "parents": [ "89027d35aa5b8f45ce0f7fa0911db85b46563da0" ], "author": { "name": "Suresh Siddha", "email": "suresh.b.siddha@intel.com", "time": "Thu Jul 10 11:16:57 2008 -0700" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Sat Jul 12 08:45:05 2008 +0200" }, "message": "x64, x2apic/intr-remap: MSI and MSI-X support for interrupt remapping infrastructure\n\nMSI and MSI-X support for interrupt remapping infrastructure.\n\nMSI address register will be programmed with interrupt-remapping table\nentry(IRTE) index and the IRTE will contain information about the vector,\ncpu destination, etc.\n\nFor MSI-X, all the IRTE\u0027s will be consecutively allocated in the table,\nand the address registers will contain the starting index to the block\nand the data register will contain the subindex with in that block.\n\nThis also introduces a new irq_chip for cleaner irq migration (in the process\ncontext as opposed to the current irq migration in the context of an interrupt.\ninterrupt-remapping infrastructure will help us achieve this).\n\nAs MSI is edge triggered, irq migration is a simple atomic update(of vector\nand cpu destination) of IRTE and flushing the hardware cache.\n\nSigned-off-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nCc: akpm@linux-foundation.org\nCc: arjan@linux.intel.com\nCc: andi@firstfloor.org\nCc: ebiederm@xmission.com\nCc: jbarnes@virtuousgeek.org\nCc: steiner@sgi.com\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "934902b474bdb235a273985ad4c61eb136afe11d", "tree": "52a59dcfe955f48615ab4ef63a86d311327d14f7", "parents": [ "30971e17ee484f72e081826a0bf3e489ef3b4c30" ], "author": { "name": "Joe Perches", "email": "joe@perches.com", "time": "Sun Mar 23 01:02:50 2008 -0700" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Thu Apr 17 17:41:25 2008 +0200" }, "message": "include/asm-x86/msidef.h: checkpatch cleanups - formatting only\n\nSigned-off-by: Joe Perches \u003cjoe@perches.com\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "96a388de5dc53a8b234b3fd41f3ae2cedc9ffd42", "tree": "d947a467aa2da3140279617bc4b9b101640d7bf4", "parents": [ "27bd0c955648646abf2a353a8371d28c37bcd982" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Thu Oct 11 11:20:03 2007 +0200" }, "committer": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Thu Oct 11 11:20:03 2007 +0200" }, "message": "i386/x86_64: move headers to include/asm-x86\n\nMove the headers to include/asm-x86 and fixup the\nheader install make rules\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "2d3fcc1c54df2f49674e1f7c99d4800ed1d51902", "tree": "7cf478bc419f8f0c17be929b5ffdac6fc4236b70", "parents": [ "589e367f9b9117b3412da0d4e10ea6882db8da84" ], "author": { "name": "Eric W. Biederman", "email": "ebiederm@xmission.com", "time": "Wed Oct 04 02:16:43 2006 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Wed Oct 04 07:55:28 2006 -0700" }, "message": "[PATCH] genirq: i386 irq: Move msi message composition into io_apic.c\n\nThis removes the hardcoded assumption that irq \u003d\u003d vector in the msi\ncomposition code, and it allows the msi message composition to setup logical\nmode, or lowest priorirty delivery mode as we do for other apic interrupts,\nand with the same selection criteria.\n\nBasically this moves the problem of what is in the msi message into the\narchitecture irq management code where it belongs. Not in a generic layer\nthat doesn\u0027t have enough information to compose msi messages properly.\n\nSigned-off-by: Eric W. Biederman \u003cebiederm@xmission.com\u003e\nCc: Ingo Molnar \u003cmingo@elte.hu\u003e\nCc: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nCc: Rajesh Shah \u003crajesh.shah@intel.com\u003e\nCc: Andi Kleen \u003cak@muc.de\u003e\nCc: \"Protasevich, Natalie\" \u003cNatalie.Protasevich@UNISYS.com\u003e\nCc: \"Luck, Tony\" \u003ctony.luck@intel.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" } ] }