)]}'
{
  "log": [
    {
      "commit": "5e5419734c8719cbc01af959ad9c0844002c0df5",
      "tree": "a075dca3f719946689efa0245464855cbf2a20ce",
      "parents": [
        "9f8f2172537de7af0b0fbd33502d18d52b1339bc"
      ],
      "author": {
        "name": "Benjamin Herrenschmidt",
        "email": "benh@kernel.crashing.org",
        "time": "Mon Feb 04 22:29:14 2008 -0800"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@woody.linux-foundation.org",
        "time": "Tue Feb 05 09:44:18 2008 -0800"
      },
      "message": "add mm argument to pte/pmd/pud/pgd_free\n\n(with Martin Schwidefsky \u003cschwidefsky@de.ibm.com\u003e)\n\nThe pgd/pud/pmd/pte page table allocation functions get a mm_struct pointer as\nfirst argument.  The free functions do not get the mm_struct argument.  This\nis 1) asymmetrical and 2) to do mm related page table allocations the mm\nargument is needed on the free function as well.\n\n[kamalesh@linux.vnet.ibm.com: i386 fix]\n[akpm@linux-foundation.org: coding-syle fixes]\nSigned-off-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nSigned-off-by: Martin Schwidefsky \u003cschwidefsky@de.ibm.com\u003e\nCc: \u003clinux-arch@vger.kernel.org\u003e\nSigned-off-by: Kamalesh Babulal \u003ckamalesh@linux.vnet.ibm.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n"
    },
    {
      "commit": "6656920b0b50beacb6cb64cf55273cbb686e436e",
      "tree": "dab9fdb81821b455a29779de6ca3306dbdf05dbd",
      "parents": [
        "ff6fd469885aafa5ec387babcb6537f3c00d6df0"
      ],
      "author": {
        "name": "Chris Zankel",
        "email": "chris@zankel.net",
        "time": "Wed Aug 22 10:14:51 2007 -0700"
      },
      "committer": {
        "name": "Chris Zankel",
        "email": "chris@zankel.net",
        "time": "Mon Aug 27 13:54:16 2007 -0700"
      },
      "message": "[XTENSA] Add support for cache-aliasing\n\nAdd support for processors that have cache-aliasing issues, such as\nthe Stretch S5000 processor. Cache-aliasing means that the size of\nthe cache (for one way) is larger than the page size, thus, a page\ncan end up in several places in cache depending on the virtual to\nphysical translation. The method used here is to map a user page\ntemporarily through the auto-refill way 0 and of of the DTLB.\nWe probably will want to revisit this issue and use a better\napproach with kmap/kunmap.\n\nSigned-off-by: Chris Zankel \u003cchris@zankel.net\u003e\n"
    },
    {
      "commit": "9a8fd5589902153a134111ed7a40f9cca1f83254",
      "tree": "6f7a06de25bdf0b2d94623794c2cbbc66b5a77f6",
      "parents": [
        "3f65ce4d141e435e54c20ed2379d983d362a2cb5"
      ],
      "author": {
        "name": "Chris Zankel",
        "email": "czankel@tensilica.com",
        "time": "Thu Jun 23 22:01:26 2005 -0700"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@ppc970.osdl.org",
        "time": "Fri Jun 24 00:05:22 2005 -0700"
      },
      "message": "[PATCH] xtensa: Architecture support for Tensilica Xtensa Part 6\n\nThe attached patches provides part 6 of an architecture implementation for the\nTensilica Xtensa CPU series.\n\nSigned-off-by: Chris Zankel \u003cchris@zankel.net\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n"
    }
  ]
}