)]}'
{
  "log": [
    {
      "commit": "3c4108c82f7769fcd265dc77a5bb0c6d8bcea25f",
      "tree": "9b5c09318f884a7ba279d4da63551098ecba69a2",
      "parents": [
        "06c77e21ae7c199435097116b8212b0761fc8ba8"
      ],
      "author": {
        "name": "Feng Tang",
        "email": "feng.tang@intel.com",
        "time": "Tue Jul 27 08:20:52 2010 +0100"
      },
      "committer": {
        "name": "Greg Kroah-Hartman",
        "email": "gregkh@suse.de",
        "time": "Tue Aug 10 13:47:46 2010 -0700"
      },
      "message": "hsu: call PCI pm hooks in suspend/resume function\n\nAlso add check for dma controller or the uart ports.\n\nSigned-off-by: Feng Tang \u003cfeng.tang@intel.com\u003e\nSigned-off-by: Alan Cox \u003calan@linux.intel.com\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n"
    },
    {
      "commit": "06c77e21ae7c199435097116b8212b0761fc8ba8",
      "tree": "2ae53076c07cbf8c112345aeeedb26a22ad7fd59",
      "parents": [
        "669b7a0938e759097c150400cd36bd49befaf5bb"
      ],
      "author": {
        "name": "Feng Tang",
        "email": "feng.tang@intel.com",
        "time": "Tue Jul 27 08:20:42 2010 +0100"
      },
      "committer": {
        "name": "Greg Kroah-Hartman",
        "email": "gregkh@suse.de",
        "time": "Tue Aug 10 13:47:46 2010 -0700"
      },
      "message": "hsu: some code cleanup\n\nMajor changes are:\n* refine the comments in the driver\n* remove unused member from structure \"hsu_port\"\n* extended spin_lock protoction for dma mode in port_irq()\n\nSigned-off-by: Feng Tang \u003cfeng.tang@intel.com\u003e\nSigned-off-by: Alan Cox \u003calan@linux.intel.com\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n"
    },
    {
      "commit": "669b7a0938e759097c150400cd36bd49befaf5bb",
      "tree": "b7244699ea1e8bf04c50dde2b9efeaf504f44bc6",
      "parents": [
        "d843fc6e9dc9bee7061b6833594860ea93ad98e1"
      ],
      "author": {
        "name": "Feng Tang",
        "email": "feng.tang@intel.com",
        "time": "Tue Jul 27 08:20:32 2010 +0100"
      },
      "committer": {
        "name": "Greg Kroah-Hartman",
        "email": "gregkh@suse.de",
        "time": "Tue Aug 10 13:47:46 2010 -0700"
      },
      "message": "hsu: add a periodic timer to check dma rx channel\n\nA general problem for uart rx dma channel is you never know when\nand how much data will be received, so usually preset it a DMA\ndescriptor with a big size, and rely on DMA RX timeout IRQ to\nknow there is some data in rx channel.\n\nFor a RX data size of multiple of MOTSR, there will be no timeout\nIRQ issued, thus OS will never be notified about that.\n\nThis is a work around for that, current timer frequency is 5 times\nper second, it should vary according to the baud rate\n\nWhen future silicon version fix the problem, this workaround need\nbe removed\n\nSigned-off-by: Feng Tang \u003cfeng.tang@intel.com\u003e\nSigned-off-by: Alan Cox \u003calan@linux.intel.com\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n"
    },
    {
      "commit": "d843fc6e9dc9bee7061b6833594860ea93ad98e1",
      "tree": "825f25909de7b4056a5c8e4180b2068fff339070",
      "parents": [
        "464eb8f596fcbdadcfbbdb4a84847ffcb93cc4dd"
      ],
      "author": {
        "name": "Feng Tang",
        "email": "feng.tang@intel.com",
        "time": "Tue Jul 27 08:20:22 2010 +0100"
      },
      "committer": {
        "name": "Greg Kroah-Hartman",
        "email": "gregkh@suse.de",
        "time": "Tue Aug 10 13:47:46 2010 -0700"
      },
      "message": "hsu: driver for Medfield High Speed UART device\n\nThis is a PCI \u0026 UART driver, which suppors both PIO and DMA mode\nUART operation. It has 3 identical UART ports and one internal\nDMA controller.\n\nCurrent FW will export 4 pci devices for hsu: 3 uart ports and 1\ndma controller, each has one IRQ line. And we need to discuss the\ndevice model, one PCI device covering whole HSU should be a better\nmodel, but there is a problem of how to export the 4 IRQs info\n\nCurrent driver set the highest baud rate to 2746800bps, which is\neasy to scale down to 115200/230400.... To suport higher baud rate,\nwe need add special process, change DLAB/DLH/PS/DIV/MUL registers\nall together.\n\n921600 is the highest baud rate that has been tested with Bluetooth\nmodem connected to HSU port 0. Will test more when there is right\nBT firmware.\n\nCurrent version contains several work around for A0\u0027s Silicon bugs\n\nSigned-off-by: Feng Tang \u003cfeng.tang@intel.com\u003e\nSigned-off-by: Alan Cox \u003calan@linux.intel.com\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n"
    }
  ]
}