)]}' { "log": [ { "commit": "5a0e3ad6af8660be21ca98a971cd00f331318c05", "tree": "5bfb7be11a03176a87296a43ac6647975c00a1d1", "parents": [ "ed391f4ebf8f701d3566423ce8f17e614cde9806" ], "author": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Wed Mar 24 17:04:11 2010 +0900" }, "committer": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Tue Mar 30 22:02:32 2010 +0900" }, "message": "include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h\n\npercpu.h is included by sched.h and module.h and thus ends up being\nincluded when building most .c files. percpu.h includes slab.h which\nin turn includes gfp.h making everything defined by the two files\nuniversally available and complicating inclusion dependencies.\n\npercpu.h -\u003e slab.h dependency is about to be removed. Prepare for\nthis change by updating users of gfp and slab facilities include those\nheaders directly instead of assuming availability. As this conversion\nneeds to touch large number of source files, the following script is\nused as the basis of conversion.\n\n http://userweb.kernel.org/~tj/misc/slabh-sweep.py\n\nThe script does the followings.\n\n* Scan files for gfp and slab usages and update includes such that\n only the necessary includes are there. ie. if only gfp is used,\n gfp.h, if slab is used, slab.h.\n\n* When the script inserts a new include, it looks at the include\n blocks and try to put the new include such that its order conforms\n to its surrounding. It\u0027s put in the include block which contains\n core kernel includes, in the same order that the rest are ordered -\n alphabetical, Christmas tree, rev-Xmas-tree or at the end if there\n doesn\u0027t seem to be any matching order.\n\n* If the script can\u0027t find a place to put a new include (mostly\n because the file doesn\u0027t have fitting include block), it prints out\n an error message indicating which .h file needs to be added to the\n file.\n\nThe conversion was done in the following steps.\n\n1. The initial automatic conversion of all .c files updated slightly\n over 4000 files, deleting around 700 includes and adding ~480 gfp.h\n and ~3000 slab.h inclusions. The script emitted errors for ~400\n files.\n\n2. Each error was manually checked. Some didn\u0027t need the inclusion,\n some needed manual addition while adding it to implementation .h or\n embedding .c file was more appropriate for others. This step added\n inclusions to around 150 files.\n\n3. The script was run again and the output was compared to the edits\n from #2 to make sure no file was left behind.\n\n4. Several build tests were done and a couple of problems were fixed.\n e.g. lib/decompress_*.c used malloc/free() wrappers around slab\n APIs requiring slab.h to be added manually.\n\n5. The script was run on all .h files but without automatically\n editing them as sprinkling gfp.h and slab.h inclusions around .h\n files could easily lead to inclusion dependency hell. Most gfp.h\n inclusion directives were ignored as stuff from gfp.h was usually\n wildly available and often used in preprocessor macros. Each\n slab.h inclusion directive was examined and added manually as\n necessary.\n\n6. percpu.h was updated not to include slab.h.\n\n7. Build test were done on the following configurations and failures\n were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my\n distributed build env didn\u0027t work with gcov compiles) and a few\n more options had to be turned off depending on archs to make things\n build (like ipr on powerpc/64 which failed due to missing writeq).\n\n * x86 and x86_64 UP and SMP allmodconfig and a custom test config.\n * powerpc and powerpc64 SMP allmodconfig\n * sparc and sparc64 SMP allmodconfig\n * ia64 SMP allmodconfig\n * s390 SMP allmodconfig\n * alpha SMP allmodconfig\n * um on x86_64 SMP allmodconfig\n\n8. percpu.h modifications were reverted so that it could be applied as\n a separate patch and serve as bisection point.\n\nGiven the fact that I had only a couple of failures from tests on step\n6, I\u0027m fairly confident about the coverage of this conversion patch.\nIf there is a breakage, it\u0027s likely to be something in one of the arch\nheaders which should be easily discoverable easily on most builds of\nthe specific arch.\n\nSigned-off-by: Tejun Heo \u003ctj@kernel.org\u003e\nGuess-its-ok-by: Christoph Lameter \u003ccl@linux-foundation.org\u003e\nCc: Ingo Molnar \u003cmingo@redhat.com\u003e\nCc: Lee Schermerhorn \u003cLee.Schermerhorn@hp.com\u003e\n" }, { "commit": "e84665c9cb4db963393fafad6fefe5efdd7e4a09", "tree": "545c4a2a63a77b853e3f34609d86b346fe61baf4", "parents": [ "076d3e10a54caa2c148de5732c126c7a31381d48" ], "author": { "name": "Lennert Buytenhek", "email": "buytenh@wantstofly.org", "time": "Fri Mar 20 09:52:09 2009 +0000" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sat Mar 21 19:06:54 2009 -0700" }, "message": "dsa: add switch chip cascading support\n\nThe initial version of the DSA driver only supported a single switch\nchip per network interface, while DSA-capable switch chips can be\ninterconnected to form a tree of switch chips. This patch adds support\nfor multiple switch chips on a network interface.\n\nAn example topology for a 16-port device with an embedded CPU is as\nfollows:\n\n\t+-----+ +--------+ +--------+\n\t| |eth0 10| switch |9 10| switch |\n\t| CPU +----------+ +-------+ |\n\t| | | chip 0 | | chip 1 |\n\t+-----+ +---++---+ +---++---+\n\t || ||\n\t || ||\n\t ||1000baseT ||1000baseT\n\t ||ports 1-8 ||ports 9-16\n\nThis requires a couple of interdependent changes in the DSA layer:\n\n- The dsa platform driver data needs to be extended: there is still\n only one netdevice per DSA driver instance (eth0 in the example\n above), but each of the switch chips in the tree needs its own\n mii_bus device pointer, MII management bus address, and port name\n array. (include/net/dsa.h) The existing in-tree dsa users need\n some small changes to deal with this. (arch/arm)\n\n- The DSA and Ethertype DSA tagging modules need to be extended to\n use the DSA device ID field on receive and demultiplex the packet\n accordingly, and fill in the DSA device ID field on transmit\n according to which switch chip the packet is heading to.\n (net/dsa/tag_{dsa,edsa}.c)\n\n- The concept of \"CPU port\", which is the switch chip port that the\n CPU is connected to (port 10 on switch chip 0 in the example), needs\n to be extended with the concept of \"upstream port\", which is the\n port on the switch chip that will bring us one hop closer to the CPU\n (port 10 for both switch chips in the example above).\n\n- The dsa platform data needs to specify which ports on which switch\n chips are links to other switch chips, so that we can enable DSA\n tagging mode on them. (For inter-switch links, we always use\n non-EtherType DSA tagging, since it has lower overhead. The CPU\n link uses dsa or edsa tagging depending on what the \u0027root\u0027 switch\n chip supports.) This is done by specifying \"dsa\" for the given\n port in the port array.\n\n- The dsa platform data needs to be extended with information on via\n which port to reach any given switch chip from any given switch chip.\n This info is specified via the per-switch chip data struct -\u003ertable[]\n array, which gives the nexthop ports for each of the other switches\n in the tree.\n\nFor the example topology above, the dsa platform data would look\nsomething like this:\n\n\tstatic struct dsa_chip_data sw[2] \u003d {\n\t\t{\n\t\t\t.mii_bus\t\u003d \u0026foo,\n\t\t\t.sw_addr\t\u003d 1,\n\t\t\t.port_names[0]\t\u003d \"p1\",\n\t\t\t.port_names[1]\t\u003d \"p2\",\n\t\t\t.port_names[2]\t\u003d \"p3\",\n\t\t\t.port_names[3]\t\u003d \"p4\",\n\t\t\t.port_names[4]\t\u003d \"p5\",\n\t\t\t.port_names[5]\t\u003d \"p6\",\n\t\t\t.port_names[6]\t\u003d \"p7\",\n\t\t\t.port_names[7]\t\u003d \"p8\",\n\t\t\t.port_names[9]\t\u003d \"dsa\",\n\t\t\t.port_names[10]\t\u003d \"cpu\",\n\t\t\t.rtable\t\t\u003d (s8 []){ -1, 9, },\n\t\t}, {\n\t\t\t.mii_bus\t\u003d \u0026foo,\n\t\t\t.sw_addr\t\u003d 2,\n\t\t\t.port_names[0]\t\u003d \"p9\",\n\t\t\t.port_names[1]\t\u003d \"p10\",\n\t\t\t.port_names[2]\t\u003d \"p11\",\n\t\t\t.port_names[3]\t\u003d \"p12\",\n\t\t\t.port_names[4]\t\u003d \"p13\",\n\t\t\t.port_names[5]\t\u003d \"p14\",\n\t\t\t.port_names[6]\t\u003d \"p15\",\n\t\t\t.port_names[7]\t\u003d \"p16\",\n\t\t\t.port_names[10]\t\u003d \"dsa\",\n\t\t\t.rtable\t\t\u003d (s8 []){ 10, -1, },\n\t\t},\n\t},\n\n\tstatic struct dsa_platform_data pd \u003d {\n\t\t.netdev\t\t\u003d \u0026foo,\n\t\t.nr_switches\t\u003d 2,\n\t\t.sw\t\t\u003d sw,\n\t};\n\nSigned-off-by: Lennert Buytenhek \u003cbuytenh@marvell.com\u003e\nTested-by: Gary Thomas \u003cgary@mlbassoc.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "396138f03f4521c55ecc3a5dd75d4c56e6323244", "tree": "61dc43e540c861a4b05753da56a9fe2a19bea206", "parents": [ "2e5f032095ff101274dfb03d5fd5e06d9aeb83cd" ], "author": { "name": "Lennert Buytenhek", "email": "buytenh@wantstofly.org", "time": "Tue Oct 07 13:46:07 2008 +0000" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Wed Oct 08 17:24:16 2008 -0700" }, "message": "dsa: add support for Trailer tagging format\n\nThis adds support for the Trailer switch tagging format. This is\nanother tagging that doesn\u0027t explicitly mark tagged packets with a\ndistinct ethertype, so that we need to add a similar hack in the\nreceive path as for the Original DSA tagging format.\n\nSigned-off-by: Lennert Buytenhek \u003cbuytenh@marvell.com\u003e\nTested-by: Byron Bradley \u003cbyron.bbradley@gmail.com\u003e\nTested-by: Tim Ellis \u003ctim.ellis@mac.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "cf85d08fdf4548ee46657ccfb7f9949a85145db5", "tree": "583e251b0d772c23ca931a207e9ac0995d679f44", "parents": [ "91da11f870f00a3322b81c73042291d7f0be5a17" ], "author": { "name": "Lennert Buytenhek", "email": "buytenh@wantstofly.org", "time": "Tue Oct 07 13:45:02 2008 +0000" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Wed Oct 08 17:19:56 2008 -0700" }, "message": "dsa: add support for original DSA tagging format\n\nMost of the DSA switches currently in the field do not support the\nEthertype DSA tagging format that one of the previous patches added\nsupport for, but only the original DSA tagging format.\n\nThe original DSA tagging format carries the same information as the\nEthertype DSA tagging format, but with the difference that it does not\nhave an ethertype field. In other words, when receiving a packet that\nis tagged with an original DSA tag, there is no way of telling in\neth_type_trans() that this packet is in fact a DSA-tagged packet.\n\nThis patch adds a hook into eth_type_trans() which is only compiled in\nif support for a switch chip that doesn\u0027t support Ethertype DSA is\nselected, and which checks whether there is a DSA switch driver\ninstance attached to this network device which uses the old tag format.\nIf so, it sets the protocol field to ETH_P_DSA without looking at the\npacket, so that the packet ends up in the right place.\n\nSigned-off-by: Lennert Buytenhek \u003cbuytenh@marvell.com\u003e\nTested-by: Nicolas Pitre \u003cnico@marvell.com\u003e\nTested-by: Peter van Valderen \u003clinux@ddcrew.com\u003e\nTested-by: Dirk Teurlings \u003cdirk@upexia.nl\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "91da11f870f00a3322b81c73042291d7f0be5a17", "tree": "670fedb54ee3c8fa403e9095f6d7e95ee560f346", "parents": [ "176eaa589b3d242f25f24e472883fcce5f196777" ], "author": { "name": "Lennert Buytenhek", "email": "buytenh@wantstofly.org", "time": "Tue Oct 07 13:44:02 2008 +0000" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Wed Oct 08 17:15:19 2008 -0700" }, "message": "net: Distributed Switch Architecture protocol support\n\nDistributed Switch Architecture is a protocol for managing hardware\nswitch chips. It consists of a set of MII management registers and\ncommands to configure the switch, and an ethernet header format to\nsignal which of the ports of the switch a packet was received from\nor is intended to be sent to.\n\nThe switches that this driver supports are typically embedded in\naccess points and routers, and a typical setup with a DSA switch\nlooks something like this:\n\n\t+-----------+ +-----------+\n\t| | RGMII | |\n\t| +-------+ +------ 1000baseT MDI (\"WAN\")\n\t| | | 6-port +------ 1000baseT MDI (\"LAN1\")\n\t| CPU | | ethernet +------ 1000baseT MDI (\"LAN2\")\n\t| |MIImgmt| switch +------ 1000baseT MDI (\"LAN3\")\n\t| +-------+ w/5 PHYs +------ 1000baseT MDI (\"LAN4\")\n\t| | | |\n\t+-----------+ +-----------+\n\nThe switch driver presents each port on the switch as a separate\nnetwork interface to Linux, polls the switch to maintain software\nlink state of those ports, forwards MII management interface\naccesses to those network interfaces (e.g. as done by ethtool) to\nthe switch, and exposes the switch\u0027s hardware statistics counters\nvia the appropriate Linux kernel interfaces.\n\nThis initial patch supports the MII management interface register\nlayout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and\nsupports the \"Ethertype DSA\" packet tagging format.\n\n(There is no officially registered ethertype for the Ethertype DSA\npacket format, so we just grab a random one. The ethertype to use\nis programmed into the switch, and the switch driver uses the value\nof ETH_P_EDSA for this, so this define can be changed at any time in\nthe future if the one we chose is allocated to another protocol or\nif Ethertype DSA gets its own officially registered ethertype, and\neverything will continue to work.)\n\nSigned-off-by: Lennert Buytenhek \u003cbuytenh@marvell.com\u003e\nTested-by: Nicolas Pitre \u003cnico@marvell.com\u003e\nTested-by: Byron Bradley \u003cbyron.bbradley@gmail.com\u003e\nTested-by: Tim Ellis \u003ctim.ellis@mac.com\u003e\nTested-by: Peter van Valderen \u003clinux@ddcrew.com\u003e\nTested-by: Dirk Teurlings \u003cdirk@upexia.nl\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" } ] }