)]}'
{
  "log": [
    {
      "commit": "f8f235e5bbf4e61f3e0886a44afb1dc4cfe8f337",
      "tree": "9211554f0542ce636aa1f14ffe58cfa832efa04d",
      "parents": [
        "93f5f7f1249e76a5e8afbdab53f90b10c41fdb61"
      ],
      "author": {
        "name": "Zhenyu Wang",
        "email": "zhenyuw@linux.intel.com",
        "time": "Fri Aug 27 11:08:57 2010 +0800"
      },
      "committer": {
        "name": "Chris Wilson",
        "email": "chris@chris-wilson.co.uk",
        "time": "Tue Sep 07 11:16:43 2010 +0100"
      },
      "message": "agp/intel: Fix cache control for Sandybridge\n\nSandybridge GTT has new cache control bits in PTE, which controls\ngraphics page cache in LLC or LLC/MLC, so we need to extend the mask\nfunction to respect the new bits.\n\nAnd set cache control to always LLC only by default on Gen6.\n\nSigned-off-by: Zhenyu Wang \u003czhenyuw@linux.intel.com\u003e\nCc: stable@kernel.org\nSigned-off-by: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\n"
    }
  ]
}