)]}'
{
  "log": [
    {
      "commit": "dbb0743a58825d94f1b3fdfa90a8d61dfef88f7b",
      "tree": "b7a69335b9480fae3c12380e94f22e8cfa197595",
      "parents": [
        "12ef65444de9d387a383b9991960848bed5bbe74"
      ],
      "author": {
        "name": "Adam Gruchala",
        "email": "adam.gruchala@intel.com",
        "time": "Wed Jun 01 22:31:03 2011 +0000"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sun Jul 03 04:04:50 2011 -0700"
      },
      "message": "isci: Added support for C0 to SCU Driver\n\nC0 silicon updates the pci revision id and requires new AFE parameters\nfor phy signal integrity.  Support for previous silicon revisions is\ndeprecated (it\u0027s also broken for the theoretical case of multiple\ncontrollers at different silicon revisions, all the more reason to get\nit removed as soon as possible)\n\nSigned-off-by: Adam Gruchala \u003cadam.gruchala@intel.com\u003e\n[fixed up deprecated silicon support]\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "f22be5d8386d9da67bfe02693806fbaff7b078da",
      "tree": "3cf2a4cbe871516d7eb1206852dc9b2a0ad00cfd",
      "parents": [
        "6cb4d6b382be6345c2d0c4b1b90dfdf9af32da7e"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Apr 19 15:29:25 2011 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sun Jul 03 04:00:37 2011 -0700"
      },
      "message": "isci: fix oem parameter header definition\n\nThe element_length is 2 bytes.\n\nReported-by: Yinghai Lu \u003cyinghai.lu@oracle.com\u003e\nAcked-by: Dave Jiang \u003cdave.jiang@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "4eefd2518aa04e1c69118252dc23e3444e694bc1",
      "tree": "5e901c31eb9d789586a3db32944a77f70e29e5c5",
      "parents": [
        "b5f18a201ed82ed3776c9950646689b93713ae57"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Fri Mar 25 09:58:15 2011 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sun Jul 03 03:58:14 2011 -0700"
      },
      "message": "isci: fix apc mode definition\n\nThe original apc mode definition is the correct one, the fix from commit\n4711ba10 \"isci: fix oem parameter initialization and mode detection\" was based\non a typo from a specification update.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "4711ba10b13891edf228944a9d0a21dfe7fe90f0",
      "tree": "c846eb029eb2bc827a614df963b00aa412b95956",
      "parents": [
        "2e8320f751030a12efc3e64ee857bfa4647f81fe"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Fri Mar 11 10:43:57 2011 -0800"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sun Jul 03 03:55:31 2011 -0700"
      },
      "message": "isci: fix oem parameter initialization and mode detection\n\n1/ Since commit 858d4aa7 \"isci: Move firmware loading to per PCI device\" we have\n   been silently falling back to built-in defaults for the parameter settings by\n   skipping the call to scic_oem_parameters_set().\n\n2/ The afe parameters from the firmware were not being honored\n\n3/ The latest oem parameter definition flips the mode_type values which are\n   now 0: for APC 1: for MPC.  For APC we need to make sure all the phys\n   default to the same address otherwise strict_wide_ports will cause duplicate\n   domains.\n\n4/ Fix up the driver announcement to indicate the source of the\n   parameters.\n\n5/ Fix up the sas addresses to be unique per controller (in the fallback case)\n\nSigned-off-by: Dave Jiang \u003cdave.jiang@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "07373a5caa29e4159ef1ea5e72985ddaf013519a",
      "tree": "0ea13c0ede1012dec6e6d491ed181418e62453ee",
      "parents": [
        "8db37aabaceb3dcd18754c1e782d4474e4052c81"
      ],
      "author": {
        "name": "Henryk Dembkowski",
        "email": "Henryk.Dembkowski@intel.com",
        "time": "Wed Feb 23 16:55:11 2011 -0800"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sun Jul 03 03:55:30 2011 -0700"
      },
      "message": "isci: add support for 2 more oem parmeters\n\n1/ add OEM paramater support for mode_type (MPC vs APC)\n2/ add OEM parameter support for max_number_concurrent_device_spin_up\n3/ cleanup scic_sds_controller_start_next_phy\n\ntodo: hook up the amp control afe parameters into the afe init code\n\nSigned-off-by: Henryk Dembkowski \u003chenryk.dembkowski@intel.com\u003e\nSigned-off-by: Jacek Danecki \u003cJacek.Danecki@intel.com\u003e\n[cleaned up scic_sds_controller_start_next_phy]\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "d044af17aacd03a1f4fced1af4b7570d205c8fd9",
      "tree": "1304fd0c7fa979fb229a4bf57771e9e6cde7b37d",
      "parents": [
        "9affa289e2f9ef4721e85edbde86466524bfe957"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Mar 08 09:52:49 2011 -0800"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sun Jul 03 03:55:30 2011 -0700"
      },
      "message": "isci: Add support for probing OROM for OEM params\n\nWe need to scan the OROM for signature and grab the OEM parameters. We\nalso need to do the same for EFI. If all fails then we resort to user\nbinary blob, and if that fails then we go to the defaults.\n\nShare the format with the create_fw utility so that all possible sources\nof the parameters are in-sync.\n\nSigned-off-by: Dave Jiang \u003cdave.jiang@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "6f231dda68080759f1aed3769896e94c73099f0f",
      "tree": "45b6ce02fa40e0e9c35526ac6c45950138387516",
      "parents": [
        "59c5f46fbe01a00eedf54a23789634438bb80603"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sat Jul 02 22:56:22 2011 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sat Jul 02 22:56:22 2011 -0700"
      },
      "message": "isci: Intel(R) C600 Series Chipset Storage Control Unit Driver\n\nSupport for the up to 2x4-port 6Gb/s SAS controllers embedded in the\nchipset.\n\nThis is a snapshot of the first publicly available version of the driver,\ncommit 4c1db2d0 in the \u0027historical\u0027 branch.\n\n   git://git.kernel.org/pub/scm/linux/kernel/git/djbw/isci.git historical\n\nSigned-off-by: Maciej Trela \u003cmaciej.trela@intel.com\u003e\nSigned-off-by: Dave Jiang \u003cdave.jiang@intel.com\u003e\nSigned-off-by: Edmund Nadolski \u003cedmund.nadolski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    }
  ]
}