)]}'
{
  "log": [
    {
      "commit": "885b976fada5bc6595a9fd3e67e3cb1a3d11f50b",
      "tree": "8b598bd3b265c0bbe8237e129410fdc80fe7847a",
      "parents": [
        "dd9c1549edef02290edced639f67b54a25abbe0e"
      ],
      "author": {
        "name": "Huang Ying",
        "email": "ying.huang@intel.com",
        "time": "Mon Feb 21 13:54:41 2011 +0800"
      },
      "committer": {
        "name": "Len Brown",
        "email": "len.brown@intel.com",
        "time": "Mon Mar 21 22:59:06 2011 -0400"
      },
      "message": "ACPI, APEI, Add ERST record ID cache\n\nAPEI ERST firmware interface and implementation has no multiple users\nin mind.  For example, if there is four records in storage with ID: 1,\n2, 3 and 4, if two ERST readers enumerate the records via\nGET_NEXT_RECORD_ID as follow,\n\nreader 1\t\treader 2\n1\n\t\t\t2\n3\n\t\t\t4\n-1\n\t\t\t-1\n\nwhere -1 signals there is no more record ID.\n\nReader 1 has no chance to check record 2 and 4, while reader 2 has no\nchance to check record 1 and 3.  And any other GET_NEXT_RECORD_ID will\nreturn -1, that is, other readers will has no chance to check any\nrecord even they are not cleared by anyone.\n\nThis makes raw GET_NEXT_RECORD_ID not suitable for used by multiple\nusers.\n\nTo solve the issue, an in-memory ERST record ID cache is designed and\nimplemented.  When enumerating record ID, the ID returned by\nGET_NEXT_RECORD_ID is added into cache in addition to be returned to\ncaller.  So other readers can check the cache to get all record ID\navailable.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nReviewed-by: Andi Kleen \u003cak@linux.intel.com\u003e\nSigned-off-by: Len Brown \u003clen.brown@intel.com\u003e\n"
    },
    {
      "commit": "415e12b2379239973feab91850b0dce985c6058a",
      "tree": "aa79c7a87fd30ac13ae3fd146aad5a44e854c4bc",
      "parents": [
        "6e8af08dfa40b747002207d3ce8e8b43a050d99f"
      ],
      "author": {
        "name": "Rafael J. Wysocki",
        "email": "rjw@sisk.pl",
        "time": "Fri Jan 07 00:55:09 2011 +0100"
      },
      "committer": {
        "name": "Jesse Barnes",
        "email": "jbarnes@virtuousgeek.org",
        "time": "Fri Jan 14 08:55:41 2011 -0800"
      },
      "message": "PCI/ACPI: Request _OSC control once for each root bridge (v3)\n\nMove the evaluation of acpi_pci_osc_control_set() (to request control of\nPCI Express native features) into acpi_pci_root_add() to avoid calling\nit many times for the same root complex with the same arguments.\nAdditionally, check if all of the requisite _OSC support bits are set\nbefore calling acpi_pci_osc_control_set() for a given root complex.\n\nReferences: https://bugzilla.kernel.org/show_bug.cgi?id\u003d20232\nReported-by: Ozan Caglayan \u003cozan@pardus.org.tr\u003e\nTested-by: Ozan Caglayan \u003cozan@pardus.org.tr\u003e\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n"
    },
    {
      "commit": "a08f82d08053fb6e3aa3635c2c26456d96337c8b",
      "tree": "ed68e8951610b66c6971cdb1fc446eb9e53e0422",
      "parents": [
        "d334a49113a4a33109fd24e46073280ecd1bea0d"
      ],
      "author": {
        "name": "Huang Ying",
        "email": "ying.huang@intel.com",
        "time": "Tue May 18 14:35:21 2010 +0800"
      },
      "committer": {
        "name": "Len Brown",
        "email": "len.brown@intel.com",
        "time": "Wed May 19 22:41:31 2010 -0400"
      },
      "message": "ACPI, APEI, Error Record Serialization Table (ERST) support\n\nERST is a way provided by APEI to save and retrieve hardware error\nrecord to and from some simple persistent storage (such as flash).\n\nThe Linux kernel support implementation is quite simple and workable\nin NMI context. So it can be used to save hardware error record into\nflash in hardware error exception or NMI handler, where other more\ncomplex persistent storage such as disk is not usable. After saving\nhardware error records via ERST in hardware error exception or NMI\nhandler, the error records can be retrieved and logged into disk or\nnetwork after a clean reboot.\n\nFor more information about ERST, please refer to ACPI Specification\nversion 4.0, section 17.4.\n\nThis patch incorporate fixes from Jin Dongming.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Andi Kleen \u003cak@linux.intel.com\u003e\nCC: Jin Dongming \u003cjin.dongming@np.css.fujitsu.com\u003e\nSigned-off-by: Len Brown \u003clen.brown@intel.com\u003e\n"
    },
    {
      "commit": "9dc966641677795f4d6b0a9ba630d6a3a3e24a57",
      "tree": "677dddf31719a2507b29d062e5b3359357296b37",
      "parents": [
        "a643ce207f3e70030bdb431e2a363cc111a60c1a"
      ],
      "author": {
        "name": "Huang Ying",
        "email": "ying.huang@intel.com",
        "time": "Tue May 18 14:35:13 2010 +0800"
      },
      "committer": {
        "name": "Len Brown",
        "email": "len.brown@intel.com",
        "time": "Wed May 19 22:35:06 2010 -0400"
      },
      "message": "ACPI, APEI, HEST table parsing\n\nHEST describes error sources in detail; communicating operational\nparameters (i.e. severity levels, masking bits, and threshold values)\nto OS as necessary. It also allows the platform to report error\nsources for which OS would typically not implement support (for\nexample, chipset-specific error registers).\n\nHEST information may be needed by other subsystems. For example, HEST\nPCIE AER error source information describes whether a PCIE root port\nworks in \"firmware first\" mode, this is needed by general PCIE AER\nerror subsystem. So a public HEST tabling parsing interface is\nprovided.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Andi Kleen \u003cak@linux.intel.com\u003e\nSigned-off-by: Len Brown \u003clen.brown@intel.com\u003e\n"
    }
  ]
}