)]}'
{
  "log": [
    {
      "commit": "659fb32d1b67476f4ade25e9ea0e2642a5b9c4b5",
      "tree": "a875904f1c457f321563060491956266a57c6514",
      "parents": [
        "d30e1521b2afb5e6f21ca8bc1a4b6ec2afc93597"
      ],
      "author": {
        "name": "Simon Guinot",
        "email": "sguinot@lacie.com",
        "time": "Wed Jul 06 12:41:31 2011 -0400"
      },
      "committer": {
        "name": "Arnd Bergmann",
        "email": "arnd@arndb.de",
        "time": "Thu Jul 07 16:02:26 2011 +0000"
      },
      "message": "genirq: replace irq_gc_ack() with {set,clr}_bit variants (fwd)\n\nThis fixes a regression introduced by e59347a \"arm: orion:\nUse generic irq chip\".\n\nDepending on the device, interrupts acknowledgement is done by setting\nor by clearing a dedicated register. Replace irq_gc_ack() with some\n{set,clr}_bit variants allows to handle both cases.\n\nNote that this patch affects the following SoCs: Davinci, Samsung and\nOrion. Except for this last, the change is minor: irq_gc_ack() is just\nrenamed into irq_gc_ack_set_bit().\n\nFor the Orion SoCs, the edge GPIO interrupts support is currently\nbroken. irq_gc_ack() try to acknowledge a such interrupt by setting\nthe corresponding cause register bit. The Orion GPIO device expect the\nopposite. To fix this issue, the irq_gc_ack_clr_bit() variant is used.\n\nTested on Network Space v2.\n\nReported-by: Joey Oravec \u003cjoravec@drewtech.com\u003e\nSigned-off-by: Simon Guinot \u003csguinot@lacie.com\u003e\nSigned-off-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n"
    },
    {
      "commit": "cfefd21e693dca791bf9ecfc9dd3794facad533c",
      "tree": "20915250e5c9749eea148cab17534b70c094386f",
      "parents": [
        "7d8280624797bbe2f5170bd3c85c75a8c9c74242"
      ],
      "author": {
        "name": "Thomas Gleixner",
        "email": "tglx@linutronix.de",
        "time": "Fri Apr 15 22:36:08 2011 +0200"
      },
      "committer": {
        "name": "Thomas Gleixner",
        "email": "tglx@linutronix.de",
        "time": "Sat Apr 23 15:56:24 2011 +0200"
      },
      "message": "genirq: Add chip suspend and resume callbacks\n\nThese callbacks are only called in the syscore suspend/resume code on\ninterrupt chips which have been registered via the generic irq chip\nmechanism. Calling those callbacks per irq would be rather icky, but\nwith the generic irq chip mechanism we can call this per registered\nchip.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: linux-arm-kernel@lists.infradead.org\n"
    },
    {
      "commit": "7d8280624797bbe2f5170bd3c85c75a8c9c74242",
      "tree": "8028581a9a51eeb3c168409b5645c68b7a32e7dd",
      "parents": [
        "7f1b1244e159a8490d7fb13667c6cb7e1e75046b"
      ],
      "author": {
        "name": "Thomas Gleixner",
        "email": "tglx@linutronix.de",
        "time": "Sun Apr 03 11:42:53 2011 +0200"
      },
      "committer": {
        "name": "Thomas Gleixner",
        "email": "tglx@linutronix.de",
        "time": "Sat Apr 23 15:56:24 2011 +0200"
      },
      "message": "genirq: Implement a generic interrupt chip\n\nImplement a generic interrupt chip, which is configurable and is able\nto handle the most common irq chip implementations.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: linux-arm-kernel@lists.infradead.org\nTested-by: H Hartley Sweeten \u003chsweeten@visionengravers.com\u003e\nTested-by: Tony Lindgren \u003ctony@atomide.com\u003e\nTested-by; Kevin Hilman \u003ckhilman@ti.com\u003e\n"
    }
  ]
}