)]}'
{
  "log": [
    {
      "commit": "8799ee9f49f6171fd58f4d64f8c067ca49006a5d",
      "tree": "b746b8800bc99633f31505d151624c8ccd75cd47",
      "parents": [
        "326764a85b7676388db3ebad6488f312631d7661"
      ],
      "author": {
        "name": "Russell King",
        "email": "rmk@dyn-67.arm.linux.org.uk",
        "time": "Thu Jun 29 18:24:21 2006 +0100"
      },
      "committer": {
        "name": "Russell King",
        "email": "rmk+kernel@arm.linux.org.uk",
        "time": "Thu Jun 29 18:24:21 2006 +0100"
      },
      "message": "[ARM] Set bit 4 on section mappings correctly depending on CPU\n\nOn some CPUs, bit 4 of section mappings means \"update the\ncache when written to\".  On others, this bit is required to\nbe one, and others it\u0027s required to be zero.  Finally, on\nARMv6 and above, setting it turns on \"no execute\" and prevents\nspeculative prefetches.\n\nWith all these combinations, no one value fits all CPUs, so we\nhave to pick a value depending on the CPU type, and the area\nwe\u0027re mapping.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n"
    },
    {
      "commit": "23759dc6430428897a36c4d493f611eca55c9481",
      "tree": "c62050927599b36ed223753c35fd737e3c0c6762",
      "parents": [
        "d3f4c571b6e596f9d39c596426269006a309d3b8"
      ],
      "author": {
        "name": "Lennert Buytenhek",
        "email": "buytenh@wantstofly.org",
        "time": "Sun Apr 02 00:07:39 2006 +0100"
      },
      "committer": {
        "name": "Russell King",
        "email": "rmk+kernel@arm.linux.org.uk",
        "time": "Sun Apr 02 00:07:39 2006 +0100"
      },
      "message": "[ARM] 3439/2: xsc3: add I/O coherency support\n\nPatch from Lennert Buytenhek\n\nThis patch adds support for the I/O coherent cache available on the\nxsc3.  The approach is to provide a simple API to determine whether the\nchipset supports coherency by calling arch_is_coherent() and then\nsetting the appropriate system memory PTE and PMD bits.  In addition,\nwe call this API on dma_alloc_coherent() and dma_map_single() calls.\nA generic version exists that will compile out all the coherency-related\ncode that is not needed on the majority of ARM systems.\n\nNote that we do not check for coherency in the dma_alloc_writecombine()\nfunction as that still requires a special PTE setting.  We also don\u0027t\ntouch dma_mmap_coherent() as that is a special ARM-only API that is by\ndefinition only used on non-coherent system.\n\nSigned-off-by: Deepak Saxena \u003cdsaxena@plexity.net\u003e\nSigned-off-by: Lennert Buytenhek \u003cbuytenh@wantstofly.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n"
    },
    {
      "commit": "74945c8616a50074277e18641baaae7464006766",
      "tree": "b74a005fd0c38b2582783378321bf324545f3346",
      "parents": [
        "0f44ba1d1e67201c0c58af26eb441fa7014c89ec"
      ],
      "author": {
        "name": "Russell King",
        "email": "rmk@dyn-67.arm.linux.org.uk",
        "time": "Thu Mar 16 14:44:36 2006 +0000"
      },
      "committer": {
        "name": "Russell King",
        "email": "rmk+kernel@arm.linux.org.uk",
        "time": "Tue Mar 21 22:03:25 2006 +0000"
      },
      "message": "[ARM] nommu: Move hardware page table definitions to pgtable-hwdef.h\n\nMove the hardware PMD and PTE page table definitions from pgtable.h\ninto pgtable-hwdef.h, and include pgtable-hwdef.h as necessary.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n"
    }
  ]
}