)]}'
{
  "log": [
    {
      "commit": "29440a2b4cd37e32dfe0fa60ef1665775b24dab1",
      "tree": "1b7bd1c1793feba0719f04de2eb68e418498e827",
      "parents": [
        "474f1a667d4bd40b6dcacc6870b70f4d2ba4e155"
      ],
      "author": {
        "name": "Bernd Schmidt",
        "email": "bernd.schmidt@analog.com",
        "time": "Thu Jul 12 16:25:29 2007 +0800"
      },
      "committer": {
        "name": "Bryan Wu",
        "email": "bryan.wu@analog.com",
        "time": "Thu Jul 12 16:25:29 2007 +0800"
      },
      "message": "Blackfin arch: Start untangling the CPLB handling code.\n\n - Move cache initialization to C from assembly.\n - Move anomaly workaround for writing [ID]MEM_CONTROL to assembly, so\n   that we don\u0027t have to mess around with .align directives in C source.\n - Fix a bug where bfin_write_DMEM_CONTROL would write to IMEM_CONTROL\n - Break out CPLB related code from kernel/setup.c into their own file.\n - Don\u0027t define variables in header files, only declare them.\n\nSigned-off-by: Bernd Schmidt \u003cbernd.schmidt@analog.com\u003e\nSigned-off-by: Bryan Wu \u003cbryan.wu@analog.com\u003e\n\n"
    },
    {
      "commit": "7adfb58fbd0a27469d26536f99b66391c4c8e2a0",
      "tree": "59e511ac2ddca77fe7c9d51bc6f6c6f0049a313b",
      "parents": [
        "0ba9e350a2c129ce2878d415cf51e88611cbc0e5"
      ],
      "author": {
        "name": "Bernd Schmidt",
        "email": "bernd.schmidt@analog.com",
        "time": "Thu Jun 21 11:34:16 2007 +0800"
      },
      "committer": {
        "name": "Bryan Wu",
        "email": "bryan.wu@analog.com",
        "time": "Thu Jun 21 11:34:16 2007 +0800"
      },
      "message": "Blackfin arch: defines and provides entry points for certain user space functions at fixed addresses\n\nThis patch defines (and provides) entry points for certain user space functions\nat fixed addresses.  The Blackfin has no usable atomic instructions, but we can\nensure that these code sequences appear atomic from a user space point of view\nby detecting when we\u0027re in the process of executing them during the interrupt\nhandler return path.  This allows much more efficient pthread lock\nimplementations than the bfin_spinlock syscall we\u0027re currently using.\n\nAlso provided is a small sys_rt_sigreturn stub which can be used by the signal\nhandler setup code.  The signal.c part will be committed separately.\n\nSigned-off-by: Bernd Schmidt \u003cbernd.schmidt@analog.com\u003e\nSigned-off-by: Bryan Wu \u003cbryan.wu@analog.com\u003e\n\n"
    },
    {
      "commit": "1394f03221790a988afc3e4b3cb79f2e477246a9",
      "tree": "2c1963c9a4f2d84a5e021307fde240c5d567cf70",
      "parents": [
        "73243284463a761e04d69d22c7516b2be7de096c"
      ],
      "author": {
        "name": "Bryan Wu",
        "email": "bryan.wu@analog.com",
        "time": "Sun May 06 14:50:22 2007 -0700"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@woody.linux-foundation.org",
        "time": "Mon May 07 12:12:58 2007 -0700"
      },
      "message": "blackfin architecture\n\nThis adds support for the Analog Devices Blackfin processor architecture, and\ncurrently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561\n(Dual Core) devices, with a variety of development platforms including those\navaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,\nBF561-EZKIT), and Bluetechnix!  Tinyboards.\n\nThe Blackfin architecture was jointly developed by Intel and Analog Devices\nInc.  (ADI) as the Micro Signal Architecture (MSA) core and introduced it in\nDecember of 2000.  Since then ADI has put this core into its Blackfin\nprocessor family of devices.  The Blackfin core has the advantages of a clean,\northogonal,RISC-like microprocessor instruction set.  It combines a dual-MAC\n(Multiply/Accumulate), state-of-the-art signal processing engine and\nsingle-instruction, multiple-data (SIMD) multimedia capabilities into a single\ninstruction-set architecture.\n\nThe Blackfin architecture, including the instruction set, is described by the\nADSP-BF53x/BF56x Blackfin Processor Programming Reference\nhttp://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf\n\nThe Blackfin processor is already supported by major releases of gcc, and\nthere are binary and source rpms/tarballs for many architectures at:\nhttp://blackfin.uclinux.org/gf/project/toolchain/frs There is complete\ndocumentation, including \"getting started\" guides available at:\nhttp://docs.blackfin.uclinux.org/ which provides links to the sources and\npatches you will need in order to set up a cross-compiling environment for\nbfin-linux-uclibc\n\nThis patch, as well as the other patches (toolchain, distribution,\nuClibc) are actively supported by Analog Devices Inc, at:\nhttp://blackfin.uclinux.org/\n\nWe have tested this on LTP, and our test plan (including pass/fails) can\nbe found at:\nhttp://docs.blackfin.uclinux.org/doku.php?id\u003dtesting_the_linux_kernel\n\n[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]\nSigned-off-by: Bryan Wu \u003cbryan.wu@analog.com\u003e\nSigned-off-by: Mariusz Kozlowski \u003cm.kozlowski@tuxland.pl\u003e\nSigned-off-by: Aubrey Li \u003caubrey.li@analog.com\u003e\nSigned-off-by: Jie Zhang \u003cjie.zhang@analog.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n"
    }
  ]
}