)]}' { "log": [ { "commit": "69f7c0a1be84b10a81b6edcce2dbee0cdec26eba", "tree": "a6d4988fda72595ea71ba7e2b4ac11f91fde0159", "parents": [ "759b9775c25f5e69aaea8a75c3914019e2dc5539" ], "author": { "name": "Con Kolivas", "email": "kernel@kolivas.org", "time": "Mon Mar 05 00:30:29 2007 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Mon Mar 05 07:57:51 2007 -0800" }, "message": "[PATCH] sched: remove SMT nice\n\nRemove the SMT-nice feature which idles sibling cpus on SMT cpus to\nfacilitiate nice working properly where cpu power is shared. The idling of\ncpus in the presence of runnable tasks is considered too fragile, easy to\nbreak with outside code, and the complexity of managing this system if an\narchitecture comes along with many logical cores sharing cpu power will be\nunworkable.\n\nRemove the associated per_cpu_gain variable in sched_domains used only by\nthis code.\n\nAlso:\n\n The reason is that with dynticks enabled, this code breaks without yet\n further tweaks so dynticks brought on the rapid demise of this code. So\n either we tweak this code or kill it off entirely. It was Ingo\u0027s preference\n to kill it off. Either way this needs to happen for 2.6.21 since dynticks\n has gone in.\n\nSigned-off-by: Con Kolivas \u003ckernel@kolivas.org\u003e\nAcked-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nCc: Nick Piggin \u003cnickpiggin@yahoo.com.au\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "08c183f31bdbb709f177f6d3110d5f288ea33933", "tree": "be7b84c07f3b0bf29473bad2b7b788fa189f948e", "parents": [ "1bd77f2da58e9cdd1f159217887343dadd9af417" ], "author": { "name": "Christoph Lameter", "email": "clameter@sgi.com", "time": "Sun Dec 10 02:20:29 2006 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.osdl.org", "time": "Sun Dec 10 09:55:43 2006 -0800" }, "message": "[PATCH] sched: add option to serialize load balancing\n\nLarge sched domains can be very expensive to scan. Add an option SD_SERIALIZE\nto the sched domain flags. If that flag is set then we make sure that no\nother such domain is being balanced.\n\n[akpm@osdl.org: build fix]\nSigned-off-by: Christoph Lameter \u003cclameter@sgi.com\u003e\nCc: Peter Williams \u003cpwil3058@bigpond.net.au\u003e\nCc: Nick Piggin \u003cnickpiggin@yahoo.com.au\u003e\nCc: Christoph Lameter \u003cclameter@sgi.com\u003e\nCc: \"Siddha, Suresh B\" \u003csuresh.b.siddha@intel.com\u003e\nCc: \"Chen, Kenneth W\" \u003ckenneth.w.chen@intel.com\u003e\nAcked-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nCc: KAMEZAWA Hiroyuki \u003ckamezawa.hiroyu@jp.fujitsu.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" }, { "commit": "1a84887080dc15f048db7c3a643e98f1435790d6", "tree": "7cd335fee247c0b60f8562c82806b49435b5fb9d", "parents": [ "74732646431a1bb7e23e6b564127a8881cfef900" ], "author": { "name": "Siddha, Suresh B", "email": "suresh.b.siddha@intel.com", "time": "Tue Oct 03 01:14:08 2006 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Tue Oct 03 08:04:06 2006 -0700" }, "message": "[PATCH] sched: introduce child field in sched_domain\n\nIntroduce the child field in sched_domain struct and use it in\nsched_balance_self().\n\nWe will also use this field in cleaning up the sched group cpu_power\nsetup(done in a different patch) code.\n\nSigned-off-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nAcked-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nAcked-by: Nick Piggin \u003cnickpiggin@yahoo.com.au\u003e\nCc: Paul Jackson \u003cpj@sgi.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" }, { "commit": "5c45bf279d378d436ce45825c0f136696c7b6109", "tree": "80e2fcf4866b84fccb787562e1a83b16f4bc8850", "parents": [ "369381694ddcf03f1de403501c8b97099b5109ec" ], "author": { "name": "Siddha, Suresh B", "email": "suresh.b.siddha@intel.com", "time": "Tue Jun 27 02:54:42 2006 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Tue Jun 27 17:32:45 2006 -0700" }, "message": "[PATCH] sched: mc/smt power savings sched policy\n\nsysfs entries \u0027sched_mc_power_savings\u0027 and \u0027sched_smt_power_savings\u0027 in\n/sys/devices/system/cpu/ control the MC/SMT power savings policy for the\nscheduler.\n\nBased on the values (1-enable, 0-disable) for these controls, sched groups\ncpu power will be determined for different domains. When power savings\npolicy is enabled and under light load conditions, scheduler will minimize\nthe physical packages/cpu cores carrying the load and thus conserving\npower(with a perf impact based on the workload characteristics... see OLS\n2005 CMP kernel scheduler paper for more details..)\n\nSigned-off-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nCc: Ingo Molnar \u003cmingo@elte.hu\u003e\nCc: Nick Piggin \u003cnickpiggin@yahoo.com.au\u003e\nCc: Con Kolivas \u003ckernel@kolivas.org\u003e\nCc: \"Chen, Kenneth W\" \u003ckenneth.w.chen@intel.com\u003e\nCc: \"David S. Miller\" \u003cdavem@davemloft.net\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" }, { "commit": "e5ecc192dfc5e0b325dd8c99ce4c755714c9acbf", "tree": "04b1d9d8936727a5b7dec4ee912b5509853cfec6", "parents": [ "a72391e42f0a13116995045b3d492d660f96697d" ], "author": { "name": "Christoph Lameter", "email": "clameter@sgi.com", "time": "Thu Apr 13 18:23:53 2006 -0700" }, "committer": { "name": "Tony Luck", "email": "tony.luck@intel.com", "time": "Fri Apr 21 10:57:40 2006 -0700" }, "message": "[IA64] Setup an IA64 specific reclaim distance\n\nRECLAIM_DISTANCE is checked on bootup against the SLIT table distances.\nZone reclaim is important for system that have higher latencies but not for\nsystems that have multiple nodes on one motherboard and therefore low latencies.\n\nWe found that on motherboard latencies are typically 1 to 1.4 of local memory\naccess speed whereas multinode systems which benefit from zone reclaim have\nusually more than 1.5 times the latency of a local access.\n\nSet the reclaim distance for IA64 to 1.5 times.\n\nSigned-off-by: Christoph Lameter \u003cclameter@sgi.com\u003e\nSigned-off-by: Tony Luck \u003ctony.luck@intel.com\u003e\n" }, { "commit": "69dcc99199fe29b0a29471a3488d39d9d33b25fc", "tree": "4232ad9a782dee6abfe7fa20c95a49249195de8f", "parents": [ "66ac5a294db70aa377c0d7bbdb0c4e3ef2349b7b" ], "author": { "name": "Zhang, Yanmin", "email": "yanmin.zhang@intel.com", "time": "Fri Feb 03 03:04:36 2006 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Fri Feb 03 08:32:09 2006 -0800" }, "message": "[PATCH] Export cpu topology in sysfs\n\nThe patch implements cpu topology exportation by sysfs.\n\nItems (attributes) are similar to /proc/cpuinfo.\n\n1) /sys/devices/system/cpu/cpuX/topology/physical_package_id:\n\trepresent the physical package id of cpu X;\n2) /sys/devices/system/cpu/cpuX/topology/core_id:\n\trepresent the cpu core id to cpu X;\n3) /sys/devices/system/cpu/cpuX/topology/thread_siblings:\n\trepresent the thread siblings to cpu X in the same core;\n4) /sys/devices/system/cpu/cpuX/topology/core_siblings:\n\trepresent the thread siblings to cpu X in the same physical package;\n\nTo implement it in an architecture-neutral way, a new source file,\ndriver/base/topology.c, is to export the 5 attributes.\n\nIf one architecture wants to support this feature, it just needs to\nimplement 4 defines, typically in file include/asm-XXX/topology.h.\nThe 4 defines are:\n#define topology_physical_package_id(cpu)\n#define topology_core_id(cpu)\n#define topology_thread_siblings(cpu)\n#define topology_core_siblings(cpu)\n\nThe type of **_id is int.\nThe type of siblings is cpumask_t.\n\nTo be consistent on all architectures, the 4 attributes should have\ndeafult values if their values are unavailable. Below is the rule.\n\n1) physical_package_id: If cpu has no physical package id, -1 is the\ndefault value.\n\n2) core_id: If cpu doesn\u0027t support multi-core, its core id is 0.\n\n3) thread_siblings: Just include itself, if the cpu doesn\u0027t support\nHT/multi-thread.\n\n4) core_siblings: Just include itself, if the cpu doesn\u0027t support\nmulti-core and HT/Multi-thread.\n\nSo be careful when declaring the 4 defines in include/asm-XXX/topology.h.\n\nIf an attribute isn\u0027t defined on an architecture, it won\u0027t be exported.\n\nThank Nathan, Greg, Andi, Paul and Venki.\n\nThe patch provides defines for i386/x86_64/ia64.\n\nSigned-off-by: Zhang, Yanmin \u003cyanmin.zhang@intel.com\u003e\nCc: Ingo Molnar \u003cmingo@elte.hu\u003e\nCc: Nick Piggin \u003cnickpiggin@yahoo.com.au\u003e\nCc: Greg KH \u003cgreg@kroah.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" }, { "commit": "8d08aed8d7714683b33666cc066e20f957dda01d", "tree": "31b8a773a09575f94adce8e00c52fb0010bd5a5f", "parents": [ "d171e519da635a82ab759cbfd46617ac160c9ec0" ], "author": { "name": "Jack Steiner", "email": "steiner@sgi.com", "time": "Tue Jan 17 15:42:46 2006 -0600" }, "committer": { "name": "Tony Luck", "email": "tony.luck@intel.com", "time": "Tue Jan 17 13:55:46 2006 -0800" }, "message": "[IA64] Zonelists for nodes without cpus\n\nIf a node runs out of memory, ensure that memory on nodes w/o cpus is used\nbefore using memory on nodes with cpus.\n\nSigned-off-by: Jack Steiner \u003csteiner@sgi.com\u003e\nSigned-off-by: Tony Luck \u003ctony.luck@intel.com\u003e\n" }, { "commit": "198e2f181163233b379dc7ce8a6d7516b84042e7", "tree": "cc4067ca1c81034ba8d214b7ff4c39f2f5be66ee", "parents": [ "4dc7a0bbeb6882ad665e588e82fabe5bb4645f2f" ], "author": { "name": "akpm@osdl.org", "email": "akpm@osdl.org", "time": "Thu Jan 12 01:05:30 2006 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Thu Jan 12 09:08:50 2006 -0800" }, "message": "[PATCH] scheduler cache-hot-autodetect\n\n\r)\n\nFrom: Ingo Molnar \u003cmingo@elte.hu\u003e\n\nThis is the latest version of the scheduler cache-hot-auto-tune patch.\n\nThe first problem was that detection time scaled with O(N^2), which is\nunacceptable on larger SMP and NUMA systems. To solve this:\n\n- I\u0027ve added a \u0027domain distance\u0027 function, which is used to cache\n measurement results. Each distance is only measured once. This means\n that e.g. on NUMA distances of 0, 1 and 2 might be measured, on HT\n distances 0 and 1, and on SMP distance 0 is measured. The code walks\n the domain tree to determine the distance, so it automatically follows\n whatever hierarchy an architecture sets up. This cuts down on the boot\n time significantly and removes the O(N^2) limit. The only assumption\n is that migration costs can be expressed as a function of domain\n distance - this covers the overwhelming majority of existing systems,\n and is a good guess even for more assymetric systems.\n\n [ People hacking systems that have assymetries that break this\n assumption (e.g. different CPU speeds) should experiment a bit with\n the cpu_distance() function. Adding a -\u003emigration_distance factor to\n the domain structure would be one possible solution - but lets first\n see the problem systems, if they exist at all. Lets not overdesign. ]\n\nAnother problem was that only a single cache-size was used for measuring\nthe cost of migration, and most architectures didnt set that variable\nup. Furthermore, a single cache-size does not fit NUMA hierarchies with\nL3 caches and does not fit HT setups, where different CPUs will often\nhave different \u0027effective cache sizes\u0027. To solve this problem:\n\n- Instead of relying on a single cache-size provided by the platform and\n sticking to it, the code now auto-detects the \u0027effective migration\n cost\u0027 between two measured CPUs, via iterating through a wide range of\n cachesizes. The code searches for the maximum migration cost, which\n occurs when the working set of the test-workload falls just below the\n \u0027effective cache size\u0027. I.e. real-life optimized search is done for\n the maximum migration cost, between two real CPUs.\n\n This, amongst other things, has the positive effect hat if e.g. two\n CPUs share a L2/L3 cache, a different (and accurate) migration cost\n will be found than between two CPUs on the same system that dont share\n any caches.\n\n(The reliable measurement of migration costs is tricky - see the source\nfor details.)\n\nFurthermore i\u0027ve added various boot-time options to override/tune\nmigration behavior.\n\nFirstly, there\u0027s a blanket override for autodetection:\n\n\tmigration_cost\u003d1000,2000,3000\n\nwill override the depth 0/1/2 values with 1msec/2msec/3msec values.\n\nSecondly, there\u0027s a global factor that can be used to increase (or\ndecrease) the autodetected values:\n\n\tmigration_factor\u003d120\n\nwill increase the autodetected values by 20%. This option is useful to\ntune things in a workload-dependent way - e.g. if a workload is\ncache-insensitive then CPU utilization can be maximized by specifying\nmigration_factor\u003d0.\n\nI\u0027ve tested the autodetection code quite extensively on x86, on 3\nP3/Xeon/2MB, and the autodetected values look pretty good:\n\nDual Celeron (128K L2 cache):\n\n ---------------------\n migration cost matrix (max_cache_size: 131072, cpu: 467 MHz):\n ---------------------\n [00] [01]\n [00]: - 1.7(1)\n [01]: 1.7(1) -\n ---------------------\n cacheflush times [2]: 0.0 (0) 1.7 (1784008)\n ---------------------\n\nHere the slow memory subsystem dominates system performance, and even\nthough caches are small, the migration cost is 1.7 msecs.\n\nDual HT P4 (512K L2 cache):\n\n ---------------------\n migration cost matrix (max_cache_size: 524288, cpu: 2379 MHz):\n ---------------------\n [00] [01] [02] [03]\n [00]: - 0.4(1) 0.0(0) 0.4(1)\n [01]: 0.4(1) - 0.4(1) 0.0(0)\n [02]: 0.0(0) 0.4(1) - 0.4(1)\n [03]: 0.4(1) 0.0(0) 0.4(1) -\n ---------------------\n cacheflush times [2]: 0.0 (33900) 0.4 (448514)\n ---------------------\n\nHere it can be seen that there is no migration cost between two HT\nsiblings (CPU#0/2 and CPU#1/3 are separate physical CPUs). A fast memory\nsystem makes inter-physical-CPU migration pretty cheap: 0.4 msecs.\n\n8-way P3/Xeon [2MB L2 cache]:\n\n ---------------------\n migration cost matrix (max_cache_size: 2097152, cpu: 700 MHz):\n ---------------------\n [00] [01] [02] [03] [04] [05] [06] [07]\n [00]: - 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1)\n [01]: 19.2(1) - 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1)\n [02]: 19.2(1) 19.2(1) - 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1)\n [03]: 19.2(1) 19.2(1) 19.2(1) - 19.2(1) 19.2(1) 19.2(1) 19.2(1)\n [04]: 19.2(1) 19.2(1) 19.2(1) 19.2(1) - 19.2(1) 19.2(1) 19.2(1)\n [05]: 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) - 19.2(1) 19.2(1)\n [06]: 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) - 19.2(1)\n [07]: 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) -\n ---------------------\n cacheflush times [2]: 0.0 (0) 19.2 (19281756)\n ---------------------\n\nThis one has huge caches and a relatively slow memory subsystem - so the\nmigration cost is 19 msecs.\n\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Ashok Raj \u003cashok.raj@intel.com\u003e\nSigned-off-by: Ken Chen \u003ckenneth.w.chen@intel.com\u003e\nCc: \u003cwilder@us.ibm.com\u003e\nSigned-off-by: John Hawkes \u003chawkes@sgi.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" }, { "commit": "c660439ba90aaaa056f68a5b0fc79f6b9e0506f5", "tree": "0139f623060027645a49f72729c4b1e6e7350248", "parents": [ "1224b375ed7982128602a3fa1da53eeeac1750b4" ], "author": { "name": "Ravikiran G Thirumalai", "email": "kiran@scalex86.org", "time": "Thu Dec 22 14:21:34 2005 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Sat Dec 24 12:30:22 2005 -0800" }, "message": "[PATCH] x86_64/ia64 : Fix compilation error for node_to_first_cpu\n\nFixes a compiler error in node_to_first_cpu, __ffs expects unsigned long as\na parameter; instead cpumask_t was being passed. The macro\nnode_to_first_cpu was not yet used in x86_64 and ia64 arches, and so we never\nhit this. This patch replaces __ffs with first_cpu macro, similar to other\narches.\n\nSigned-off-by: Alok N Kataria \u003calokk@calsoftinc.com\u003e\nSigned-off-by: Ravikiran G Thirumalai \u003ckiran@scalex86.org\u003e\nSigned-off-by: Shai Fultheim \u003cshai@scalex86.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" }, { "commit": "9c1cfda20a508b181bdda8c0045f7c0c333880a5", "tree": "eaa5b7ef7407316c36def26169574d0e37b1e60a", "parents": [ "ef08e3b4981aebf2ba9bd7025ef7210e8eec07ce" ], "author": { "name": "John Hawkes", "email": "hawkes@sgi.com", "time": "Tue Sep 06 15:18:14 2005 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Wed Sep 07 16:57:40 2005 -0700" }, "message": "[PATCH] cpusets: Move the ia64 domain setup code to the generic code\n\nSigned-off-by: John Hawkes \u003chawkes@sgi.com\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" }, { "commit": "514604c6d1779c55d3e97dc4e9a71c117c1ccbcd", "tree": "19241b4db64f1da60c0dd594606c5d5fba8b254f", "parents": [ "1604d9c8f8dffafe3a077dc5ae7c935d2318bcf6" ], "author": { "name": "Christoph Lameter", "email": "clameter@sgi.com", "time": "Thu Jul 07 16:59:00 2005 -0700" }, "committer": { "name": "Tony Luck", "email": "tony.luck@intel.com", "time": "Tue Jul 12 11:04:22 2005 -0700" }, "message": "[IA64] pcibus_to_node implementation for IA64\n\npcibus_to_node provides a way for the Linux kernel to identify to which\nnode a certain pcibus connects to. Allocations of control structures\nfor devices can then be made on the node where the pci bus is located\nto allow local access during interrupt and other device manipulation.\n\nThis patch provides a new \"node\" field in the the pci_controller\nstructure. The node field will be set based on ACPI information (thanks\nto Alex Williamson \u003calex.williamson@hp.com for that piece).\n\nSigned-off-by: Christoph Lameter \u003cclameter@sgi.com\u003e\nSigned-off-by: Tony Luck \u003ctony.luck@intel.com\u003e\n" }, { "commit": "687f1661d302bc70ce906594a6d3f615ef075a50", "tree": "2895a027851322c2badcd40acf6b871698f2962b", "parents": [ "68767a0ae428801649d510d9a65bb71feed44dd1" ], "author": { "name": "Nick Piggin", "email": "nickpiggin@yahoo.com.au", "time": "Sat Jun 25 14:57:21 2005 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@ppc970.osdl.org", "time": "Sat Jun 25 16:24:42 2005 -0700" }, "message": "[PATCH] sched: sched tuning\n\nDo some basic initial tuning.\n\nSigned-off-by: Nick Piggin \u003cnickpiggin@yahoo.com.au\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" }, { "commit": "1da177e4c3f41524e886b7f1b8a0c1fc7321cac2", "tree": "0bba044c4ce775e45a88a51686b5d9f90697ea9d", "parents": [], "author": { "name": "Linus Torvalds", "email": "torvalds@ppc970.osdl.org", "time": "Sat Apr 16 15:20:36 2005 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@ppc970.osdl.org", "time": "Sat Apr 16 15:20:36 2005 -0700" }, "message": "Linux-2.6.12-rc2\n\nInitial git repository build. I\u0027m not bothering with the full history,\neven though we have it. We can create a separate \"historical\" git\narchive of that later if we want to, and in the meantime it\u0027s about\n3.2GB when imported into git - space that would just make the early\ngit days unnecessarily complicated, when we don\u0027t have a lot of good\ninfrastructure for it.\n\nLet it rip!\n" } ] }