)]}' { "log": [ { "commit": "eb2d8d60327bec172ec80efbda94d0c492088204", "tree": "5c01deb8c251f8aa64cc3db2b95fd26f8ac285a6", "parents": [ "a650d3839e7a68321e5b76264398a63019b0928b" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sat Oct 13 21:42:46 2007 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sat Oct 13 21:53:15 2007 -0700" }, "message": "[SPARC64]: Access ivector_table[] using physical addresses.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "a650d3839e7a68321e5b76264398a63019b0928b", "tree": "e0500c57687c57bc22d0100b74485033a5738dbf", "parents": [ "d060db63fd38a8a75f666576ef9999c28cdc31cf" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Fri Oct 12 02:59:40 2007 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sat Oct 13 21:53:15 2007 -0700" }, "message": "[SPARC64]: Make IVEC pointers 64-bit.\n\nCurrently we chain IVEC entries using 32-bit \"pointers\"\nbecause we know that the ivector_table is in the main\nkernel image, thus below 4GB.\n\nThis uses proper 64-bit pointers instead.\n\nWhilst this bloats up the kernel image size, this sets\nthe infrastructure necessary to significantly shrink the\nkernel size by using physical addresses and dynamically\nallocating the ivector table.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "8b99cfb8cc51adae7f5294c8962a026c63100959", "tree": "349cebcae3eda608f1ed52fa3afcf661fca075a9", "parents": [ "27a2ef382c7935a4dd02bff9fd361ce118df98c6" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sat Jul 14 02:23:37 2007 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Jul 16 04:05:02 2007 -0700" }, "message": "[SPARC64]: More sensible udelay implementation.\n\nTake a page from the powerpc folks and just calculate the\ndelay factor directly.\n\nSince frequency scaling chips use a system-tick register,\nthe value is going to be the same system-wide.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "4f0234f4f9da485ecb9729af1b88567700fd4767", "tree": "7073115c86dbf4e691ddac12f5c9ce1c58ce53be", "parents": [ "b3e13fbeb9ac1eb8e7b0791bf56e1775c692972b" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Fri Jul 13 16:03:42 2007 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Jul 16 04:04:40 2007 -0700" }, "message": "[SPARC64]: Initial LDOM cpu hotplug support.\n\nOnly adding cpus is supports at the moment, removal\nwill come next.\n\nWhen new cpus are configured, the machine description is\nupdated. When we get the configure request we pass in a\ncpu mask of to-be-added cpus to the mdesc CPU node parser\nso it only fetches information for those cpus. That code\nalso proceeds to update the SMT/multi-core scheduling bitmaps.\n\ncpu_up() does all the work and we return the status back\nover the DS channel.\n\nCPUs via dr-cpu need to be booted straight out of the\nhypervisor, and this requires:\n\n1) A new trampoline mechanism. CPUs are booted straight\n out of the hypervisor with MMU disabled and running in\n physical addresses with no mappings installed in the TLB.\n\n The new hvtramp.S code sets up the critical cpu state,\n installs the locked TLB mappings for the kernel, and\n turns the MMU on. It then proceeds to follow the logic\n of the existing trampoline.S SMP cpu bringup code.\n\n2) All calls into OBP have to be disallowed when domaining\n is enabled. Since cpus boot straight into the kernel from\n the hypervisor, OBP has no state about that cpu and therefore\n cannot handle being invoked on that cpu.\n\n Luckily it\u0027s only a handful of interfaces which can be called\n after the OBP device tree is obtained. For example, rebooting,\n halting, powering-off, and setting options node variables.\n\nCPU removal support will require some infrastructure changes\nhere. Namely we\u0027ll have to process the requests via a true\nkernel thread instead of in a workqueue. workqueues run on\na per-cpu thread, but when unconfiguring we might need to\nforce the thread to execute on another cpu if the current cpu\nis the one being removed. Removal of a cpu also causes the kernel\nto destroy that cpu\u0027s workqueue running thread.\n\nAnother issue on removal is that we may have interrupts still\npointing to the cpu-to-be-removed. So new code will be needed\nto walk the active INO list and retarget those cpus as-needed.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "f78eae2e6f5d1eb05f76a45486286445b916bd92", "tree": "0fa81e104ad9891afcaf18cdcb413c4a0f2ee8da", "parents": [ "d887ab3a9b1899f88b8cfba531e726b5fb2ebd14" ], "author": { "name": "David S. Miller", "email": "davem@hutch.davemloft.net", "time": "Mon Jun 04 17:01:39 2007 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Jun 04 21:50:00 2007 -0700" }, "message": "[SPARC64]: Proper multi-core scheduling support.\n\nThe scheduling domain hierarchy is:\n\n all cpus --\u003e\n cpus that share an instruction cache --\u003e\n cpus that share an integer execution unit\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "22adb358e816ce6aa0afb231ae9d826b0bddc8b0", "tree": "6f9886bf5b4e5c916c72d8d5733211813873c5fc", "parents": [ "5cbc30737398b49f62ae8603129ce43ac7db1a41" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sat May 26 01:14:43 2007 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Tue May 29 02:49:49 2007 -0700" }, "message": "[SPARC64]: Eliminate NR_CPUS limitations.\n\nCheetah systems can have cpuids as large as 1023, although physical\nsystems don\u0027t have that many cpus.\n\nOnly three limitations existed in the kernel preventing arbitrary\nNR_CPUS values:\n\n1) dcache dirty cpu state stored in page-\u003eflags on\n D-cache aliasing platforms. With some build time\n calculations and some build-time BUG checks on\n page-\u003eflags layout, this one was easily solved.\n\n2) The cheetah XCALL delivery code could only handle\n a cpumask with up to 32 cpus set. Some simple looping\n logic clears that up too.\n\n3) thread_info-\u003ecpu was a u8, easily changed to a u16.\n\nThere are a few spots in the kernel that still put NR_CPUS\nsized arrays on the kernel stack, but that\u0027s not a sparc64\nspecific problem.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "5cbc30737398b49f62ae8603129ce43ac7db1a41", "tree": "45d01a686865e6fd9c32b670f77af1e37db03008", "parents": [ "e01c0d6d8cf29c1c11725837b265598cab687952" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Fri May 25 15:49:59 2007 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Tue May 29 02:49:41 2007 -0700" }, "message": "[SPARC64]: Use machine description and OBP properly for cpu probing.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "777a447529ad138f5fceb9c9ad28bab19848f277", "tree": "d6fa75027b26d0b2d436cb0f8dc97c72f411b970", "parents": [ "a58c9f3c1e929c3c323c26dbdafef46373a719d4" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Feb 22 06:24:10 2007 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Apr 26 01:54:11 2007 -0700" }, "message": "[SPARC64]: Unify timer interrupt handler.\n\nThings were scattered all over the place, split between\nSMP and non-SMP.\n\nUnify it all so that dyntick support is easier to add.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "fd0504c3217d6d1bc8f33f53fb536299cae8feda", "tree": "4379f5376358d1f54fc183f458614f289ed6d326", "parents": [ "3185d4d2873a46ca1620d784013f285522091aa0" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jun 20 01:20:00 2006 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jun 20 01:20:00 2006 -0700" }, "message": "[SPARC64]: Send all device interrupts via one PIL.\n\nThis is the first in a series of cleanups that will hopefully\nallow a seamless attempt at using the generic IRQ handling\ninfrastructure in the Linux kernel.\n\nDefine PIL_DEVICE_IRQ and vector all device interrupts through\nthere.\n\nGet rid of the ugly pil0_dummy_{bucket,desc}, instead vector\nthe timer interrupt directly to a specific handler since the\ntimer interrupt is the only event that will be signaled on\nPIL 14.\n\nThe irq_worklist is now in the per-cpu trap_block[].\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "dcc1e8dd88d4bc55e32a26dad7633d20ffe606d2", "tree": "a47592213d94f918867d3dd81bb91dac3e727dea", "parents": [ "14778d9072e53d2171f66ffd9657daff41acfaed" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Wed Mar 22 00:49:59 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Mar 22 01:15:14 2006 -0800" }, "message": "[SPARC64]: Add a secondary TSB for hugepage mappings.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "1bd0cd74d102a527b2a72907698d73fad4b82cbd", "tree": "2df2dede361dd259b6cd4b91c3ab8d5c783401ac", "parents": [ "8ca2557c48000daa8183b07d83f582a597705ebe" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Tue Feb 21 15:41:01 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:13:51 2006 -0800" }, "message": "[SPARC64]: Kill cpudata-\u003eidle_volume.\n\nSet, but never used.\n\nWe used to use this for dynamic IRQ retargetting, but that\ncode died a long time ago.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "ebd8c56c5ae154e2c6cfb7453a76a4e7265b2377", "tree": "155df85100a1316ac103dcaed140d20ddc72c855", "parents": [ "101d5c18a928ef82b6c7bf99a9eaa536b5ccf593" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Fri Feb 17 08:38:06 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:13:24 2006 -0800" }, "message": "[SPARC64]: Fix uniprocessor IRQ targetting on SUN4V.\n\nWe need to use the real hardware processor ID when\ntargetting interrupts, not the \"define to 0\" thing\nthe uniprocessor build gives us.\n\nAlso, fill in the Node-ID and Agent-ID fields properly\non sun4u/Safari.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "72aff53f1fe74153eccef303ab2f79de888d248c", "tree": "a229645be99274d36bed04bed355d74ec3c0baa2", "parents": [ "19a0d585e80e84b54bb9bf120bf0c826045dd3dd" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Fri Feb 17 01:29:17 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:13:22 2006 -0800" }, "message": "[SPARC64]: Get SUN4V SMP working.\n\nThe sibling cpu bringup is extremely fragile. We can only\nperform the most basic calls until we take over the trap\ntable from the firmware/hypervisor on the new cpu.\n\nThis means no accesses to %g4, %g5, %g6 since those can\u0027t be\nTLB translated without our trap handlers.\n\nIn order to achieve this:\n\n1) Change sun4v_init_mondo_queues() so that it can operate in\n several modes.\n\n It can allocate the queues, or install them in the current\n processor, or both.\n\n The boot cpu does both in it\u0027s call early on.\n\n Later, the boot cpu allocates the sibling cpu queue, starts\n the sibling cpu, then the sibling cpu loads them in.\n\n2) init_cur_cpu_trap() is changed to take the current_thread_info()\n as an argument instead of reading %g6 directly on the current\n cpu.\n\n3) Create a trampoline stack for the sibling cpus. We do our basic\n kernel calls using this stack, which is locked into the kernel\n image, then go to our proper thread stack after taking over the\n trap table.\n\n4) While we are in this delicate startup state, we put 0xdeadbeef\n into %g4/%g5/%g6 in order to catch accidental accesses.\n\n5) On the final prom_set_trap_table*() call, we put \u0026init_thread_union\n into %g6. This is a hack to make prom_world(0) work. All that\n wants to do is restore the %asi register using\n get_thread_current_ds().\n\nLonger term we should just do the OBP calls to set the trap table by\nhand just like we do for everything else. This would avoid that silly\nprom_world(0) issue, then we can remove the init_thread_union hack.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "12eaa328f9fb2d3fcb5afb682c762690d05a3cd8", "tree": "cce4e68b971757010a3e0bbf035fc65a381a3cd4", "parents": [ "18397944642cbca7fcd4a109b43ed5b4652e95b9" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Fri Feb 10 15:39:51 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:15 2006 -0800" }, "message": "[SPARC64]: Use ASI_SCRATCHPAD address 0x0 properly.\n\nThis is where the virtual address of the fault status\narea belongs.\n\nTo set it up we don\u0027t make a hypervisor call, instead\nwe call OBP\u0027s SUNW,set-trap-table with the real address\nof the fault status area as the second argument. And\nright before that call we write the virtual address into\nASI_SCRATCHPAD vaddr 0x0.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "1d2f1f90a1e004b0c1b8a73ed4394a93f09104b3", "tree": "2fcc0840b52218631020311d7b6d785e9a15db6a", "parents": [ "5b0c0572fcd6204675c5f7ddfa572b5017f817dd" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Feb 08 16:41:20 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:02 2006 -0800" }, "message": "[SPARC64]: Sun4v cross-call sending support.\n\nTechnically the hypervisor call supports sending in a list\nof all cpus to get the cross-call, but I only pass in one\ncpu at a time for now.\n\nThe multi-cpu support is there, just ifdef\u0027d out so it\u0027s easy to\nenable or delete it later.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "5b0c0572fcd6204675c5f7ddfa572b5017f817dd", "tree": "1075a61338e887bd6d4ecd4517646ef95dc09fbc", "parents": [ "ac29c11d4cd4fa1fac968e99998a956405732f2f" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Feb 08 02:53:50 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:01 2006 -0800" }, "message": "[SPARC64]: Sun4v interrupt handling.\n\nSun4v has 4 interrupt queues: cpu, device, resumable errors,\nand non-resumable errors. A set of head/tail offset pointers\nhelp maintain a work queue in physical memory. The entries\nare 64-bytes in size.\n\nEach queue is allocated then registered with the hypervisor\nas we bring cpus up.\n\nThe two error queues each get a kernel side buffer that we\nuse to quickly empty the main interrupt queue before we\ncall up to C code to log the event and possibly take evasive\naction.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "7202c55c5c57d2ad4611a751544c9368d7fba93a", "tree": "282219004791550b35f7de50d449d96f396be8f6", "parents": [ "3bfd6f3e77f58479ec53aa91d0b078abbb4c0868" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Tue Feb 07 22:53:56 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:58 2006 -0800" }, "message": "[SPARC64]: Add sun4v mondo queue bases to struct trap_per_cpu.\n\nAlso, correct TRAP_PER_CPU_FAULT_INFO define, it should be\n0x40 not 0x20.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "89a5264f065672a882f555228000614a6b2182b7", "tree": "4fa226fed4b8119096e50ff8c915d2c0f8d6cd6d", "parents": [ "8591e3027235d6d11b958e43379f2ee7b7114841" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Tue Feb 07 21:15:41 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:55 2006 -0800" }, "message": "[SPARC64]: asm/cpudata.h needs asm/asi.h\n\nFor the expansion of __GET_CPUID() on SMP.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "df7d6aec96ab98cb182dd5138a85bdc363a9bf0d", "tree": "d71808a328639a32b16c53b24ce8a6b641f43ad2", "parents": [ "d257d5da39a78b32721ca84b2ba7f461f2f7ed7f" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Tue Feb 07 00:00:16 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:53 2006 -0800" }, "message": "[SPARC64]: Rename gl_{1,2}insn_patch --\u003e sun4v_{1,2}insn_patch\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "d257d5da39a78b32721ca84b2ba7f461f2f7ed7f", "tree": "ac28d377688ebe13a4d38e05f4ff65ba73d8652a", "parents": [ "840aaef8db32572b6d11e0d5cb5e6efcbc812000" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Feb 06 23:44:37 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:52 2006 -0800" }, "message": "[SPARC64]: Initial sun4v TLB miss handling infrastructure.\n\nThings are a little tricky because, unlike sun4u, we have\nto:\n\n1) do a hypervisor trap to do the TLB load.\n2) do the TSB lookup calculations by hand\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "45fec05f805a113372c9a7ff4c653ac749f6921c", "tree": "36fc99d10656775acb8e9442719447d64ac30a03", "parents": [ "314981ac7177a933319e3c071a5cf0a579205e6e" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sun Feb 05 22:27:28 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:50 2006 -0800" }, "message": "[SPARC64]: Sanitize %pstate writes for sun4v.\n\nIf we\u0027re just switching between different alternate global\nsets, nop it out on sun4v. Also, get rid of all of the\nalternate global save/restore in the OBP CIF trampoline code.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "936f482af1743141d637483ec10eb881537c26dc", "tree": "913da89a4d9f4038c510c9ecf2f5957b0f6d167f", "parents": [ "6e02493a7f33ac89e698b980a657d77ab2749eaf" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sun Feb 05 21:29:28 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:48 2006 -0800" }, "message": "[SPARC64]: Add initial code to twiddle %gl on trap entry/exit.\n\nInstead of setting/clearing PSTATE_AG we have to change\nthe %gl register value on sun4v.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "d96b81533ba3d5775e45aee6986b2aa33c10801c", "tree": "334af39452d650cc14b389c58a30cc54e9e130dd", "parents": [ "e1c21c4f476f2270c98aad1fe55e5f33e25f77f5" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sat Feb 04 15:40:53 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:45 2006 -0800" }, "message": "[SPARC64]: Add sun4v case to __GET_CPUID() patch tables.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "ffe483d55229fadbaf4cc7316d47024a24ecd1a2", "tree": "70bdb6c94d5b3512a7b2a3ff06979ac2e4e869bf", "parents": [ "92704a1c63c3b481870d02636d0b5a70c7e21cd1" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Feb 02 21:55:10 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:35 2006 -0800" }, "message": "[SPARC64]: Add explicit register args to trap state loading macros.\n\nThis, as well as making the code cleaner, allows a simplification in\nthe TSB miss handling path.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "92704a1c63c3b481870d02636d0b5a70c7e21cd1", "tree": "098f96da6ab50a1d878425e2b91a9cf22f78ac80", "parents": [ "f4e841da30b4bcbb8f1cc20a01157a788ff58b21" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sun Feb 26 23:27:19 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:35 2006 -0800" }, "message": "[SPARC64]: Refine code sequences to get the cpu id.\n\nOn uniprocessor, it\u0027s always zero for optimize that.\n\nOn SMP, the jmpl to the stub kills the return address stack in the cpu\nbranch prediction logic, so expand the code sequence inline and use a\ncode patching section to fix things up. This also always better and\nexplicit register selection, which will be taken advantage of in a\nfuture changeset.\n\nThe hard_smp_processor_id() function is big, so do not inline it.\n\nFix up tests for Jalapeno to also test for Serrano chips too. These\ntests want \"jbus Ultra-IIIi\" cases to match, so that is what we should\ntest for.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "86b818687d4894063ecd1190e54717a0cce8c009", "tree": "d2951295358502c88f7fe0c02517d729cff4eb9a", "parents": [ "9954863975910a1b9372b7d5006a6cba43bdd288" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jan 31 18:34:51 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:29 2006 -0800" }, "message": "[SPARC64]: Fix race in LOAD_PER_CPU_BASE()\n\nSince we use %g5 itself as a temporary, it can get clobbered\nif we take an interrupt mid-stream and thus cause end up with\nthe final %g5 value too early as a result of rtrap processing.\n\nSet %g5 at the very end, atomically, to avoid this problem.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "a8b900d801697609d1b56cc9c110148c64678068", "tree": "47602480aba29d17f8a79cc76dfe8af4d62f2599", "parents": [ "3487d1d4414fbfab5d98ec559e6f84f55520cb15" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jan 31 18:33:37 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:25 2006 -0800" }, "message": "[SPARC64]: Kill sole argument passed to setup_tba().\n\nNo longer used, and move extern declaration to a header file.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "56fb4df6da76c35dca22036174e2d1edef83ff1f", "tree": "b39f152ec9ed682edceca965a85680fd4bf736a7", "parents": [ "3c936465249f863f322154ff1aaa628b84ee5750" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sun Feb 26 23:24:22 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:16 2006 -0800" }, "message": "[SPARC64]: Elminate all usage of hard-coded trap globals.\n\nUltraSPARC has special sets of global registers which are switched to\nfor certain trap types. There is one set for MMU related traps, one\nset of Interrupt Vector processing, and another set (called the\nAlternate globals) for all other trap types.\n\nFor what seems like forever we\u0027ve hard coded the values in some of\nthese trap registers. Some examples include:\n\n1) Interrupt Vector global %g6 holds current processors interrupt\n work struct where received interrupts are managed for IRQ handler\n dispatch.\n\n2) MMU global %g7 holds the base of the page tables of the currently\n active address space.\n\n3) Alternate global %g6 held the current_thread_info() value.\n\nSuch hardcoding has resulted in some serious issues in many areas.\nThere are some code sequences where having another register available\nwould help clean up the implementation. Taking traps such as\ncross-calls from the OBP firmware requires some trick code sequences\nwherein we have to save away and restore all of the special sets of\nglobal registers when we enter/exit OBP.\n\nWe were also using the IMMU TSB register on SMP to hold the per-cpu\narea base address, which doesn\u0027t work any longer now that we actually\nuse the TSB facility of the cpu.\n\nThe implementation is pretty straight forward. One tricky bit is\ngetting the current processor ID as that is different on different cpu\nvariants. We use a stub with a fancy calling convention which we\npatch at boot time. The calling convention is that the stub is\nbranched to and the (PC - 4) to return to is in register %g1. The cpu\nnumber is left in %g6. This stub can be invoked by using the\n__GET_CPUID macro.\n\nWe use an array of per-cpu trap state to store the current thread and\nphysical address of the current address space\u0027s page tables. The\nTRAP_LOAD_THREAD_REG loads %g6 with the current thread from this\ntable, it uses __GET_CPUID and also clobbers %g1.\n\nTRAP_LOAD_IRQ_WORK is used by the interrupt vector processing to load\nthe current processor\u0027s IRQ software state into %g6. It also uses\n__GET_CPUID and clobbers %g1.\n\nFinally, TRAP_LOAD_PGD_PHYS loads the physical address base of the\ncurrent address space\u0027s page tables into %g7, it clobbers %g1 and uses\n__GET_CPUID.\n\nMany refinements are possible, as well as some tuning, with this stuff\nin place.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "3c936465249f863f322154ff1aaa628b84ee5750", "tree": "2bd7a229236f197d20a655133370e5d0c1bf886c", "parents": [ "05e28f9de65a38bb0c769080e91b6976e7e1e70c" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jan 31 18:30:27 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:14 2006 -0800" }, "message": "[SPARC64]: Kill pgtable quicklists and use SLAB.\n\nTaking a nod from the powerpc port.\n\nWith the per-cpu caching of both the page allocator and SLAB, the\npgtable quicklist scheme becomes relatively silly and primitive.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "05e28f9de65a38bb0c769080e91b6976e7e1e70c", "tree": "e1d3fcc1381ea6612ce4c082ca8596e84b637216", "parents": [ "74bf4312fff083ab25c3f357cc653ada7995e5f6" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jan 31 18:30:13 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:13 2006 -0800" }, "message": "[SPARC64]: No need to D-cache color page tables any longer.\n\nUnlike the virtual page tables, the new TSB scheme does not\nrequire this ugly hack.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "80dc0d6b44ce0f01df58d8899e46612690ed7d81", "tree": "570b8e834c0fae0793bdf75dd2fd2516b0fabf4f", "parents": [ "56425306517ef28a9b480161cdb96d182172bc1d" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Sep 26 00:32:17 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Sep 26 00:32:17 2005 -0700" }, "message": "[SPARC64]: Probe D/I/E-cache config and use.\n\nAt boot time, determine the D-cache, I-cache and E-cache size and\nline-size. Use them in cache flushes when appropriate.\n\nThis change was motivated by discovering that the D-cache on\nUltraSparc-IIIi and later are 64K not 32K, and the flushes done by the\nCheetah error handlers were assuming a 32K size.\n\nThere are still some pieces of code that are hard coding things and\nwill need to be fixed up at some point.\n\nWhile we\u0027re here, fix the D-cache and I-cache parity error handlers\nto run with interrupts disabled, and when the trap occurs at trap\nlevel \u003e 1 log the event via a counter displayed in /proc/cpuinfo.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "d7ce78fd9a51ca0d6b9a8cf35baef884ddb9a95c", "tree": "d7103663f1b5262d7a90f9d99e0c2af611ad07c9", "parents": [ "826509f8110049663799bc20f2b5b6170e2f78ca" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Mon Aug 29 22:46:43 2005 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Mon Aug 29 22:46:43 2005 -0700" }, "message": "[SPARC64]: Eliminate irq_cpustat_t.\n\nWe can put the __softirq_pending mask in the cpudata,\nno need for the silly NR_CPUS array in kernel/softirq.c\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "1da177e4c3f41524e886b7f1b8a0c1fc7321cac2", "tree": "0bba044c4ce775e45a88a51686b5d9f90697ea9d", "parents": [], "author": { "name": "Linus Torvalds", "email": "torvalds@ppc970.osdl.org", "time": "Sat Apr 16 15:20:36 2005 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@ppc970.osdl.org", "time": "Sat Apr 16 15:20:36 2005 -0700" }, "message": "Linux-2.6.12-rc2\n\nInitial git repository build. I\u0027m not bothering with the full history,\neven though we have it. We can create a separate \"historical\" git\narchive of that later if we want to, and in the meantime it\u0027s about\n3.2GB when imported into git - space that would just make the early\ngit days unnecessarily complicated, when we don\u0027t have a lot of good\ninfrastructure for it.\n\nLet it rip!\n" } ] }