)]}' { "log": [ { "commit": "2d9e2763c22a4ce41c3cc5f35366a51f1eba38dc", "tree": "5a8ee71858b3ec58ff07a2cd9cf875cfb458cf63", "parents": [ "5f81941c9d47f783e834028dcfb8548809da5a53" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Tue May 29 01:58:31 2007 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Tue May 29 02:51:38 2007 -0700" }, "message": "[SPARC64]: Fix two bugs wrt. kernel 4MB TSB.\n\n1) The TSB lookup was not using the correct hash mask.\n\n2) It was not aligned on a boundary equal to it\u0027s size,\n which is required by the sun4v Hypervisor.\n\nwasn\u0027t having it\u0027s return value checked, and that bug will be fixed up\nas well in a subsequent changeset.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "d1acb4210aaa9bdc413d276dbc96d0a23ada97ba", "tree": "b0ca2efd2b34e319aeb09c451d89fd1c9dc47ba3", "parents": [ "db98e0b434a6265c451ffe94ec0a29b8d0aaf587" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Fri Mar 16 17:20:28 2007 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Fri Mar 16 17:20:28 2007 -0700" }, "message": "[SPARC64]: Get DEBUG_PAGEALLOC working again.\n\nWe have to make sure to use base-pagesize TLB entries even during the\nearly transition period where we need TLB miss handling but don\u0027t have\nthe kernel page tables setup yet for the linear region.\n\nAlso, it is necessary therefore to not use the 4MB TSB for these\ntranslations, and instead use the normal kernel TSB. This allows us\nto also get rid of the 4MB tsb for debug builds which shrinks the\nkernel a little bit.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "d7744a09504d5ae84edc8289a02254e1f2102410", "tree": "be0f245ee0725f2f066bf87d17d254ce1e7279bf", "parents": [ "9cc3a1ac9a819cadff05ca37bb7f208013a22035" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Feb 21 22:31:11 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:13:56 2006 -0800" }, "message": "[SPARC64]: Create a seperate kernel TSB for 4MB/256MB mappings.\n\nIt can map all of the linear kernel mappings with zero TSB hash\nconflicts for systems with 16GB or less ram. In such cases, on\nSUN4V, once we load up this TSB the first time with all the\nmappings, we never take a linear kernel mapping TLB miss ever\nagain, the hypervisor handles them all.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "8b234274418d6d79527c4ac3a72da446ca4cb35f", "tree": "ab4ab14fa7f1cab7889ecc2339f0261253a5d0e1", "parents": [ "7adb37fe80d06cbd40de9b225b12a3a9ec40b6bb" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Fri Feb 17 18:01:02 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:13:34 2006 -0800" }, "message": "[SPARC64]: More TLB/TSB handling fixes.\n\nThe SUN4V convention with non-shared TSBs is that the context\nbit of the TAG is clear. So we have to choose an \"invalid\"\nbit and initialize new TSBs appropriately. Otherwise a zero\nTAG looks \"valid\".\n\nMake sure, for the window fixup cases, that we use the right\nglobal registers and that we don\u0027t potentially trample on\nthe live global registers in etrap/rtrap handling (%g2 and\n%g6) and that we put the missing virtual address properly\nin %g5.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "d257d5da39a78b32721ca84b2ba7f461f2f7ed7f", "tree": "ac28d377688ebe13a4d38e05f4ff65ba73d8652a", "parents": [ "840aaef8db32572b6d11e0d5cb5e6efcbc812000" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Feb 06 23:44:37 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:52 2006 -0800" }, "message": "[SPARC64]: Initial sun4v TLB miss handling infrastructure.\n\nThings are a little tricky because, unlike sun4u, we have\nto:\n\n1) do a hypervisor trap to do the TLB load.\n2) do the TSB lookup calculations by hand\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "517af33237ecfc3c8a93b335365fa61e741ceca4", "tree": "58eff40eb4c517c4fd49fd347d38273ee1e1ee4b", "parents": [ "b0fd4e49aea8a460afab7bc67cd618e2d19291d4" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Feb 01 15:55:21 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:32 2006 -0800" }, "message": "[SPARC64]: Access TSB with physical addresses when possible.\n\nThis way we don\u0027t need to lock the TSB into the TLB.\nThe trick is that every TSB load/store is registered into\na special instruction patch section. The default uses\nvirtual addresses, and the patch instructions use physical\naddress load/stores.\n\nWe can\u0027t do this on all chips because only cheetah+ and later\nhave the physical variant of the atomic quad load.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "b0fd4e49aea8a460afab7bc67cd618e2d19291d4", "tree": "a596c793cbc918bdcea462bcfe2f2f41fe8afeb2", "parents": [ "30a6ecad9670d97c9d0fbfa7d80970aeb339bdec" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Tue Jan 31 23:13:29 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:31 2006 -0800" }, "message": "[SPARC64]: Kill out-of-date commentary in asm-sparc64/tsb.h\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "2f7ee7c63f08b7f883b710a29d91c1891b81b8e1", "tree": "c0539482cecfd3cbc0b983a23058315811dc8b55", "parents": [ "a8b900d801697609d1b56cc9c110148c64678068" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jan 31 18:33:49 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:26 2006 -0800" }, "message": "[SPARC64]: Increase swapper_tsb size to 32K.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "4753eb2ac7022b999e5e484f1a5dc001dba22bd3", "tree": "138321ebd3b3c3aeb99517ec5158a65f556da774", "parents": [ "96c6e0d8e2a0eb1338751598be47fa1ffed91704" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jan 31 18:32:44 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:21 2006 -0800" }, "message": "[SPARC64]: Fix incorrect TSB lock bit handling.\n\nThe TSB_LOCK_BIT define is actually a special\nvalue shifted down by 32-bits for the assembler\ncode macros.\n\nIn C code, this isn\u0027t what we want.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "98c5584cfc47932c4f3ccf5eee2e0bae1447b85e", "tree": "c067ac8bfc081bbe0b3073374cb15708458e04ab", "parents": [ "09f94287f7260e03bbeab497e743691fafcc22c3" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jan 31 18:31:20 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:17 2006 -0800" }, "message": "[SPARC64]: Add infrastructure for dynamic TSB sizing.\n\nThis also cleans up tsb_context_switch(). The assembler\nroutine is now __tsb_context_switch() and the former is\nan inline function that picks out the bits from the mm_struct\nand passes it into the assembler code as arguments.\n\nsetup_tsb_parms() computes the locked TLB entry to map the\nTSB. Later when we support using the physical address quad\nload instructions of Cheetah+ and later, we\u0027ll simply use\nthe physical address for the TSB register value and set\nthe map virtual and PTE both to zero.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "74bf4312fff083ab25c3f357cc653ada7995e5f6", "tree": "c23dea461e32485f4cd7ca4b8c33c632655eb906", "parents": [ "30d4d1ffed7098afe2641536d67eef150499da02" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jan 31 18:29:18 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:13 2006 -0800" }, "message": "[SPARC64]: Move away from virtual page tables, part 1.\n\nWe now use the TSB hardware assist features of the UltraSPARC\nMMUs.\n\nSMP is currently knowingly broken, we need to find another place\nto store the per-cpu base pointers. We hid them away in the TSB\nbase register, and that obviously will not work any more :-)\n\nAnother known broken case is non-8KB base page size.\n\nAlso noticed that flush_tlb_all() is not referenced anywhere, only\nthe internal __flush_tlb_all() (local cpu only) is used by the\nsparc64 port, so we can get rid of flush_tlb_all().\n\nThe kernel gets it\u0027s own 8KB TSB (swapper_tsb) and each address space\ngets it\u0027s own private 8K TSB. Later we can add code to dynamically\nincrease the size of per-process TSB as the RSS grows. An 8KB TSB is\ngood enough for up to about a 4MB RSS, after which the TSB starts to\nincur many capacity and conflict misses.\n\nWe even accumulate OBP translations into the kernel TSB.\n\nAnother area for refinement is large page size support. We could use\na secondary address space TSB to handle those.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" } ] }