)]}' { "log": [ { "commit": "777a447529ad138f5fceb9c9ad28bab19848f277", "tree": "d6fa75027b26d0b2d436cb0f8dc97c72f411b970", "parents": [ "a58c9f3c1e929c3c323c26dbdafef46373a719d4" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Feb 22 06:24:10 2007 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Apr 26 01:54:11 2007 -0700" }, "message": "[SPARC64]: Unify timer interrupt handler.\n\nThings were scattered all over the place, split between\nSMP and non-SMP.\n\nUnify it all so that dyntick support is easier to add.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "10e267234cc0133bc9ed26bc34eb09de90c248c0", "tree": "8493e2767e1752f5873e50cc899a4c701cc55fbb", "parents": [ "af1713e0f111647052953ba12fd10a59c74a5dde" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Thu Nov 16 13:38:57 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sun Dec 10 02:39:09 2006 -0800" }, "message": "[SPARC64]: Add irqtrace/stacktrace/lockdep support.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "62c4f0a2d5a188f73a94f2cb8ea0dba3e7cf0a7f", "tree": "e85ca2d0dd43f90dccf758338764c3caa55f333f", "parents": [ "089f26d5e31b7bf42a9a8fefec08b30cd27f4b0e" ], "author": { "name": "David Woodhouse", "email": "dwmw2@infradead.org", "time": "Wed Apr 26 12:56:16 2006 +0100" }, "committer": { "name": "David Woodhouse", "email": "dwmw2@infradead.org", "time": "Wed Apr 26 12:56:16 2006 +0100" }, "message": "Don\u0027t include linux/config.h from anywhere else in include/\n\nSigned-off-by: David Woodhouse \u003cdwmw2@infradead.org\u003e\n" }, { "commit": "8b234274418d6d79527c4ac3a72da446ca4cb35f", "tree": "ab4ab14fa7f1cab7889ecc2339f0261253a5d0e1", "parents": [ "7adb37fe80d06cbd40de9b225b12a3a9ec40b6bb" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Fri Feb 17 18:01:02 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:13:34 2006 -0800" }, "message": "[SPARC64]: More TLB/TSB handling fixes.\n\nThe SUN4V convention with non-shared TSBs is that the context\nbit of the TAG is clear. So we have to choose an \"invalid\"\nbit and initialize new TSBs appropriately. Otherwise a zero\nTAG looks \"valid\".\n\nMake sure, for the window fixup cases, that we use the right\nglobal registers and that we don\u0027t potentially trample on\nthe live global registers in etrap/rtrap handling (%g2 and\n%g6) and that we put the missing virtual address properly\nin %g5.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "459b6e621e0e15315c25bac47fa7113e5818d45d", "tree": "4bbff0ec1dafb7fba8b247c84ad708f54cc687fe", "parents": [ "fd05068d7b22b64211f9202aa67ad44b51d44242" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sat Feb 11 12:21:20 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:23 2006 -0800" }, "message": "[SPARC64]: Fix some SUN4V TLB miss bugs.\n\nCode patching did not sign extend negative branch\noffsets correctly.\n\nKernel TLB miss path needs patching and %g4 register\npreservation in order to handle SUN4V correctly.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "12eaa328f9fb2d3fcb5afb682c762690d05a3cd8", "tree": "cce4e68b971757010a3e0bbf035fc65a381a3cd4", "parents": [ "18397944642cbca7fcd4a109b43ed5b4652e95b9" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Fri Feb 10 15:39:51 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:15 2006 -0800" }, "message": "[SPARC64]: Use ASI_SCRATCHPAD address 0x0 properly.\n\nThis is where the virtual address of the fault status\narea belongs.\n\nTo set it up we don\u0027t make a hypervisor call, instead\nwe call OBP\u0027s SUNW,set-trap-table with the real address\nof the fault status area as the second argument. And\nright before that call we write the virtual address into\nASI_SCRATCHPAD vaddr 0x0.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "aa9143b9719c07fb6f1f6207790c9c5086ae07e7", "tree": "74d56ecc53ed0542f200d6c6257c8f051095111c", "parents": [ "12816ab38adddc9d7e9b3315d1739655dedc7c9f" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Feb 09 16:12:22 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:05 2006 -0800" }, "message": "[SPARC64]: Implement sun4v TSB miss handlers.\n\nWhen we register a TSB with the hypervisor, so that it or hardware can\nhandle TLB misses and do the TSB walk for us, the hypervisor traps\ndown to these trap when it incurs a TSB miss.\n\nProcessing is simple, we load the missing virtual address and context,\nand do a full page table walk.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "314ef6859750b6539eac48d78059bb7986f29cb1", "tree": "26c7da386349c1cf377225356e1012ae62da6f07", "parents": [ "ffe483d55229fadbaf4cc7316d47024a24ecd1a2" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sat Feb 04 00:10:01 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:36 2006 -0800" }, "message": "[SPARC64]: Refine register window trap handling.\n\nWhen saving and restoing trap state, do the window spill/fill\nhandling inline so that we never trap deeper than 2 trap levels.\nThis is important for chips like Niagara.\n\nThe window fixup code is massively simplified, and many more\nimprovements are now possible.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "56fb4df6da76c35dca22036174e2d1edef83ff1f", "tree": "b39f152ec9ed682edceca965a85680fd4bf736a7", "parents": [ "3c936465249f863f322154ff1aaa628b84ee5750" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sun Feb 26 23:24:22 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:16 2006 -0800" }, "message": "[SPARC64]: Elminate all usage of hard-coded trap globals.\n\nUltraSPARC has special sets of global registers which are switched to\nfor certain trap types. There is one set for MMU related traps, one\nset of Interrupt Vector processing, and another set (called the\nAlternate globals) for all other trap types.\n\nFor what seems like forever we\u0027ve hard coded the values in some of\nthese trap registers. Some examples include:\n\n1) Interrupt Vector global %g6 holds current processors interrupt\n work struct where received interrupts are managed for IRQ handler\n dispatch.\n\n2) MMU global %g7 holds the base of the page tables of the currently\n active address space.\n\n3) Alternate global %g6 held the current_thread_info() value.\n\nSuch hardcoding has resulted in some serious issues in many areas.\nThere are some code sequences where having another register available\nwould help clean up the implementation. Taking traps such as\ncross-calls from the OBP firmware requires some trick code sequences\nwherein we have to save away and restore all of the special sets of\nglobal registers when we enter/exit OBP.\n\nWe were also using the IMMU TSB register on SMP to hold the per-cpu\narea base address, which doesn\u0027t work any longer now that we actually\nuse the TSB facility of the cpu.\n\nThe implementation is pretty straight forward. One tricky bit is\ngetting the current processor ID as that is different on different cpu\nvariants. We use a stub with a fancy calling convention which we\npatch at boot time. The calling convention is that the stub is\nbranched to and the (PC - 4) to return to is in register %g1. The cpu\nnumber is left in %g6. This stub can be invoked by using the\n__GET_CPUID macro.\n\nWe use an array of per-cpu trap state to store the current thread and\nphysical address of the current address space\u0027s page tables. The\nTRAP_LOAD_THREAD_REG loads %g6 with the current thread from this\ntable, it uses __GET_CPUID and also clobbers %g1.\n\nTRAP_LOAD_IRQ_WORK is used by the interrupt vector processing to load\nthe current processor\u0027s IRQ software state into %g6. It also uses\n__GET_CPUID and clobbers %g1.\n\nFinally, TRAP_LOAD_PGD_PHYS loads the physical address base of the\ncurrent address space\u0027s page tables into %g7, it clobbers %g1 and uses\n__GET_CPUID.\n\nMany refinements are possible, as well as some tuning, with this stuff\nin place.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "1da177e4c3f41524e886b7f1b8a0c1fc7321cac2", "tree": "0bba044c4ce775e45a88a51686b5d9f90697ea9d", "parents": [], "author": { "name": "Linus Torvalds", "email": "torvalds@ppc970.osdl.org", "time": "Sat Apr 16 15:20:36 2005 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@ppc970.osdl.org", "time": "Sat Apr 16 15:20:36 2005 -0700" }, "message": "Linux-2.6.12-rc2\n\nInitial git repository build. I\u0027m not bothering with the full history,\neven though we have it. We can create a separate \"historical\" git\narchive of that later if we want to, and in the meantime it\u0027s about\n3.2GB when imported into git - space that would just make the early\ngit days unnecessarily complicated, when we don\u0027t have a lot of good\ninfrastructure for it.\n\nLet it rip!\n" } ] }