)]}' { "log": [ { "commit": "52cf25d0ab7f78eeecc59ac652ed5090f69b619e", "tree": "031d1ffb3890bd69c0260c864c512e0be62ac05c", "parents": [ "6c1733aca0b48db4d0e660d54976a1cca25b5eaf" ], "author": { "name": "Emese Revfy", "email": "re.emese@gmail.com", "time": "Tue Jan 19 02:58:23 2010 +0100" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Sun Mar 07 17:04:49 2010 -0800" }, "message": "Driver core: Constify struct sysfs_ops in struct kobj_type\n\nConstify struct sysfs_ops.\n\nThis is part of the ops structure constification\neffort started by Arjan van de Ven et al.\n\nBenefits of this constification:\n\n * prevents modification of data that is shared\n (referenced) by many other structure instances\n at runtime\n\n * detects/prevents accidental (but not intentional)\n modification attempts on archs that enforce\n read-only kernel data at runtime\n\n * potentially better optimized code as the compiler\n can assume that the const data cannot be changed\n\n * the compiler/linker move const data into .rodata\n and therefore exclude them from false sharing\n\nSigned-off-by: Emese Revfy \u003cre.emese@gmail.com\u003e\nAcked-by: David Teigland \u003cteigland@redhat.com\u003e\nAcked-by: Matt Domsch \u003cMatt_Domsch@dell.com\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nAcked-by: Hans J. Koch \u003chjk@linutronix.de\u003e\nAcked-by: Pekka Enberg \u003cpenberg@cs.helsinki.fi\u003e\nAcked-by: Jens Axboe \u003cjens.axboe@oracle.com\u003e\nAcked-by: Stephen Hemminger \u003cshemminger@vyatta.com\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n" }, { "commit": "4a31c08d2fecc74a630653828f5388fbb037f8c2", "tree": "c3baf80157bab2cf6bdf3d26772001e43233aad6", "parents": [ "2ddb3b15f1b46836c61cfac5b00d8f08a24236e6", "0272282f7cffb469cd2676dcb6e58bc942fcf8a8" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun Mar 07 15:47:19 2010 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun Mar 07 15:47:19 2010 -0800" }, "message": "Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6\n\n* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (26 commits)\n sh: Convert sh to use read/update_persistent_clock\n sh: Move PMB debugfs entry initialization to later stage\n sh: Fix up flush_cache_vmap() on SMP.\n sh: fix up MMU reset with variable PMB mapping sizes.\n sh: establish PMB mappings for NUMA nodes.\n sh: check for existing mappings for bolted PMB entries.\n sh: fixed virt/phys mapping helpers for PMB.\n sh: make pmb iomapping configurable.\n sh: reworked dynamic PMB mapping.\n sh: Fix up cpumask_of_pcibus() for the NUMA build.\n serial: sh-sci: Tidy up build warnings.\n sh: Fix up ctrl_read/write stragglers in migor setup.\n serial: sh-sci: Add DMA support.\n dmaengine: shdma: extend .device_terminate_all() to record partial transfer\n sh: merge sh7722 and sh7724 DMA register definitions\n sh: activate runtime PM for dmaengine on sh7722 and sh7724\n dmaengine: shdma: add runtime PM support.\n dmaengine: shdma: separate DMA headers.\n dmaengine: shdma: convert to platform device resources\n dmaengine: shdma: fix DMA error handling.\n ...\n" }, { "commit": "984b3f5746ed2cde3d184651dabf26980f2b66e5", "tree": "87dc2162b4778b0075874d9592384530022e15a4", "parents": [ "e3cb91ce1ac1d93a7cc6f81bb5247f7602b572bb" ], "author": { "name": "Akinobu Mita", "email": "akinobu.mita@gmail.com", "time": "Fri Mar 05 13:41:37 2010 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sat Mar 06 11:26:23 2010 -0800" }, "message": "bitops: rename for_each_bit() to for_each_set_bit()\n\nRename for_each_bit to for_each_set_bit in the kernel source tree. To\npermit for_each_clear_bit(), should that ever be added.\n\nThe patch includes a macro to map the old for_each_bit() onto the new\nfor_each_set_bit(). This is a (very) temporary thing to ease the migration.\n\n[akpm@linux-foundation.org: add temporary for_each_bit()]\nSuggested-by: Alexey Dobriyan \u003cadobriyan@gmail.com\u003e\nSuggested-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Akinobu Mita \u003cakinobu.mita@gmail.com\u003e\nCc: \"David S. Miller\" \u003cdavem@davemloft.net\u003e\nCc: Russell King \u003crmk@arm.linux.org.uk\u003e\nCc: David Woodhouse \u003cdwmw2@infradead.org\u003e\nCc: Artem Bityutskiy \u003cdedekind@infradead.org\u003e\nCc: Stephen Rothwell \u003csfr@canb.auug.org.au\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "9bb676966aa85e56af00b353387d3c274a26e480", "tree": "cafc9a409aa05cc9060eb53f03c35881f41b6cec", "parents": [ "0f2cc4ecd81dc1917a041dc93db0ada28f8356fa", "dd58ffcf5a5352fc10820c8ffbcd5fed416a2c3a" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Mar 04 08:20:14 2010 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Mar 04 08:20:14 2010 -0800" }, "message": "Merge branch \u0027next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx\n\n* \u0027next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: (28 commits)\n ioat: cleanup -\u003etimer_fn() and -\u003ecleanup_fn() prototypes\n ioat3: interrupt coalescing\n ioat: close potential BUG_ON race in the descriptor cleanup path\n ioat2: kill pending flag\n ioat3: use ioat2_quiesce()\n ioat3: cleanup, don\u0027t enable DCA completion writes\n DMAENGINE: COH 901 318 lli sg offset fix\n DMAENGINE: COH 901 318 configure channel direction\n DMAENGINE: COH 901 318 remove irq counting\n DMAENGINE: COH 901 318 descriptor pool refactoring\n DMAENGINE: COH 901 318 cleanups\n dma: Add MPC512x DMA driver\n Debugging options for the DMA engine subsystem\n iop-adma: redundant/wrong tests in iop_*_count()?\n dmatest: fix handling of an even number of xor_sources\n dmatest: correct raid6 PQ test\n fsldma: Fix cookie issues\n fsldma: Fix cookie issues\n dma: cases IPU_PIX_FMT_BGRA32, BGR32 and ABGR32 are the same in ipu_ch_param_set_size()\n dma: make Open Firmware device id constant\n ...\n" }, { "commit": "dd58ffcf5a5352fc10820c8ffbcd5fed416a2c3a", "tree": "f36172b40f9f3fc2c646f70da40e01705399b6b8", "parents": [ "aa4d72ae946a4fa40486b871717778734184fa29", "56a5d3cf21c71963c8fc506e9b9d3f71641d9c71" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 03 21:22:21 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 03 21:22:21 2010 -0700" }, "message": "Merge branch \u0027coh\u0027 into dmaengine\n" }, { "commit": "aa4d72ae946a4fa40486b871717778734184fa29", "tree": "5c98641f00a7866e28a364861b9af9b6df606fdd", "parents": [ "b9cc98697d1ca35a86bbb708acc6d93993c28f0f" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 03 21:21:13 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 03 21:21:13 2010 -0700" }, "message": "ioat: cleanup -\u003etimer_fn() and -\u003ecleanup_fn() prototypes\n\nIf the calling convention of -\u003etimer_fn() and -\u003ecleanup_fn() are unified\nacross hardware versions we can drop parameters to ioat_init_channel() and\nunify ioat_is_dma_complete() implementations.\n\nBoth -\u003etimer_fn() and -\u003ecleanup_fn() are modified to expect a struct\ndma_chan pointer.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "b9cc98697d1ca35a86bbb708acc6d93993c28f0f", "tree": "22bace58c86068483209b8b2d9a2b6238eb0c179", "parents": [ "aa75db0080603bae27961c0502812dfd0f522bb3" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 03 21:21:13 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 03 21:21:13 2010 -0700" }, "message": "ioat3: interrupt coalescing\n\nThe hardware automatically disables further interrupts after each event\nuntil rearmed. This allows a delay to be injected between the occurence\nof the interrupt and the running of the cleanup routine. The delay is\nscaled by the descriptor backlog and then written to the INTRDELAY\nregister which specifies the number of microseconds to hold off\ninterrupt delivery after an interrupt event occurs. According to\npowertop this reduces the interrupt rate from ~5000 intr/s to ~150\nintr/s per without affecting throughput (simple dd to a raid6 array).\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "aa75db0080603bae27961c0502812dfd0f522bb3", "tree": "3e7fbb0ef4415c9f36107a81378f00bba6db9440", "parents": [ "281befa5592b0c5f9a3856b5666c62ac66d3d9ee" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 03 21:21:10 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 03 21:21:10 2010 -0700" }, "message": "ioat: close potential BUG_ON race in the descriptor cleanup path\n\nSince ioat_cleanup_preamble() and the update of the last completed\ndescriptor are not synchronized there is a chance that two cleanup threads\ncan see descriptors to clean. If the first cleans up all pending\ndescriptors then the second will trigger the BUG_ON.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "281befa5592b0c5f9a3856b5666c62ac66d3d9ee", "tree": "a0e7ca560fd1f2c43d3352786b0a5317af97ccf7", "parents": [ "b372ec2d900a5b50e47ef9e9624536ad146236be" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 03 11:47:43 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 03 11:47:43 2010 -0700" }, "message": "ioat2: kill pending flag\n\nThe pending \u003d\u003d 2 case no longer exists in the driver so, we can use\nioat2_ring_pending() outside the lock to determine if there might be any\ndescriptors in the ring that the hardware has not seen.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "b372ec2d900a5b50e47ef9e9624536ad146236be", "tree": "3c9efbdcac54e7b924057d8b60e223058195d768", "parents": [ "773d9e2d8dbf02cfaf65786cf9100eef02c9fda4" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 03 11:47:42 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 03 11:47:42 2010 -0700" }, "message": "ioat3: use ioat2_quiesce()\n\nReplace open coded ioat2_quiesce() call in ioat3_restart_channel\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "773d9e2d8dbf02cfaf65786cf9100eef02c9fda4", "tree": "f4cdd84bb7ebd3ae8340f02c3c1e0e641601f88c", "parents": [ "0fb6f739bb612bc989d295056877374b749e721b" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 03 11:47:42 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 03 11:47:42 2010 -0700" }, "message": "ioat3: cleanup, don\u0027t enable DCA completion writes\n\nWe already disallow raid operations while DCA is globally enabled, so\nhaving it locally enabled is a nop and confusing when reading the code.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "0a135ba14d71fb84c691a5386aff5049691fe6d7", "tree": "adb1de887dd6839d69d2fc16ffa2a10ff63298fa", "parents": [ "4850f524b2c4c8a4e9f8ef4dd9c7c4afde2f2b2c", "a29d8b8e2d811a24bbe49215a0f0c536b72ebc18" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Mar 03 07:34:18 2010 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Mar 03 07:34:18 2010 -0800" }, "message": "Merge branch \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tj/percpu\n\n* \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tj/percpu:\n percpu: add __percpu sparse annotations to what\u0027s left\n percpu: add __percpu sparse annotations to fs\n percpu: add __percpu sparse annotations to core kernel subsystems\n local_t: Remove leftover local.h\n this_cpu: Remove pageset_notifier\n this_cpu: Page allocator conversion\n percpu, x86: Generic inc / dec percpu instructions\n local_t: Move local.h include to ringbuffer.c and ring_buffer_benchmark.c\n module: Use this_cpu_xx to dynamically allocate counters\n local_t: Remove cpu_local_xx macros\n percpu: refactor the code in pcpu_[de]populate_chunk()\n percpu: remove compile warnings caused by __verify_pcpu_ptr()\n percpu: make accessors check for percpu pointer in sparse\n percpu: add __percpu for sparse.\n percpu: make access macros universal\n percpu: remove per_cpu__ prefix.\n" }, { "commit": "56a5d3cf21c71963c8fc506e9b9d3f71641d9c71", "tree": "3f793e6f9323fa4d34b71c2f1bb85e0497135207", "parents": [ "516fd4305e5f5718475e81fe5c17c95888a8157b" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@stericsson.com", "time": "Tue Mar 02 20:12:56 2010 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Mar 02 14:17:46 2010 -0700" }, "message": "DMAENGINE: COH 901 318 lli sg offset fix\n\nThis makes the COH 901 318 respect the scatter offset field by using\nthe sg_phys() rather than the sg_dma_address() so we get a pointer\nto the actual data we want to send rather than the beginning of the\nbuffer. Also initialize the lli:s a bit more thoroughly.\n\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "516fd4305e5f5718475e81fe5c17c95888a8157b", "tree": "33d6648233b48178d58426d1659fd1234d9f95b0", "parents": [ "0b58828c923e57f1bfbbd2c4277ceb60666314fa" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@stericsson.com", "time": "Tue Mar 02 20:12:46 2010 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Mar 02 14:17:46 2010 -0700" }, "message": "DMAENGINE: COH 901 318 configure channel direction\n\nThis makes the COH 901 318 configure channel direction (to or from\ndevice) dynamically, instead of being passed in from the platform\ndata. This was necessary in order to get the MMC/SD-card channel\nbidirectional (all other channels on the U300 were either RX or\nTX but this one was both). This also sets memcpy() alignent to\neven 2^2 (32bit) boundaries, which makes the memcpy() stress tests\nstart working.\n\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "0b58828c923e57f1bfbbd2c4277ceb60666314fa", "tree": "399402924ea132fdea66a0fce141c9cae6020b8e", "parents": [ "b87108a772e001af3fa79f9cfd87b190375f47a2" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@stericsson.com", "time": "Tue Mar 02 14:17:44 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Mar 02 14:17:44 2010 -0700" }, "message": "DMAENGINE: COH 901 318 remove irq counting\n\nThis removes the pointless irq counting for the COH 901 318, as\nit turns out the hardware will only ever fire one IRQ for a linked\nlist anyway. In the process also a missing spinlock was introduced.\n\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "b87108a772e001af3fa79f9cfd87b190375f47a2", "tree": "003099acce3eb98244bbef317b4db52fe9cbe933", "parents": [ "848ad121240f539e14a59eddd69e164aea9560b2" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@stericsson.com", "time": "Tue Mar 02 14:17:20 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Mar 02 14:17:20 2010 -0700" }, "message": "DMAENGINE: COH 901 318 descriptor pool refactoring\n\nThis centralize some spread-out initialization of descriptors into\none function and cleans up the error paths.\n\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "848ad121240f539e14a59eddd69e164aea9560b2", "tree": "c35cea653fa13f3ec83031a296204606fbaa9aa5", "parents": [ "734c2992828c66cee3feb21ecd30a6ac44aecc51" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@stericsson.com", "time": "Tue Mar 02 14:17:15 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Mar 02 14:17:15 2010 -0700" }, "message": "DMAENGINE: COH 901 318 cleanups\n\nThis cleans up the some debug code that was not working in the\nCOH 901 318 driver, adds some helpful comments and rearrange the\ncode a bit.\n\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "0fb6f739bb612bc989d295056877374b749e721b", "tree": "a7105b3d73736535b3bdb0f15f8f8c0869b81279", "parents": [ "6c664a8915f5341c2e7f1df0bb4b9b4a88f6ad77" ], "author": { "name": "Piotr Ziecik", "email": "kosmo@semihalf.com", "time": "Fri Feb 05 03:42:52 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Mar 01 22:16:42 2010 -0700" }, "message": "dma: Add MPC512x DMA driver\n\nAdds initial version of MPC512x DMA driver.\nOnly memory to memory transfers are currenly supported.\n\nSigned-off-by: Piotr Ziecik \u003ckosmo@semihalf.com\u003e\nSigned-off-by: Wolfgang Denk \u003cwd@denx.de\u003e\nSigned-off-by: Anatolij Gustschin \u003cagust@denx.de\u003e\nCc: John Rigby \u003cjcrigby@gmail.com\u003e\nAcked-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "6c664a8915f5341c2e7f1df0bb4b9b4a88f6ad77", "tree": "031bab9e62b2948ef3fc8a0a3223e8074bc201bb", "parents": [ "f1acb878b6070941e844dfc4ca1b3b9e5a70426c" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@stericsson.com", "time": "Tue Feb 09 22:34:54 2010 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Mar 01 22:13:20 2010 -0700" }, "message": "Debugging options for the DMA engine subsystem\n\nThis adds Kconfig options for DEBUG and VERBOSE_DEBUG to the DMA\nengine subsystem, I got tired of editing the Makefile manually\neach time I want to debug things in here, modelled this on the\ndebug switches for other subsystems and works like a charm when\nworking on our DMA engines.\n\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "c014906a870ce70e009def0c9d170ccabeb0be63", "tree": "b1cfb6520ed0bcdfb0f1b32282b94658a989b04f", "parents": [ "c8e3149ba7de24dfd4c37bb0df23c878cdecd8d4" ], "author": { "name": "Guennadi Liakhovetski", "email": "g.liakhovetski@gmx.de", "time": "Thu Feb 18 16:30:02 2010 +0000" }, "committer": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Tue Mar 02 11:12:03 2010 +0900" }, "message": "dmaengine: shdma: extend .device_terminate_all() to record partial transfer\n\nThis patch extends the .device_terminate_all() method of the shdma driver\nto return number of bytes transfered in the current descriptor.\n\nSigned-off-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nSigned-off-by: Paul Mundt \u003clethal@linux-sh.org\u003e\n" }, { "commit": "20f2a3b5d57701c54bdd59b89dd37fe775926bae", "tree": "28a69ee7db15840fa886c51524c52a1a787487e4", "parents": [ "8b1935e6a36b0967efc593d67ed3aebbfbc1f5b1" ], "author": { "name": "Guennadi Liakhovetski", "email": "g.liakhovetski@gmx.de", "time": "Thu Feb 11 16:50:18 2010 +0000" }, "committer": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Tue Mar 02 11:09:07 2010 +0900" }, "message": "dmaengine: shdma: add runtime PM support.\n\nProvided platforms implement runtime PM, this disables the controller, when not\nin use.\n\nSigned-off-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nSigned-off-by: Paul Mundt \u003clethal@linux-sh.org\u003e\n" }, { "commit": "8b1935e6a36b0967efc593d67ed3aebbfbc1f5b1", "tree": "811ebd670e9704790625137b4a824e548bded00b", "parents": [ "027811b9b81a6b3ae5aa20c3302897bee9dcf09e" ], "author": { "name": "Guennadi Liakhovetski", "email": "g.liakhovetski@gmx.de", "time": "Thu Feb 11 16:50:14 2010 +0000" }, "committer": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Tue Mar 02 11:09:04 2010 +0900" }, "message": "dmaengine: shdma: separate DMA headers.\n\nSeparate SH DMA headers into ones, commonly used by both drivers, and ones,\nspecific to each of them. This will make the future development of the\ndmaengine driver easier.\n\nSigned-off-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nAcked-by: Mark Brown \u003cbroonie@opensource.wolfsonmicro.com\u003e\nSigned-off-by: Paul Mundt \u003clethal@linux-sh.org\u003e\n" }, { "commit": "027811b9b81a6b3ae5aa20c3302897bee9dcf09e", "tree": "cde9b764d10d7ba9d0a41d9c780bf9032214dcae", "parents": [ "47a4dc26eeb89a3746f9b1e2092602b40469640a" ], "author": { "name": "Guennadi Liakhovetski", "email": "g.liakhovetski@gmx.de", "time": "Thu Feb 11 16:50:10 2010 +0000" }, "committer": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Tue Mar 02 11:09:02 2010 +0900" }, "message": "dmaengine: shdma: convert to platform device resources\n\nThe shdma dmaengine driver currently uses numerous macros to support various\nplatforms, selected by ifdef\u0027s. Convert it to use platform device resources and\nlists of channel descriptors to specify register locations, interrupt numbers\nand other system-specific configuration variants. Unavoidably, we have to\nsimultaneously convert all shdma users to provide those resources.\n\nSigned-off-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nSigned-off-by: Paul Mundt \u003clethal@linux-sh.org\u003e\n" }, { "commit": "47a4dc26eeb89a3746f9b1e2092602b40469640a", "tree": "69eb685635ca18f42ac8e245c9be7032a8dd41e7", "parents": [ "920925f90fa6455f7e8c9db0e215e706cd7dedeb" ], "author": { "name": "Guennadi Liakhovetski", "email": "g.liakhovetski@gmx.de", "time": "Thu Feb 11 16:50:05 2010 +0000" }, "committer": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Tue Mar 02 11:09:00 2010 +0900" }, "message": "dmaengine: shdma: fix DMA error handling.\n\nPresent DMA error ISR in shdma.c is bogus, it locks the system hard in multiple\nways. Fix it to abort all queued transactions on all channels on the affected\ncontroller and giving submitters a chance to get a DMA_ERROR status for aborted\ntransactions. Afterwards further functionality is again possible without the\nneed to re-load the driver.\n\nSigned-off-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nSigned-off-by: Paul Mundt \u003clethal@linux-sh.org\u003e\n" }, { "commit": "67b9124f734b22b30d9adf18c39fe795e2901070", "tree": "209e80992ca7722a1ddc82dde8dda1a5e119c666", "parents": [ "94de648d72c8bc833590523f22386d4babbea988" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sun Feb 28 22:20:18 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sun Feb 28 22:20:18 2010 -0700" }, "message": "dmatest: fix handling of an even number of xor_sources\n\nJust like commit ac5d73fc, we need to be careful to use \u0027src_cnt\u0027 as it\ncontains the fixed up number of xor sources (forced odd) to meet dmatest\u0027s\ndata verification scheme.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "94de648d72c8bc833590523f22386d4babbea988", "tree": "8507157200c687012e13da8a5ea5088528c0151f", "parents": [ "76bd061f5c7b7550cdaed68ad6219ea7cee288fc" ], "author": { "name": "Anatolij Gustschin", "email": "agust@denx.de", "time": "Mon Feb 15 22:35:23 2010 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sun Feb 28 22:18:36 2010 -0700" }, "message": "dmatest: correct raid6 PQ test\n\nThe number of PQ sources specified by module parameter \"pq_sources\"\nis always forced odd to fit into dmatest\u0027s destination verificaton\nscheme. But number of PQ sources and coefficients as passed to the\ndriver\u0027s prep_dma_pq() is not adjusted accordingly.\n\nFix it now to get correct PQ testing results in the case passed\n\"pq_sources\" parameter is even.\n\nSigned-off-by: Anatolij Gustschin \u003cagust@denx.de\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nCc: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "76bd061f5c7b7550cdaed68ad6219ea7cee288fc", "tree": "5ae663b8bab6bd77cab2b8bc095c0743cc2da138", "parents": [ "6ca3a7a96e91b1aa8c704153c992b191d35b5747" ], "author": { "name": "Steven J. Magnani", "email": "steve@digidescorp.com", "time": "Sun Feb 28 22:18:16 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sun Feb 28 22:18:16 2010 -0700" }, "message": "fsldma: Fix cookie issues\n\nfsl_dma_update_completed_cookie() appears to calculate the last completed\ncookie incorrectly in the corner case where DMA on cookie 1 is in progress\njust following a cookie wrap.\n\nSigned-off-by: Steven J. Magnani \u003csteve@digidescorp.com\u003e\nAcked-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\n[dan.j.williams@intel.com: fix an integer overflow warning with INT_MAX]\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "6ca3a7a96e91b1aa8c704153c992b191d35b5747", "tree": "4700e2eecbae9e33492df683d11e5366f16aeca2", "parents": [ "9ad7bd2944bd979ef4877cd439719be44c5f3b47" ], "author": { "name": "Steven J. Magnani", "email": "steve@digidescorp.com", "time": "Thu Feb 25 13:39:30 2010 -0600" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sun Feb 28 20:27:42 2010 -0700" }, "message": "fsldma: Fix cookie issues\n\nfsl_dma_tx_submit() only sets the cookie on the first descriptor of a\ntransaction. It should set the cookie on all.\n\nSigned-off-by: Steven J. Magnani \u003csteve@digidescorp.com\u003e\nAcked-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "a29d8b8e2d811a24bbe49215a0f0c536b72ebc18", "tree": "5a714679aeebd5f7af5d1fc521f0db8639324f6c", "parents": [ "003cb608a2533d0927a83bc4e07e46d7a622eda9" ], "author": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Tue Feb 02 14:39:15 2010 +0900" }, "committer": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Wed Feb 17 11:17:38 2010 +0900" }, "message": "percpu: add __percpu sparse annotations to what\u0027s left\n\nAdd __percpu sparse annotations to places which didn\u0027t make it in one\nof the previous patches. All converions are trivial.\n\nThese annotations are to make sparse consider percpu variables to be\nin a different address space and warn if accessed without going\nthrough percpu accessors. This patch doesn\u0027t affect normal builds.\n\nSigned-off-by: Tejun Heo \u003ctj@kernel.org\u003e\nAcked-by: Borislav Petkov \u003cborislav.petkov@amd.com\u003e\nCc: Dan Williams \u003cdan.j.williams@intel.com\u003e\nCc: Huang Ying \u003cying.huang@intel.com\u003e\nCc: Len Brown \u003clenb@kernel.org\u003e\nCc: Neil Brown \u003cneilb@suse.de\u003e\n" }, { "commit": "028c5d5d596651bce13d06737eb3707a7e99a30c", "tree": "e4e429858a19635ad2b5aa563bf1b4e39396d4e2", "parents": [ "19f6b8b44e3f633d5d7d1ed68848b1eb89a1e800", "4b505db9c4c72dbd2a8e66b8d681640101325af6" ], "author": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Mon Feb 15 14:49:37 2010 +0900" }, "committer": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Mon Feb 15 14:49:37 2010 +0900" }, "message": "Merge branch \u0027sh/stable-updates\u0027\n" }, { "commit": "734c2992828c66cee3feb21ecd30a6ac44aecc51", "tree": "c732007f463393046dc83cc3d6b5953cb076aa32", "parents": [ "8f98781e0f15207b6ab33bee1fae05428be0475b" ], "author": { "name": "Julia Lawall", "email": "julia@diku.dk", "time": "Sat Feb 06 09:43:41 2010 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Feb 10 12:07:28 2010 -0700" }, "message": "drivers/dma: Correct NULL test\n\ncohd_fin has already been verified not to be NULL, so the argument to\nBUG_ON cannot be true.\n\nA simplified version of the semantic match that finds this problem is as\nfollows: (http://coccinelle.lip6.fr/)\n\n// \u003csmpl\u003e\n@r@\nexpression *x;\nexpression e;\nidentifier l;\n@@\n\nif (x \u003d\u003d NULL || ...) {\n ... when forall\n return ...; }\n... when !\u003d goto l;\n when !\u003d x \u003d e\n when !\u003d \u0026x\n*x \u003d\u003d NULL\n// \u003c/smpl\u003e\n\nSigned-off-by: Julia Lawall \u003cjulia@diku.dk\u003e\nAcked-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "8f98781e0f15207b6ab33bee1fae05428be0475b", "tree": "31830720fd57bd11191e85bbdc98eaefe061f127", "parents": [ "b953df7c70740cd7593072ebec77a8f658505630" ], "author": { "name": "Guennadi Liakhovetski", "email": "g.liakhovetski@gmx.de", "time": "Wed Feb 10 17:32:38 2010 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Feb 10 12:01:06 2010 -0700" }, "message": "async-tx: fix buffer submission error handling in ipu_idma.c\n\nIf submitting new buffer failed, a wrong descriptor gets completed and it\ndoesn\u0027t check, if a callback is at all defined, which can lead to an Oops. Fix\nthese bugs and make ipu_update_channel_buffer() void, because it never fails.\n\nSigned-off-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "cfefe99795251d76d92e8457f4152f532a961ec5", "tree": "531a4677401afb0e9816441ac1366dfa46f5ca7b", "parents": [ "623b4ac4bf9e767991c66e29b47dd4b19458fb42" ], "author": { "name": "Guennadi Liakhovetski", "email": "g.liakhovetski@gmx.de", "time": "Wed Feb 03 14:46:41 2010 +0000" }, "committer": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Mon Feb 08 09:40:26 2010 +0900" }, "message": "sh: implement DMA_SLAVE capability in SH dmaengine driver\n\nTested to work with a SIU ASoC driver on sh7722 (migor).\n\nSigned-off-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nAcked-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nSigned-off-by: Paul Mundt \u003clethal@linux-sh.org\u003e\n" }, { "commit": "623b4ac4bf9e767991c66e29b47dd4b19458fb42", "tree": "9cf9c5ef8ac1ab714a35db1baf627fb701a98287", "parents": [ "fc4618575f79eea062cdc51715040e40cd35b71c" ], "author": { "name": "Guennadi Liakhovetski", "email": "g.liakhovetski@gmx.de", "time": "Wed Feb 03 14:44:12 2010 +0000" }, "committer": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Mon Feb 08 09:40:24 2010 +0900" }, "message": "sh: fix Transfer Size calculation in both DMA drivers\n\nBoth the original arch/sh/drivers/dma/dma-sh.c and the new SH dmaengine drivers\ndo not take into account bits 3:2 of the Transfer Size field in the CHCR\nregister, besides, bit-field defines set bit 2, but the mask only passes bits\n1:0 through. TS_16BLK and TS_32BLK macros are bogus too. This patch fixes all\nthese issues for sh7722 and sh7724, other CPUs stay unchanged and might need to\nbe fixed too.\n\nSigned-off-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nAcked-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nSigned-off-by: Paul Mundt \u003clethal@linux-sh.org\u003e\n" }, { "commit": "fc4618575f79eea062cdc51715040e40cd35b71c", "tree": "86c3024f48db02b9f5e391d3f0a3aa787fa89375", "parents": [ "6339204ecc2aa2067a99595522de0403f0854bb8" ], "author": { "name": "Guennadi Liakhovetski", "email": "g.liakhovetski@gmx.de", "time": "Tue Jan 19 07:24:55 2010 +0000" }, "committer": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Mon Feb 08 09:38:35 2010 +0900" }, "message": "sh: prepare the DMA driver for slave functionality\n\nSlave DMA functionality uses scatter-gather arrays for data transfers,\nwhereas memcpy just uses a single data buffer. This patch converts the\ncurrent memcpy implementation in shdma.c to use scatter-gather, making it\njust a special case with one SG-element. This allows us to isolate\ndescriptor list manipulations and locking into one function, thus reducing\nerror chances.\n\nSigned-off-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nAcked-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nSigned-off-by: Paul Mundt \u003clethal@linux-sh.org\u003e\n" }, { "commit": "b953df7c70740cd7593072ebec77a8f658505630", "tree": "3f831c33f2b1a0173e7142226869dababcd16422", "parents": [ "7e55a70c5b9a57c12f49c44b0847c9343d4f54e4" ], "author": { "name": "Yong Zhang", "email": "yong.zhang0@gmail.com", "time": "Fri Feb 05 21:52:37 2010 +0800" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Feb 05 15:35:53 2010 -0700" }, "message": "dmaengine: correct onstack wait_queue_head declaration\n\nUse DECLARE_WAIT_QUEUE_HEAD_ONSTACK to make lockdep happy\n\nSigned-off-by: Yong Zhang \u003cyong.zhang0@gmail.com\u003e\nCc: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nCc: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nCc: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "9ad7bd2944bd979ef4877cd439719be44c5f3b47", "tree": "cf70d092016d677b68b4178b7f669939c3820b63", "parents": [ "4b1cf1facca31b7db2a61d8aa2ba40d5a93a0957" ], "author": { "name": "Roel Kluin", "email": "roel.kluin@gmail.com", "time": "Wed Jan 20 01:25:56 2010 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Feb 02 23:42:25 2010 -0700" }, "message": "dma: cases IPU_PIX_FMT_BGRA32, BGR32 and ABGR32 are the same in ipu_ch_param_set_size()\n\nIn these cases the same statements are executed.\n\nSigned-off-by: Roel Kluin \u003croel.kluin@gmail.com\u003e\nAcked-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "4b1cf1facca31b7db2a61d8aa2ba40d5a93a0957", "tree": "97fd86a2a15a6e482546b7f8b92e47c5a56a2aaa", "parents": [ "9c3a50b7d7ec45da34e73cac66cde12dd6092dd8" ], "author": { "name": "Márton Németh", "email": "nm127@freemail.hu", "time": "Tue Feb 02 23:41:06 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Feb 02 23:41:06 2010 -0700" }, "message": "dma: make Open Firmware device id constant\n\nThe match_table field of the struct of_device_id is constant in \u003clinux/of_platform.h\u003e\nso it is worth to make the initialization data also constant.\n\nThe semantic match that finds this kind of pattern is as follows:\n(http://coccinelle.lip6.fr/)\n\n// \u003csmpl\u003e\n@r@\ndisable decl_init,const_decl_init;\nidentifier I1, I2, x;\n@@\n\tstruct I1 {\n\t ...\n\t const struct I2 *x;\n\t ...\n\t};\n@s@\nidentifier r.I1, y;\nidentifier r.x, E;\n@@\n\tstruct I1 y \u003d {\n\t .x \u003d E,\n\t};\n@c@\nidentifier r.I2;\nidentifier s.E;\n@@\n\tconst struct I2 E[] \u003d ... ;\n@depends on !c@\nidentifier r.I2;\nidentifier s.E;\n@@\n+\tconst\n\tstruct I2 E[] \u003d ...;\n// \u003c/smpl\u003e\n\nSigned-off-by: Márton Németh \u003cnm127@freemail.hu\u003e\nCc: Julia Lawall \u003cjulia@diku.dk\u003e\nCc: cocci@diku.dk\n[dan.j.williams@intel.com: resolved conflict with recent fsldma updates]\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "7e55a70c5b9a57c12f49c44b0847c9343d4f54e4", "tree": "e9ba9f5896d8e97e76894f23641afd3abce5aac4", "parents": [ "adef477268ff5ddd0195611dc7e26d7a879fefe1" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Jan 13 13:33:12 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Feb 02 22:57:34 2010 -0700" }, "message": "ioat: fix infinite timeout checking in ioat2_quiesce\n\nFix typo in ioat2_quiesce. check \u0027tmo\u0027 is zero, not \u0027end\u0027. Also applies\nto 2.6.32.3\n\nCc: \u003cstable@kernel.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "adef477268ff5ddd0195611dc7e26d7a879fefe1", "tree": "ad7b36a817f5f045719b28ade67914a2ce775d5c", "parents": [ "abe94c756c08d50566c09a65b9c7fe72f83071c5" ], "author": { "name": "Anatolij Gustschin", "email": "agust@denx.de", "time": "Tue Jan 26 10:26:06 2010 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Feb 02 14:58:37 2010 -0700" }, "message": "dmaengine: fix memleak in dma_async_device_unregister\n\nWhile debugging a dma driver I noticed a memleak after\nunloading the driver module.\n\nCaught by kmemleak.\n\nSigned-off-by: Anatolij Gustschin \u003cagust@denx.de\u003e\nCc: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "9c3a50b7d7ec45da34e73cac66cde12dd6092dd8", "tree": "a16b2dd972ba8ebdd9e6796ad8f0027513316f49", "parents": [ "a1c03319018061304be28d131073ac13a5cb86fb" ], "author": { "name": "Ira Snyder", "email": "iws@ovro.caltech.edu", "time": "Wed Jan 06 13:34:06 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Feb 02 14:51:42 2010 -0700" }, "message": "fsldma: major cleanups and fixes\n\nFix locking. Use two queues in the driver, one for pending transacions, and\none for transactions which are actually running on the hardware. Call\ndma_run_dependencies() on descriptor cleanup so that the async_tx API works\ncorrectly.\n\nThere are a number of places throughout the code where lists of descriptors\nare freed in a loop. Create functions to handle this, and use them instead\nof open-coding the loop each time.\n\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "a1c03319018061304be28d131073ac13a5cb86fb", "tree": "9d5e2f1d0a66d001e94c8dc34681ac49cf1b66bb", "parents": [ "d3f620b2c4fecdc8e060b70e8d92d29fc01c6126" ], "author": { "name": "Ira Snyder", "email": "iws@ovro.caltech.edu", "time": "Wed Jan 06 13:34:05 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Feb 02 14:51:41 2010 -0700" }, "message": "fsldma: rename fsl_chan to chan\n\nThe name fsl_chan seems too long, so it has been shortened to chan. There\nare only a few places where the higher level \"struct dma_chan *chan\" name\nconflicts. These have been changed to \"struct dma_chan *dchan\" instead.\n\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "d3f620b2c4fecdc8e060b70e8d92d29fc01c6126", "tree": "652ddf41247241ef3f82419a80e36bb5ee5dd810", "parents": [ "e7a29151de1bd52081f27f149b68074fac0323be" ], "author": { "name": "Ira Snyder", "email": "iws@ovro.caltech.edu", "time": "Wed Jan 06 13:34:04 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Feb 02 14:51:41 2010 -0700" }, "message": "fsldma: simplify IRQ probing and handling\n\nThe IRQ probing is needlessly complex. All off the 83xx device trees in\narch/powerpc/boot/dts/ specify 5 interrupts per DMA controller: one for the\ncontroller, and one for each channel. These interrupts are all attached to\nthe same IRQ line.\n\nThis causes an interesting situation if two channels interrupt at the same\ntime. The per-controller handler will handle the first channel, and the\nper-channel handler will handle the remaining channels.\n\nInstead of this mess, we fix the bug in the per-controller handler, and\nmake it handle all channels that generated an interrupt. When a\nper-controller handler is specified in the device tree, we prefer to use\nthe shared handler instead of the per-channel handler.\n\nThe 85xx/86xx controllers do not have a per-controller interrupt, and\ninstead use a per-channel interrupt. This behavior has not been changed.\n\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "e7a29151de1bd52081f27f149b68074fac0323be", "tree": "72fa616e49d5ca99e0a1dc79f467e73d071d5dd9", "parents": [ "738f5f7e1ae876448cb7d9c82bea258b69386647" ], "author": { "name": "Ira Snyder", "email": "iws@ovro.caltech.edu", "time": "Wed Jan 06 13:34:03 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Feb 02 14:51:41 2010 -0700" }, "message": "fsldma: clean up the OF subsystem routines\n\nThis fixes some errors in the cleanup paths of the OF subsystem, including\nmissing checks for ioremap failing. Also, some variables were renamed for\nbrevity.\n\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "738f5f7e1ae876448cb7d9c82bea258b69386647", "tree": "61616b4be922b7e3461f26d0d4dc2f9e5b0ac8cc", "parents": [ "a4f56d4b103d4e5d1a59a9118db0185a6bd1a83b" ], "author": { "name": "Ira Snyder", "email": "iws@ovro.caltech.edu", "time": "Wed Jan 06 13:34:02 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Feb 02 14:51:41 2010 -0700" }, "message": "fsldma: rename dest to dst for uniformity\n\nMost functions in the standard library use \"dst\" as a parameter, rather\nthan \"dest\". This renames all use of \"dest\" to \"dst\" to match the usual\nconvention.\n\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "a4f56d4b103d4e5d1a59a9118db0185a6bd1a83b", "tree": "aa00d6faf06d168e57c090f1eb05b16596b9a299", "parents": [ "4ce0e953f6286777452bf07c83056342d6b9b257" ], "author": { "name": "Ira Snyder", "email": "iws@ovro.caltech.edu", "time": "Wed Jan 06 13:34:01 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Feb 02 14:51:41 2010 -0700" }, "message": "fsldma: rename struct fsl_dma_chan to struct fsldma_chan\n\nThis is the beginning of a cleanup which will change all instances of\n\"fsl_dma\" to \"fsldma\" to match the name of the driver itself.\n\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "4ce0e953f6286777452bf07c83056342d6b9b257", "tree": "69a182aaa86cad2e8680132464b122374d7a53b0", "parents": [ "272ca655090978bdaa2630fc44fb2c03da5576fd" ], "author": { "name": "Ira Snyder", "email": "iws@ovro.caltech.edu", "time": "Wed Jan 06 13:34:00 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Feb 02 14:51:40 2010 -0700" }, "message": "fsldma: remove unused structure members\n\nRemove some unused members from the fsldma data structures. A few trivial\nuses of struct resource were converted to use the stack rather than keeping\nthe memory allocated for the lifetime of the driver.\n\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "272ca655090978bdaa2630fc44fb2c03da5576fd", "tree": "3ad63195951405f4a51c44f1a57f125415d649e6", "parents": [ "abe94c756c08d50566c09a65b9c7fe72f83071c5" ], "author": { "name": "Ira Snyder", "email": "iws@ovro.caltech.edu", "time": "Wed Jan 06 13:33:59 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Feb 02 14:51:40 2010 -0700" }, "message": "fsldma: reduce kernel text size\n\nSome of the functions are written in a way where they use multiple reads\nand writes where a single read/write pair could suffice. This shrinks the\nkernel text size measurably, while making the functions easier to\nunderstand.\n\nadd/remove: 0/0 grow/shrink: 1/4 up/down: 4/-196 (-192)\nfunction old new delta\nfsl_chan_set_request_count 120 124 +4\ndma_halt 300 272 -28\nfsl_chan_set_src_loop_size 208 156 -52\nfsl_chan_set_dest_loop_size 208 156 -52\nfsl_chan_xfer_ld_queue 500 436 -64\n\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "05a625486efc3209ae4d98e253dafa6ce0124385", "tree": "b78b4a854639fecc91598ecb05900c929a6ab85e", "parents": [ "1f11abc966b82b9fd0c834707486ef301b2f398d", "f80ca163d65903276bec7045a484a79c0897eb2d" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Dec 30 13:46:29 2009 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Dec 30 13:46:29 2009 -0800" }, "message": "Merge branch \u0027fixes\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx\n\n* \u0027fixes\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx:\n drivers/dma: Correct use after free\n drivers/dma: drop unnecesary memset\n ioat2,3: put channel hardware in known state at init\n async_tx: expand async raid6 test to cover ioatdma corner case\n ioat3: fix p-disabled q-continuation\n sh: fix DMA driver\u0027s descriptor chaining and cookie assignment\n dma: at_hdmac: correct incompatible type for argument 1 of \u0027spin_lock_bh\u0027\n" }, { "commit": "f80ca163d65903276bec7045a484a79c0897eb2d", "tree": "97c7d61d43248b9db0757a76af80ff58b98b5599", "parents": [ "0794ec8ce327ec74416b569b8fb1951274693700", "a6d52d70677e99bdb89b6921c265d0a58c22e597" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Dec 22 17:21:47 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Dec 22 17:21:47 2009 -0700" }, "message": "Merge branch \u0027ioat\u0027 into fixes\n" }, { "commit": "0794ec8ce327ec74416b569b8fb1951274693700", "tree": "4e6a59cdf0c13005d22165932b82acf1213bc937", "parents": [ "1e9d1b13efae7e0a2705611d47ae5f07e27015f0" ], "author": { "name": "Julia Lawall", "email": "julia@diku.dk", "time": "Tue Dec 22 21:30:59 2009 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Dec 22 15:30:08 2009 -0700" }, "message": "drivers/dma: Correct use after free\n\nMove the kfree after the iounmap that refers to the same structure.\n\nA simplified version of the semantic match that finds this problem is as\nfollows: (http://coccinelle.lip6.fr/)\n\n// \u003csmpl\u003e\n@@\nexpression x,e;\nidentifier f;\niterator I;\nstatement S;\n@@\n\n*kfree(x);\n... when !\u003d \u0026x\n when !\u003d x \u003d e\n when !\u003d I(x,...) S\n*x-\u003ef\n// \u003c/smpl\u003e\n\nSigned-off-by: Julia Lawall \u003cjulia@diku.dk\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "1e9d1b13efae7e0a2705611d47ae5f07e27015f0", "tree": "bb5f9eed3636080b2dc8a4791d03b812e65a6786", "parents": [ "3542a113ab2f5880f1b62e5909d754250fb57d6b" ], "author": { "name": "Julia Lawall", "email": "julia@diku.dk", "time": "Sat Dec 19 08:30:30 2009 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Dec 22 15:29:05 2009 -0700" }, "message": "drivers/dma: drop unnecesary memset\n\nmemset of 0 is not needed after kzalloc\n\nThe semantic patch that makes this change is as follows:\n(http://coccinelle.lip6.fr/)\n\n// \u003csmpl\u003e\n@@\nexpression x;\nstatement S;\n@@\n\nx \u003d kzalloc(...);\nif (x \u003d\u003d NULL) S\n... when !\u003d x\n-memset(x,0,...);// \u003c/smpl\u003e\n\nSigned-off-by: Julia Lawall \u003cjulia@diku.dk\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "a6d52d70677e99bdb89b6921c265d0a58c22e597", "tree": "9310005efbfa5d3141c1bf9d9ed5464377419f1e", "parents": [ "e02a0e47a3f061c1a53fc4376332a988ec047e8a" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Dec 19 15:36:02 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Dec 19 15:36:02 2009 -0700" }, "message": "ioat2,3: put channel hardware in known state at init\n\nPut the ioat2 and ioat3 state machines in the halted state with all\nerrors cleared.\n\nThe ioat1 init path is not disturbed for stability, there are no\nreported ioat1 initiaization issues.\n\nCc: \u003cstable@kernel.org\u003e\nReported-by: Roland Dreier \u003crdreier@cisco.com\u003e\nTested-by: Roland Dreier \u003crdreier@cisco.com\u003e\nAcked-by: Simon Horman \u003chorms@verge.net.au\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "cd78809f6191485a90ea6c92c2b58900ab5c156f", "tree": "d17a0e30178ec8ae78e04df69ca3d7b280054361", "parents": [ "22763c5cf3690a681551162c15d34d935308c8d7" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Dec 17 13:52:39 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Dec 17 13:52:39 2009 -0700" }, "message": "ioat3: fix p-disabled q-continuation\n\nWhen continuing a pq calculation the driver needs 3 extra sources. The\ndriver can perform a 3 source calculation with a single descriptor, but\nneeds an extended descriptor to process up to 8 sources in one\noperation. However, in the p-disabled case only one extra source is\nneeded. When continuing a p-disabled operation there are occasions\n(i.e. 0 \u003c src_cnt % 8 \u003c 3) where the tail operation does not need an\nextended descriptor. Properly account for this fact otherwise invalid\n\u0027dmacount\u0027 values will be written to hardware usually causing the\nchannel to halt with \u0027invalid descriptor\u0027 errors.\n\nCc: \u003cstable@kernel.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "3542a113ab2f5880f1b62e5909d754250fb57d6b", "tree": "30359d2425678ccc84b62c055c19e943a300ecf6", "parents": [ "4297a462f455e38f08976df7b16c849614a287da" ], "author": { "name": "Guennadi Liakhovetski", "email": "g.liakhovetski@gmx.de", "time": "Thu Dec 17 09:41:39 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Dec 17 09:41:39 2009 -0700" }, "message": "sh: fix DMA driver\u0027s descriptor chaining and cookie assignment\n\nThe SH DMA driver wrongly assigns negative cookies to transfer descriptors,\nalso, its chaining of partial descriptors is broken. The latter problem is\nusually invisible, because maximum transfer size per chunk is 16M, but if you\nartificially set this limit lower, the driver fails. Since cookies are also\nused in chunk management, both these problems are fixed in one patch. As side\neffects a possible memory leak, when descriptors are prepared, but not\nsubmitted, and multiple races have also been fixed.\n\nSigned-off-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nAcked-by: Paul Mundt \u003clethal@linux-sh.org\u003e\nAcked-by: Nobuhiro Iwamatsu \u003ciwamatsu@nigauri.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "7949456b1b96924c2d9ae5aea5fa7d4c81c946ed", "tree": "819e64dcd686c8b53c698c164aea96a002e8b5f8", "parents": [ "60d9aa758c00f20ade0cb1951f6a934f628dd2d7", "12458ea06efd7b44281e68fe59c950ec7d59c649" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Dec 16 10:28:56 2009 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Dec 16 10:28:56 2009 -0800" }, "message": "Merge branch \u0027next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx\n\n* \u0027next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx:\n ppc440spe-adma: adds updated ppc440spe adma driver\n iop-adma.c: use resource_size()\n dmaengine: clarify the meaning of the DMA_CTRL_ACK flag\n sh: stylistic improvements for the DMA driver\n dmaengine: fix dmatest to verify minimum transfer length and test buffer size\n sh: DMA driver has to specify its alignment requirements\n Add COH 901 318 DMA block driver v5\n" }, { "commit": "4297a462f455e38f08976df7b16c849614a287da", "tree": "0c488ff750a68ad4058fdc77561a5392f71877d0", "parents": [ "12458ea06efd7b44281e68fe59c950ec7d59c649" ], "author": { "name": "Nicolas Ferre", "email": "nicolas.ferre@atmel.com", "time": "Wed Dec 16 16:28:03 2009 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Dec 16 11:21:48 2009 -0700" }, "message": "dma: at_hdmac: correct incompatible type for argument 1 of \u0027spin_lock_bh\u0027\n\nCorrect a typo error in locking calls.\n\nCc: \u003cstable@kernel.org\u003e\nSigned-off-by: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "471452104b8520337ae2fb48c4e61cd4896e025d", "tree": "8594ae4a8362014e3cccf72a4e8834cdbb610bdd", "parents": [ "0ead0f84e81a41c3e98aeceab04af8ab1bb08d1f" ], "author": { "name": "Alexey Dobriyan", "email": "adobriyan@gmail.com", "time": "Mon Dec 14 18:00:08 2009 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Dec 15 08:53:25 2009 -0800" }, "message": "const: constify remaining dev_pm_ops\n\nSigned-off-by: Alexey Dobriyan \u003cadobriyan@gmail.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "d0316554d3586cbea60592a41391b5def2553d6f", "tree": "5e7418f0bacbc68cec5dfd1541e03eb56870aa02", "parents": [ "fb0bbb92d42d5bd0ab224605444efdfed06d6934", "51e99be00ce2713cbb841cedc997cafa6e26c7f4" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Dec 14 09:58:24 2009 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Dec 14 09:58:24 2009 -0800" }, "message": "Merge branch \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tj/percpu\n\n* \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tj/percpu: (34 commits)\n m68k: rename global variable vmalloc_end to m68k_vmalloc_end\n percpu: add missing per_cpu_ptr_to_phys() definition for UP\n percpu: Fix kdump failure if booted with percpu_alloc\u003dpage\n percpu: make misc percpu symbols unique\n percpu: make percpu symbols in ia64 unique\n percpu: make percpu symbols in powerpc unique\n percpu: make percpu symbols in x86 unique\n percpu: make percpu symbols in xen unique\n percpu: make percpu symbols in cpufreq unique\n percpu: make percpu symbols in oprofile unique\n percpu: make percpu symbols in tracer unique\n percpu: make percpu symbols under kernel/ and mm/ unique\n percpu: remove some sparse warnings\n percpu: make alloc_percpu() handle array types\n vmalloc: fix use of non-existent percpu variable in put_cpu_var()\n this_cpu: Use this_cpu_xx in trace_functions_graph.c\n this_cpu: Use this_cpu_xx for ftrace\n this_cpu: Use this_cpu_xx in nmi handling\n this_cpu: Use this_cpu operations in RCU\n this_cpu: Use this_cpu ops for VM statistics\n ...\n\nFix up trivial (famous last words) global per-cpu naming conflicts in\n\tarch/x86/kvm/svm.c\n\tmm/slab.c\n" }, { "commit": "12458ea06efd7b44281e68fe59c950ec7d59c649", "tree": "264df3c6fa054b7b866bb2eccca5f83e41044632", "parents": [ "2e032b62c4c8560d6416ad3cc925cfc2a5eafb07" ], "author": { "name": "Anatolij Gustschin", "email": "agust@denx.de", "time": "Fri Dec 11 21:24:44 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Dec 11 21:24:44 2009 -0700" }, "message": "ppc440spe-adma: adds updated ppc440spe adma driver\n\nThis patch adds new version of the PPC440SPe ADMA driver.\n\nSigned-off-by: Yuri Tikhonov \u003cyur@emcraft.com\u003e\nSigned-off-by: Anatolij Gustschin \u003cagust@denx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "2e032b62c4c8560d6416ad3cc925cfc2a5eafb07", "tree": "8700a84d68eebf61def8dde6cf4bd5d76a13c5fb", "parents": [ "a88f6667078412e5eff37ead68a043ee0ec9f1da" ], "author": { "name": "H Hartley Sweeten", "email": "hartleys@visionengravers.com", "time": "Fri Dec 11 21:24:33 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Dec 11 21:24:33 2009 -0700" }, "message": "iop-adma.c: use resource_size()\n\nThe size of the requested and ioremaped memory is off by 1.\nUse resource_size() to get the correct value.\n\nSigned-off-by: H Hartley Sweeten \u003chsweeten@visionengravers.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "86d61b33e48f1da5a6b310d3de93187db62ab72a", "tree": "9d82b881df70b3832111c9f79da69fcb60aa079b", "parents": [ "cfe4f2751ef1a5390b56c5d263f90b6ff138ba31" ], "author": { "name": "Guennadi Liakhovetski", "email": "g.liakhovetski@gmx.de", "time": "Thu Dec 10 18:35:07 2009 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Dec 10 23:32:09 2009 -0700" }, "message": "sh: stylistic improvements for the DMA driver\n\nSigned-off-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "cfe4f2751ef1a5390b56c5d263f90b6ff138ba31", "tree": "05eb71e6046cde60a728b792b9b44918e9b1c210", "parents": [ "ddb4f0f0e05871c7ac540cc778993c06ff53b765" ], "author": { "name": "Guennadi Liakhovetski", "email": "g.liakhovetski@gmx.de", "time": "Fri Dec 04 19:44:48 2009 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Dec 10 23:27:51 2009 -0700" }, "message": "dmaengine: fix dmatest to verify minimum transfer length and test buffer size\n\nTransfers and the test buffer have to be at least align bytes long.\n\nSigned-off-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "ddb4f0f0e05871c7ac540cc778993c06ff53b765", "tree": "6880d9690d296bd2cade679e46ccca8986deab83", "parents": [ "61f135b92f4758bc4d4767cd0a5d2da954e27f14" ], "author": { "name": "Guennadi Liakhovetski", "email": "g.liakhovetski@gmx.de", "time": "Fri Dec 04 19:44:41 2009 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Dec 10 23:25:58 2009 -0700" }, "message": "sh: DMA driver has to specify its alignment requirements\n\nThe SH DMA driver by default uses 32-byte transfers, in this mode buffers and\nsizes have to be 32-byte aligned. Specifying this requirement also fixes Oopses\nwith dmatest.\n\nSigned-off-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "4ef58d4e2ad1fa2a3e5bbf41af2284671fca8cf8", "tree": "856ba96302a36014736747e8464f80eeb827bbdd", "parents": [ "f6c4c8195b5e7878823caa1181be404d9e86d369", "d014d043869cdc591f3a33243d3481fa4479c2d0" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Dec 09 19:43:33 2009 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Dec 09 19:43:33 2009 -0800" }, "message": "Merge branch \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial\n\n* \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: (42 commits)\n tree-wide: fix misspelling of \"definition\" in comments\n reiserfs: fix misspelling of \"journaled\"\n doc: Fix a typo in slub.txt.\n inotify: remove superfluous return code check\n hdlc: spelling fix in find_pvc() comment\n doc: fix regulator docs cut-and-pasteism\n mtd: Fix comment in Kconfig\n doc: Fix IRQ chip docs\n tree-wide: fix assorted typos all over the place\n drivers/ata/libata-sff.c: comment spelling fixes\n fix typos/grammos in Documentation/edac.txt\n sysctl: add missing comments\n fs/debugfs/inode.c: fix comment typos\n sgivwfb: Make use of ARRAY_SIZE.\n sky2: fix sky2_link_down copy/paste comment error\n tree-wide: fix typos \"couter\" -\u003e \"counter\"\n tree-wide: fix typos \"offest\" -\u003e \"offset\"\n fix kerneldoc for set_irq_msi()\n spidev: fix double \"of of\" in comment\n comment typo fix: sybsystem -\u003e subsystem\n ...\n" }, { "commit": "d014d043869cdc591f3a33243d3481fa4479c2d0", "tree": "63626829498e647ba058a1ce06419fe7e4d5f97d", "parents": [ "6ec22f9b037fc0c2e00ddb7023fad279c365324d", "6070d81eb5f2d4943223c96e7609a53cdc984364" ], "author": { "name": "Jiri Kosina", "email": "jkosina@suse.cz", "time": "Mon Dec 07 18:36:35 2009 +0100" }, "committer": { "name": "Jiri Kosina", "email": "jkosina@suse.cz", "time": "Mon Dec 07 18:36:35 2009 +0100" }, "message": "Merge branch \u0027for-next\u0027 into for-linus\n\nConflicts:\n\n\tkernel/irq/chip.c\n" }, { "commit": "e28edb723e64200554194da17617ee6e82de6690", "tree": "6116b7166054a17c9fbd94ade6db070d31c7c786", "parents": [ "2fc42814d8a9dd757abc7f80fbf11e9247e97d40", "01c62c9b32ec122bf5e3edeecec4d826cb8e81e5", "43234b1ef630388c2cffb34eeeaa84dd731602cc", "183bd50f4fe6cd49c1790a90163e3d1ece80f344", "50dcfa0234753c32e1c838cc0e6d7952dda73201", "045868df2c5eee2330c052f8237b428afa9394fd", "6635529987cd01f9af0c3996cf2e7b9e2bbb4aa7", "870725d9fcdecb23eab696d405fa90df46151865" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Dec 05 10:35:18 2009 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Dec 05 10:35:18 2009 +0000" }, "message": "Merge branches \u0027at91\u0027, \u0027ep93xx\u0027, \u0027etm\u0027, \u0027ks8695\u0027, \u0027nuc\u0027, \u0027u300\u0027 and \u0027u8500\u0027 into devel\n" }, { "commit": "af901ca181d92aac3a7dc265144a9081a86d8f39", "tree": "380054af22521144fbe1364c3bcd55ad24c9bde4", "parents": [ "972b94ffb90ea6d20c589d9a47215df103388ddd" ], "author": { "name": "André Goddard Rosa", "email": "andre.goddard@gmail.com", "time": "Sat Nov 14 13:09:05 2009 -0200" }, "committer": { "name": "Jiri Kosina", "email": "jkosina@suse.cz", "time": "Fri Dec 04 15:39:55 2009 +0100" }, "message": "tree-wide: fix assorted typos all over the place\n\nThat is \"success\", \"unknown\", \"through\", \"performance\", \"[re|un]mapping\"\n, \"access\", \"default\", \"reasonable\", \"[con]currently\", \"temperature\"\n, \"channel\", \"[un]used\", \"application\", \"example\",\"hierarchy\", \"therefore\"\n, \"[over|under]flow\", \"contiguous\", \"threshold\", \"enough\" and others.\n\nSigned-off-by: André Goddard Rosa \u003candre.goddard@gmail.com\u003e\nSigned-off-by: Jiri Kosina \u003cjkosina@suse.cz\u003e\n" }, { "commit": "56adf7e8127d601b172e180b44551ce83404348f", "tree": "eabcdad1e4b17ea8f7c20a50a44ca859360085d3", "parents": [ "49954c1567cb0d70d28bb5512d471dc5bd4e2c3f" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sun Nov 22 12:10:10 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sun Nov 22 12:10:10 2009 -0700" }, "message": "shdma: fix initialization error handling\n\n1/ Error handling code following a kzalloc should free the allocated data.\n2/ Report an error when no platform data is detected\n\nBoth problems fixed by moving the platform data check before the allocation,\nand allows a goto to be killed.\n\nReported-by: Julia Lawall \u003cjulia@diku.dk\u003e\nAcked-by: Julia Lawall \u003cjulia@diku.dk\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "61f135b92f4758bc4d4767cd0a5d2da954e27f14", "tree": "388fdc08150e2f8fcb2859f70ca67cdd86616f36", "parents": [ "b419148e567728f6af0c3b01965c1cc141e3e13a" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@stericsson.com", "time": "Thu Nov 19 19:49:17 2009 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 23:45:19 2009 -0700" }, "message": "Add COH 901 318 DMA block driver v5\n\nThis patch adds support for the ST-Ericsson COH 901 318 DMA block,\nfound in the U300 series platforms. It registers a DMA slave for\ndevice I/O and also a memcpy slave for memcpy.\n\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "49954c1567cb0d70d28bb5512d471dc5bd4e2c3f", "tree": "c64b4585518028b5c8ae749b93d9f560d536f649", "parents": [ "7b3cc2b1fc2066391e498f3387204908c4eced21" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 17:11:03 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 23:21:03 2009 -0700" }, "message": "ioat3: fix pq completion versus channel deallocation race\n\nThe completion of a pq operation is notified with a null descriptor\nappended to the end of the chain. This descriptor needs to be visible\nto dma clients otherwise the client is precluded from ensuring all\noperations are quiesced before freeing channel resources, i.e. due to\ndescriptor polling it may get the completion notification ahead of the\ninterrupt delivered by the null descriptor.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "7b3cc2b1fc2066391e498f3387204908c4eced21", "tree": "8a2bc28955710c580201046d04843773cb7d87a1", "parents": [ "4499a24dec00e037da7d09caccad45e7594a9c19" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 17:10:37 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 23:21:03 2009 -0700" }, "message": "async_tx: build-time toggling of async_{syndrome,xor}_val dma support\n\nioat3.2 does not support asynchronous error notifications which makes\nthe driver experience latencies when non-zero pq validate results are\nexpected. Provide a mechanism for turning off async_xor_val and\nasync_syndrome_val via Kconfig. This approach is generally useful for\nany driver that specifies ASYNC_TX_DISABLE_CHANNEL_SWITCH and would like\nto force the async_tx api to fall back to the synchronous path for\ncertain operations.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "4499a24dec00e037da7d09caccad45e7594a9c19", "tree": "d336eb5f67a2873bcd7e43ef64d5d149283e7e0f", "parents": [ "b57014def9afc2bd8a62299d2f51b77dad5ae0c7" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 17:10:25 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 23:21:03 2009 -0700" }, "message": "dmaengine: include xor/pq validate in device_has_all_tx_types()\n\nA channel must include these capabilities to satisfy\nASYNC_TX_DISABLE_CHANNEL_SWITCH.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "b57014def9afc2bd8a62299d2f51b77dad5ae0c7", "tree": "b196078bed3b982475bd0dd22ce0ce8aad2f517a", "parents": [ "de581b65f6fe78168affa552c3bd15b8c80ed614" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 17:10:07 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 23:21:03 2009 -0700" }, "message": "ioat2,3: report all uncorrectable errors\n\nModify is_ioat_bug() to catch all errors that are uncorrectable, or not\ncurrently handled.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "de581b65f6fe78168affa552c3bd15b8c80ed614", "tree": "b980e64cf31ad79c489838310be2e13e626dd05c", "parents": [ "6f82b83b7a56bc6e9dd6d7b93531dde6027c5309" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 17:08:45 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 17:08:45 2009 -0700" }, "message": "ioat3: specify valid address for disabled-Q or disabled-P\n\nAlthough disabled, hardware still checks address validity, so duplicate\nthe known address.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "6f82b83b7a56bc6e9dd6d7b93531dde6027c5309", "tree": "d6f9fc6064e60711e1d041a48d8ff0927ca819e7", "parents": [ "228c4f5cfbf1cda411d9aa7204a612a63c89b1e8" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 17:07:57 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 17:07:57 2009 -0700" }, "message": "ioat2,3: disable asynchronous error notifications\n\nError interrupts and error completions may cause channel hangs, so\npoll the channel status register after a timeout.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "228c4f5cfbf1cda411d9aa7204a612a63c89b1e8", "tree": "0920f900732ce598fef2cdc0c4899860534e837d", "parents": [ "e22dde9904c2d26a522f1a2b89854a8238bf0933" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 17:07:10 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 17:07:10 2009 -0700" }, "message": "ioat3: dca and raid operations are incompatible\n\nRAID operations cause a system hang on platforms with DCA\n(Direct-Cache-Access) enabled. So turn off RAID capabilities in this\ncase.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "e22dde9904c2d26a522f1a2b89854a8238bf0933", "tree": "dbb3b1f2d1d1ddafb3c004819c25c31a73811ae8", "parents": [ "b419148e567728f6af0c3b01965c1cc141e3e13a" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Nov 17 11:34:31 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Nov 17 11:34:31 2009 -0700" }, "message": "ioat: silence \"dca disabled\" messages\n\nTurning off dca is not an \"error\", and the dca-enabled state can be\nviewed from sysfs.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "cd3abf98aeaec9b23a926159856b54a95707ee88", "tree": "c5d73254dce77c63e88ac9010322fbd1da032984", "parents": [ "f51f78c06c7fb442d304b93b68b3a1ebe3785a55" ], "author": { "name": "Yegor Yefremov", "email": "yegorslists@googlemail.com", "time": "Fri Oct 23 11:27:59 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Oct 25 16:00:34 2009 +0000" }, "message": "ARM: 5770/1: Add DMA Engine support to at91sam9g45\n\nAdd at91sam9g45 dependency to drivers/dma/Kconfig\n\nSigned-off-by: Yegor Yefremov \u003cyegorslists@googlemail.com\u003e\nAcked-by: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "e7dcaa4755e35d7540bf19f316f8798357c53fa0", "tree": "69c41151378213382199b577f2bc7b0d8bd1cc22", "parents": [ "ca0c9584b1f16bd5911893647cb7f1be82e60554" ], "author": { "name": "Christoph Lameter", "email": "cl@linux-foundation.org", "time": "Sat Oct 03 19:48:23 2009 +0900" }, "committer": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Sat Oct 03 19:48:23 2009 +0900" }, "message": "this_cpu: Eliminate get/put_cpu\n\nThere are cases where we can use this_cpu_ptr and as the result\nof using this_cpu_ptr() we no longer need to determine the\ncurrently executing cpu.\n\nIn those places no get/put_cpu combination is needed anymore.\nThe local cpu variable can be eliminated.\n\nPreemption still needs to be disabled and enabled since the\nmodifications of the per cpu variables is not atomic. There may\nbe multiple per cpu variables modified and those must all\nbe from the same processor.\n\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nAcked-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nAcked-by: Tejun Heo \u003ctj@kernel.org\u003e\ncc: Eric Biederman \u003cebiederm@aristanetworks.com\u003e\ncc: Stephen Hemminger \u003cshemminger@vyatta.com\u003e\ncc: David L Stevens \u003cdlstevens@us.ibm.com\u003e\nSigned-off-by: Christoph Lameter \u003ccl@linux-foundation.org\u003e\nSigned-off-by: Tejun Heo \u003ctj@kernel.org\u003e\n" }, { "commit": "4b3df5668c8ebaebd8d66a5a94374be3e3b2ef0c", "tree": "51a231742e211143f5845edf4b09d1712dcd2771", "parents": [ "1ef04fefe2241087d9db7e9615c3f11b516e36cf", "1f6672d44c1ae7408b43c06170ec34eb0a0e9b9f" ], "author": { "name": "NeilBrown", "email": "neilb@suse.de", "time": "Wed Sep 23 18:31:11 2009 +1000" }, "committer": { "name": "NeilBrown", "email": "neilb@suse.de", "time": "Wed Sep 23 18:31:11 2009 +1000" }, "message": "Merge branch \u0027next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx into for-linus\n" }, { "commit": "cdef57dbb618608bfffda2fc32c8d0a4012a1d3a", "tree": "e58d3301ea4fb264f713c4602c25e6451d4e6707", "parents": [ "f477f5b3316f39c841aa121a219b82b3a56e7da7" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Sep 21 09:22:29 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Sep 21 09:22:29 2009 -0700" }, "message": "ioat3: fix uninitialized var warnings\n\ndrivers/dma/ioat/dma_v3.c: In function \u0027ioat3_prep_memset_lock\u0027:\ndrivers/dma/ioat/dma_v3.c:439: warning: \u0027fill\u0027 may be used uninitialized in this function\ndrivers/dma/ioat/dma_v3.c:437: warning: \u0027desc\u0027 may be used uninitialized in this function\ndrivers/dma/ioat/dma_v3.c: In function \u0027__ioat3_prep_xor_lock\u0027:\ndrivers/dma/ioat/dma_v3.c:489: warning: \u0027xor\u0027 may be used uninitialized in this function\ndrivers/dma/ioat/dma_v3.c:486: warning: \u0027desc\u0027 may be used uninitialized in this function\ndrivers/dma/ioat/dma_v3.c: In function \u0027__ioat3_prep_pq_lock\u0027:\ndrivers/dma/ioat/dma_v3.c:631: warning: \u0027pq\u0027 may be used uninitialized in this function\ndrivers/dma/ioat/dma_v3.c:628: warning: \u0027desc\u0027 may be used uninitialized in this function\n\ngcc-4.0, unlike gcc-4.3, does not see that these variables are\ninitialized before use. Convert the descriptor loops to do-while make\nthis initialization apparent.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "f477f5b3316f39c841aa121a219b82b3a56e7da7", "tree": "392476186ece4084f85b3c5227853d92ecae79a6", "parents": [ "1b6df6930994d5d027375b07ac9da63644eb5758" ], "author": { "name": "Andrew Morton", "email": "akpm@linux-foundation.org", "time": "Mon Sep 21 09:17:58 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Sep 21 09:17:58 2009 -0700" }, "message": "drivers/dma/ioat/dma_v2.c: fix warnings\n\ndrivers/dma/ioat/dma_v2.c: In function \u0027ioat2_dma_prep_memcpy_lock\u0027:\ndrivers/dma/ioat/dma_v2.c:680: warning: \u0027hw\u0027 may be used uninitialized in this function\ndrivers/dma/ioat/dma_v2.c:681: warning: \u0027desc\u0027 may be used uninitialized in this function\n\nCc: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "376ec37667b510453f5a62fcd95d762786e6a0a9", "tree": "7352166b585463ce53633e379b96196dff72014f", "parents": [ "6c910a78e495b4c1778a8b136b37fe3c05712730" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Sep 16 15:16:50 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Sep 16 15:16:50 2009 -0700" }, "message": "ioat2: clarify ring size limits\n\nWith the addition of ioat_max_alloc_order it is not clear what the\nmaximum allocation order is, so document that in the modinfo. Also take\nan opportunity to kill a stray semicolon.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "33f82d141c897f39cd8bce592d88cb3c5af58342", "tree": "7765831183d05fb635e60e8f8bf92e0bdfe06b5c", "parents": [ "3eb132c986f04f64b9c360abd67a1e0d18d6d5b4" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Sep 10 00:06:44 2009 +0200" }, "committer": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Mon Sep 14 20:27:00 2009 +0200" }, "message": "at_hdmac: Rework suspend_late()/resume_early()\n\nThis patch reworks platform driver power management code\nfor at_hdmac from legacy late/early callbacks to dev_pm_ops.\n\nThe callbacks are converted for CONFIG_SUSPEND like this:\n suspend_late() -\u003e suspend_noirq()\n resume_early() -\u003e resume_noirq()\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\n" }, { "commit": "3208ca52f3bfa36914c44db207d0a34071f9897f", "tree": "fb28779eb8ec74fd650f2df085f507353fcd79ce", "parents": [ "1a5aeeecd550ee4344cfba1791f1134739b16dc6" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Sep 10 11:27:36 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Sep 10 11:27:36 2009 -0700" }, "message": "ioat: driver version 4.0\n\nA new ring implementation and the addition of raid functionality\nconstitutes a bump in the driver major version number.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "1a5aeeecd550ee4344cfba1791f1134739b16dc6", "tree": "0b2f1f104d7dbff82130ea1d41c037a74fa6753e", "parents": [ "9a8de639f35ca3951b910d5e3a2f92f4cf3afc8f" ], "author": { "name": "Maciej Sosnowski", "email": "maciej.sosnowski@intel.com", "time": "Thu Sep 10 15:05:58 2009 +0200" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Sep 10 10:00:05 2009 -0700" }, "message": "dca: registering requesters in multiple dca domains\n\nThis patch enables DCA support on multiple-IOH/multiple-IIO architectures.\nIt modifies dca module by replacing single dca_providers list\nwith dca_domains list, each domain containing separate list of providers.\nThis approach lets dca driver manage multiple domains, i.e. sets of providers\nand requesters mapped back to the same PCI root complex device.\nThe driver takes care to register each requester to a provider\nfrom the same domain.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\n" }, { "commit": "9a8de639f35ca3951b910d5e3a2f92f4cf3afc8f", "tree": "58d799166b6facdf25e314885ee7fadd20597482", "parents": [ "d8902adcc1a9fd484c8cb5e575152e32192c1ff8" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 15:06:10 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:56:37 2009 -0700" }, "message": "async_tx: remove HIGHMEM64G restriction\n\nThis restriction prevented ASYNC_TX_DMA from being enabled on platform\nconfigurations where DMA address conversion could not be performed in\nplace on the stack. Since commit 04ce9ab3 (\"async_xor: permit callers\nto pass in a \u0027dma/page scribble\u0027 region\") the async_tx api now either\nuses a caller provided \u0027scribble\u0027 buffer, or performs the conversion in\nplace when sizeof(dma_addr_t) \u003c\u003d sizeof(struct page *).\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "d8902adcc1a9fd484c8cb5e575152e32192c1ff8", "tree": "305109ce60db5ea9710dddce9db8a23f65ff4572", "parents": [ "9134d02bc0af4a8747d448d1f811ec5f8eb96df6" ], "author": { "name": "Nobuhiro Iwamatsu", "email": "iwamatsu.nobuhiro@renesas.com", "time": "Mon Sep 07 03:26:23 2009 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:56:02 2009 -0700" }, "message": "dmaengine: sh: Add Support SuperH DMA Engine driver\n\nThis supported all DMA channels, and it was tested in SH7722,\nSH7780, SH7785 and SH7763.\nThis can not use with SH DMA API.\n\nSigned-off-by: Nobuhiro Iwamatsu \u003ciwamatsu.nobuhiro@renesas.com\u003e\nReviewed-by: Matt Fleming \u003cmatt@console-pimps.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nAcked-by: Paul Mundt \u003clethal@linux-sh.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "bbb20089a3275a19e475dbc21320c3742e3ca423", "tree": "216fdc1cbef450ca688135c5b8969169482d9a48", "parents": [ "3e48e656903e9fd8bc805c6a2c4264d7808d315b", "657a77fa7284d8ae28dfa48f1dc5d919bf5b2843" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:55:21 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:55:21 2009 -0700" }, "message": "Merge branch \u0027dmaengine\u0027 into async-tx-next\n\nConflicts:\n\tcrypto/async_tx/async_xor.c\n\tdrivers/dma/ioat/dma_v2.h\n\tdrivers/dma/ioat/pci.c\n\tdrivers/md/raid5.c\n" }, { "commit": "3e48e656903e9fd8bc805c6a2c4264d7808d315b", "tree": "dfee34eb1f317b35f33a02291e65ce6ec46e3a5a", "parents": [ "a6417dd58d6832f123f36c6f22c63ec1ab62ce1c", "f6dbf651615900646fe0ba1ef5ce1027e5b4748d" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:57 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:57 2009 -0700" }, "message": "Merge branch \u0027iop-raid6\u0027 into async-tx-next\n" }, { "commit": "657a77fa7284d8ae28dfa48f1dc5d919bf5b2843", "tree": "74fd6b5c2c35dcea18928a600ff34c04f8626cb6", "parents": [ "bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7d" ], "author": { "name": "Atsushi Nemoto", "email": "anemo@mba.ocn.ne.jp", "time": "Tue Sep 08 17:53:05 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:05 2009 -0700" }, "message": "dmaengine: Move all map_sg/unmap_sg for slave channel to its client\n\nDan Williams wrote:\n... DMA-slave clients request specific channels and know the hardware\ndetails at a low level, so it should not be too high an expectation to\npush dma mapping responsibility to the client.\n\nAlso this patch includes DMA_COMPL_{SRC,DEST}_UNMAP_SINGLE support for\ndw_dmac driver.\n\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nAcked-by: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nSigned-off-by: Atsushi Nemoto \u003canemo@mba.ocn.ne.jp\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7d", "tree": "5f2145c023b9145d1461ecb63c839fd32f762378", "parents": [ "e6c7ecb64e08ef346cb7062b4a5421f00bc602bd" ], "author": { "name": "Ira Snyder", "email": "iws@ovro.caltech.edu", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "message": "fsldma: Add DMA_SLAVE support\n\nUse the DMA_SLAVE capability of the DMAEngine API to copy/from a\nscatterlist into an arbitrary list of hardware address/length pairs.\n\nThis allows a single DMA transaction to copy data from several different\ndevices into a scatterlist at the same time.\n\nThis also adds support to enable some controller-specific features such as\nexternal start and external pause for a DMA transaction.\n\n[dan.j.williams@intel.com: rebased on tx_list movement]\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nAcked-by: Li Yang \u003cleoli@freescale.com\u003e\nAcked-by: Kumar Gala \u003cgalak@kernel.crashing.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n" }, { "commit": "e6c7ecb64e08ef346cb7062b4a5421f00bc602bd", "tree": "73424d223391302a9a16df65378d78f25fd05929", "parents": [ "162b96e63e518aa6ff029ce23de12d7f027483bf" ], "author": { "name": "Ira Snyder", "email": "iws@ovro.caltech.edu", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "message": "fsldma: split apart external pause and request count features\n\nWhen using the Freescale DMA controller in external control mode, both the\nrequest count and external pause bits need to be setup correctly. This was\nbeing done with the same function.\n\nThe 83xx controller lacks the external pause feature, but has a similar\nfeature called external start. This feature requires that the request count\nbits be setup correctly.\n\nSplit the function into two parts, to make it possible to use the external\nstart feature on the 83xx controller.\n\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "162b96e63e518aa6ff029ce23de12d7f027483bf", "tree": "532191d0cef7cf975b70a07b1c69a293d6f552f7", "parents": [ "0803172778901e24a75ab074798d98c2b7411559" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "message": "ioat2,3: cacheline align software descriptor allocations\n\nAll the necessary fields for handling an ioat2,3 ring entry can fit into\none cacheline. Move -\u003elen prior to -\u003etxd in struct ioat_ring_ent, and\nmove allocation of these entries to a hw-cache-aligned kmem cache to\nreduce the number of cachelines dirtied for descriptor management.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "0803172778901e24a75ab074798d98c2b7411559", "tree": "a3e1d0cf4228d65dc1fac2ad56f3beb6b6f3474b", "parents": [ "1979b186b80449ac6574d97c254b694c8a99b703" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "message": "dmaengine: kill tx_list\n\nThe tx_list attribute of struct dma_async_tx_descriptor is common to\nmost, but not all dma driver implementations. None of the upper level\ncode (dmaengine/async_tx) uses it, so allow drivers to implement it\nlocally if they need it. This saves sizeof(struct list_head) bytes for\ndrivers that do not manage descriptors with a linked list (e.g.: ioatdma\nv2,3).\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "1979b186b80449ac6574d97c254b694c8a99b703", "tree": "9befdf33c11c0b0e4ce6720c7c81efeb7005ce7c", "parents": [ "285a3c71640ad7101b7237b8fbaa4ead22c6551c" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:03 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:03 2009 -0700" }, "message": "txx9dmac: implement a private tx_list\n\nDrop txx9dmac\u0027s use of tx_list from struct dma_async_tx_descriptor in\npreparation for removal of this field.\n\nCc: Atsushi Nemoto \u003canemo@mba.ocn.ne.jp\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "285a3c71640ad7101b7237b8fbaa4ead22c6551c", "tree": "d4da48d227f2bc069cb3c1074c6267b5e29426e1", "parents": [ "64203b67274680e95e0c2eec935a22fc94e9ecb5" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:03 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:03 2009 -0700" }, "message": "at_hdmac: implement a private tx_list\n\nDrop at_hdmac\u0027s use of tx_list from struct dma_async_tx_descriptor in\npreparation for removal of this field.\n\nCc: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "64203b67274680e95e0c2eec935a22fc94e9ecb5", "tree": "93d56edbf3ecccdd0cffae3a20c3a7b7dd17cd5a", "parents": [ "ea25968a32a621b02c3715d6b649f0c6ef53c24e" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:03 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:03 2009 -0700" }, "message": "mv_xor: implement a private tx_list\n\nDrop mv_xor\u0027s use of tx_list from struct dma_async_tx_descriptor in\npreparation for removal of this field.\n\nCc: Saeed Bishara \u003csaeed@marvell.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "ea25968a32a621b02c3715d6b649f0c6ef53c24e", "tree": "8da75c38c0ac0690eb03e89ccf146d062ba4d855", "parents": [ "308136d1abcb2d759bac40ed4f5d42ac4af59d8b" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:02 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:02 2009 -0700" }, "message": "ioat: implement a private tx_list\n\nDrop ioatdma\u0027s use of tx_list from struct dma_async_tx_descriptor in\npreparation for removal of this field.\n\nCc: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" } ], "next": "308136d1abcb2d759bac40ed4f5d42ac4af59d8b" }