)]}' { "log": [ { "commit": "73017a542fd2e92a02464eb8b727c200c97e6c0c", "tree": "39063d55b4110c321433678169078ea86b81781f", "parents": [ "dc28094b905a872f8884f1f1c48ca86b3b78583a" ], "author": { "name": "Paul Gortmaker", "email": "paul.gortmaker@windriver.com", "time": "Sun Jul 31 16:14:14 2011 -0400" }, "committer": { "name": "Paul Gortmaker", "email": "paul.gortmaker@windriver.com", "time": "Mon Oct 31 19:30:50 2011 -0400" }, "message": "arm: fix implicit module.h users by adding it to arch/arm as required.\n\nThese files will fail to compile if we dont clean them up in advance\nand have them include the appropriate headers they need.\n\nSigned-off-by: Paul Gortmaker \u003cpaul.gortmaker@windriver.com\u003e\n" }, { "commit": "ecea4ab6d3d8bb4122522398200f1cd2a06af6d5", "tree": "299301ffcd3e45203a865fa1d86c1f695a90a280", "parents": [ "d91ef63bd5ae52f642c0a0369d57671977508e3d" ], "author": { "name": "Paul Gortmaker", "email": "paul.gortmaker@windriver.com", "time": "Fri Jul 22 10:58:34 2011 -0400" }, "committer": { "name": "Paul Gortmaker", "email": "paul.gortmaker@windriver.com", "time": "Mon Oct 31 19:30:49 2011 -0400" }, "message": "arm: convert core files from module.h to export.h\n\nMany of the core ARM kernel files are not modules, but just\nincluding module.h for exporting symbols. Now these files can\nuse the lighter footprint export.h for this role.\n\nThere are probably lots more, but ARM files of mach-* and plat-*\ndon\u0027t get coverage via a simple yesconfig build. They will have\nto be cleaned up and tested via using their respective configs.\n\nSigned-off-by: Paul Gortmaker \u003cpaul.gortmaker@windriver.com\u003e\n" }, { "commit": "d91ef63bd5ae52f642c0a0369d57671977508e3d", "tree": "77d06c4ffe25dbe7a8ff34670f175def4b130dbd", "parents": [ "3d46cceb6082bcc08290365f21043faf342a928a" ], "author": { "name": "Paul Gortmaker", "email": "paul.gortmaker@windriver.com", "time": "Fri Jul 22 10:29:08 2011 -0400" }, "committer": { "name": "Paul Gortmaker", "email": "paul.gortmaker@windriver.com", "time": "Mon Oct 31 19:30:48 2011 -0400" }, "message": "arm: remove several unnecessary module.h include instances\n\nBuilding these files does not reveal a hidden need for\nany of these. Since module.h brings in the whole kitchen\nsink, it just needlessly adds 30k+ lines to the cpp burden.\n\nThere are probably lots more, but ARM files of mach-* and plat-*\ndon\u0027t get coverage via a simple yesconfig build. They will have\nto be cleaned up and tested via using their respective configs.\n\nSigned-off-by: Paul Gortmaker \u003cpaul.gortmaker@windriver.com\u003e\n" }, { "commit": "d44b28c49e7ab3baf280100ab86d8e7ef9204e45", "tree": "b8bf7e8b8ec02ce8bdbb016ad43c20961f487cd7", "parents": [ "ce8b9d25c94980cc05e59730c97b2ef0285587b4" ], "author": { "name": "Paul Gortmaker", "email": "paul.gortmaker@windriver.com", "time": "Sun Jul 31 10:52:44 2011 -0400" }, "committer": { "name": "Paul Gortmaker", "email": "paul.gortmaker@windriver.com", "time": "Mon Oct 31 19:30:45 2011 -0400" }, "message": "arm: fix implicit memset/string.h usage in various arch/arm files\n\nTo fix things like this:\n\narch/arm/mach-omap2/usb-tusb6010.c:58: error: implicit declaration of function \u0027memset\u0027\narch/arm/kernel/leds.c:40: error: implicit declaration of function \u0027strcspn\u0027\narch/arm/kernel/leds.c:40: warning: incompatible implicit declaration of built-in function \u0027strcspn\u0027\narch/arm/kernel/leds.c:45: error: implicit declaration of function \u0027strncmp\u0027\narch/arm/kernel/leds.c:55: error: implicit declaration of function \u0027strlen\u0027\narch/arm/kernel/leds.c:55: warning: incompatible implicit declaration of built-in function \u0027strlen\u0027\narch/arm/mach-omap2/clockdomain.c:52: error: implicit declaration of function \u0027strcmp\u0027\n\nSigned-off-by: Paul Gortmaker \u003cpaul.gortmaker@windriver.com\u003e\n" }, { "commit": "ce8b9d25c94980cc05e59730c97b2ef0285587b4", "tree": "c97ed080536b1ecc15248d37aa46652b3a5cd9e4", "parents": [ "ead53f22dc646d91a1b6201b9f44dd47d7d88c34" ], "author": { "name": "Paul Gortmaker", "email": "paul.gortmaker@windriver.com", "time": "Mon Jul 18 12:03:53 2011 -0400" }, "committer": { "name": "Paul Gortmaker", "email": "paul.gortmaker@windriver.com", "time": "Mon Oct 31 19:30:45 2011 -0400" }, "message": "arm: add elf.h to arch/arm/kernel/ptrace.c\n\nIt was implicitly getting it via an implicit presence of module.h\nbut when we clean that up, we\u0027ll get a bunch of lines like this:\n\narch/arm/kernel/ptrace.c:764: error: \u0027NT_PRSTATUS\u0027 undeclared here (not in a function)\narch/arm/kernel/ptrace.c:765: error: \u0027ELF_NGREG\u0027 undeclared here (not in a function)\narch/arm/kernel/ptrace.c:776: error: \u0027NT_PRFPREG\u0027 undeclared here (not in a function)\n\nSigned-off-by: Paul Gortmaker \u003cpaul.gortmaker@windriver.com\u003e\n" }, { "commit": "1fdb24e969110fafea36d3b393bea438f702c87f", "tree": "47a1dfef8a259e7922285315f8a02d31b4efe2f1", "parents": [ "f362f98e7c445643d27c610bb7a86b79727b592e", "531a6a941745e1e045dd2a6bd09e1dc01247a5f3" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Oct 28 12:02:27 2011 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Oct 28 12:02:27 2011 -0700" }, "message": "Merge branch \u0027devel-stable\u0027 of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm\n\n* \u0027devel-stable\u0027 of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm: (178 commits)\n ARM: 7139/1: fix compilation with CONFIG_ARM_ATAG_DTB_COMPAT and large TEXT_OFFSET\n ARM: gic, local timers: use the request_percpu_irq() interface\n ARM: gic: consolidate PPI handling\n ARM: switch from NO_MACH_MEMORY_H to NEED_MACH_MEMORY_H\n ARM: mach-s5p64x0: remove mach/memory.h\n ARM: mach-s3c64xx: remove mach/memory.h\n ARM: plat-mxc: remove mach/memory.h\n ARM: mach-prima2: remove mach/memory.h\n ARM: mach-zynq: remove mach/memory.h\n ARM: mach-bcmring: remove mach/memory.h\n ARM: mach-davinci: remove mach/memory.h\n ARM: mach-pxa: remove mach/memory.h\n ARM: mach-ixp4xx: remove mach/memory.h\n ARM: mach-h720x: remove mach/memory.h\n ARM: mach-vt8500: remove mach/memory.h\n ARM: mach-s5pc100: remove mach/memory.h\n ARM: mach-tegra: remove mach/memory.h\n ARM: plat-tcc: remove mach/memory.h\n ARM: mach-mmp: remove mach/memory.h\n ARM: mach-cns3xxx: remove mach/memory.h\n ...\n\nFix up mostly pretty trivial conflicts in:\n - arch/arm/Kconfig\n - arch/arm/include/asm/localtimer.h\n - arch/arm/kernel/Makefile\n - arch/arm/mach-shmobile/board-ap4evb.c\n - arch/arm/mach-u300/core.c\n - arch/arm/mm/dma-mapping.c\n - arch/arm/mm/proc-v7.S\n - arch/arm/plat-omap/Kconfig\nlargely due to some CONFIG option renaming (ie CONFIG_PM_SLEEP -\u003e\nCONFIG_ARM_CPU_SUSPEND for the arm-specific suspend code etc) and\naddition of NEED_MACH_MEMORY_H next to HAVE_IDE.\n" }, { "commit": "3cfef9524677a4ecb392d6fbffe6ebce6302f1d4", "tree": "88647d9dc50d634dee9cfeb7f354d620977a2f33", "parents": [ "982653009b883ef1529089e3e6f1ae2fee41cbe2", "68cc3990a545dc0da221b4844dd8b9c06623a6c5" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Oct 26 16:17:32 2011 +0200" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Oct 26 16:17:32 2011 +0200" }, "message": "Merge branch \u0027core-locking-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip\n\n* \u0027core-locking-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (27 commits)\n rtmutex: Add missing rcu_read_unlock() in debug_rt_mutex_print_deadlock()\n lockdep: Comment all warnings\n lib: atomic64: Change the type of local lock to raw_spinlock_t\n locking, lib/atomic64: Annotate atomic64_lock::lock as raw\n locking, x86, iommu: Annotate qi-\u003eq_lock as raw\n locking, x86, iommu: Annotate irq_2_ir_lock as raw\n locking, x86, iommu: Annotate iommu-\u003eregister_lock as raw\n locking, dma, ipu: Annotate bank_lock as raw\n locking, ARM: Annotate low level hw locks as raw\n locking, drivers/dca: Annotate dca_lock as raw\n locking, powerpc: Annotate uic-\u003elock as raw\n locking, x86: mce: Annotate cmci_discover_lock as raw\n locking, ACPI: Annotate c3_lock as raw\n locking, oprofile: Annotate oprofilefs lock as raw\n locking, video: Annotate vga console lock as raw\n locking, latencytop: Annotate latency_lock as raw\n locking, timer_stats: Annotate table_lock as raw\n locking, rwsem: Annotate inner lock as raw\n locking, semaphores: Annotate inner lock as raw\n locking, sched: Annotate thread_group_cputimer as raw\n ...\n\nFix up conflicts in kernel/posix-cpu-timers.c manually: making\ncputimer-\u003ecputime a raw lock conflicted with the ABBA fix in commit\nbcd5cff7216f (\"cputimer: Cure lock inversion\").\n" }, { "commit": "bdf4e9482360a3ddc1619efbd5d1c928ede8c3fa", "tree": "b02319e809c5b8abfca85409a11472775e27f597", "parents": [ "06afb1a087d49ae0f676b2e5b9ffe5f4b3aba355", "eb0474544bc16a9dab53b26abd846e86ba814eb1" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Oct 25 08:19:59 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Oct 25 08:19:59 2011 +0100" }, "message": "Merge branch \u0027misc\u0027 into for-linus\n\nConflicts:\n\tarch/arm/mach-integrator/integrator_ap.c\n" }, { "commit": "06afb1a087d49ae0f676b2e5b9ffe5f4b3aba355", "tree": "5377c063ed07aed23eb9da0bfecfca307f8da0bc", "parents": [ "c3b92c8787367a8bb53d57d9789b558f1295cc96", "7816e210a7e4681fb775bbb57bffbef3cc4aa456", "f73765fcb8bb79e80af58059441eb931679e68c0", "70e5f5efcc933af55a3a18efdb3b2edd3eb510ec", "91c2ebb90b1890abc648ba9dec5608cbc97e1cb9", "daece59689e76ed55d8863cae04993679a8e844e", "d7c5d0dcffb3b5702d9477faceff4b8398e6fed0", "a06f916b7a9b57447ceb875eb0a89f1a66b31bca" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Oct 25 08:19:29 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Oct 25 08:19:29 2011 +0100" }, "message": "Merge branches \u0027arnd-randcfg-fixes\u0027, \u0027debug\u0027, \u0027io\u0027 (early part), \u0027l2x0\u0027, \u0027p2v\u0027, \u0027pgt\u0027 (early part) and \u0027smp\u0027 into for-linus\n" }, { "commit": "eb0474544bc16a9dab53b26abd846e86ba814eb1", "tree": "d065ba5fce871af8b02a8a8b55625084548ea3a0", "parents": [ "6c5482d53f195d3ca61c9ec1be25b0f4a92575fe" ], "author": { "name": "Thomas Gleinxer", "email": "tglx@linutronix.de", "time": "Fri Oct 14 12:44:41 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Oct 23 21:22:58 2011 +0100" }, "message": "ARM: 7133/1: SMP: fix per cpu timer setup before the cpu is marked online\n\nThe problem is related to the early enabling of interrupts and the\nper cpu timer setup before the cpu is marked online. This doesn\u0027t\nneed to be done in order to call calibrate_delay().\n\ncalibrate_delay() monitors jiffies, which are updated from the CPU\nwhich is waiting for the new CPU to set the online bit.\n\nSo simply calibrate_delay() can be called on the new CPU just from\nthe interrupt disabled region and move the local timer setup after\nstored the cpu data and before enabling interrupts.\n\nThis solves both the cpu_online vs. cpu_active problem and the\naffinity setting of the per cpu timers.\n\nSigned-off-by: Thomas Gleinxer \u003ctglx@linutronix.de\u003e\nSigned-off-by: Kukjin Kim \u003ckgene.kim@samsung.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "34471a9168c8bfd7f0d00989a7b0797ad27d585e", "tree": "847af3ec746c6357902cf57c7e12ba55a35eed30", "parents": [ "cefd3e71efca6f4ef7f06f1fc507771d76072741", "28af690a284dfcb627bd69d0963db1c0f412cb8c" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Oct 23 14:42:30 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Oct 23 14:42:30 2011 +0100" }, "message": "Merge branch \u0027ppi-irq-core-for-rmk\u0027 of git://github.com/mzyngier/arm-platforms into devel-stable\n" }, { "commit": "28af690a284dfcb627bd69d0963db1c0f412cb8c", "tree": "6daa595281c87b5bfee4cca79492a724deb1cfbc", "parents": [ "292b293ceef2eda1f96f0c90b96e954d7bdabd1c" ], "author": { "name": "Marc Zyngier", "email": "marc.zyngier@arm.com", "time": "Fri Jul 22 12:52:37 2011 +0100" }, "committer": { "name": "Marc Zyngier", "email": "marc.zyngier@arm.com", "time": "Sun Oct 23 13:32:33 2011 +0100" }, "message": "ARM: gic, local timers: use the request_percpu_irq() interface\n\nThis patch remove the hardcoded link between local timers and PPIs,\nand convert the PPI users (TWD, MCT and MSM timers) to the new\n*_percpu_irq interface. Also some collateral cleanup\n(local_timer_ack() is gone, and the interrupt handler is strictly\nprivate to each driver).\n\nPPIs are now useable for more than just the local timers.\n\nAdditional testing by David Brown (msm8250 and msm8660) and\nShawn Guo (imx6q).\n\nCc: David Brown \u003cdavidb@codeaurora.org\u003e\nCc: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nAcked-by: David Brown \u003cdavidb@codeaurora.org\u003e\nTested-by: David Brown \u003cdavidb@codeaurora.org\u003e\nTested-by: Shawn Guo \u003cshawn.guo@linaro.org\u003e\nSigned-off-by: Marc Zyngier \u003cmarc.zyngier@arm.com\u003e\n" }, { "commit": "292b293ceef2eda1f96f0c90b96e954d7bdabd1c", "tree": "931da77e74e1aee404ffb61f8ffe2f6acb73f80c", "parents": [ "88b6fc8c57055590d8e9538f6faa85483db8c366" ], "author": { "name": "Marc Zyngier", "email": "marc.zyngier@arm.com", "time": "Wed Jul 20 16:24:14 2011 +0100" }, "committer": { "name": "Marc Zyngier", "email": "marc.zyngier@arm.com", "time": "Sun Oct 23 13:32:29 2011 +0100" }, "message": "ARM: gic: consolidate PPI handling\n\nPPI handling is a bit of an odd beast. It uses its own low level\nhandling code and is hardwired to the local timers (hence lacking\na registration interface).\n\nInstead, switch the low handling to the normal SPI handling code.\nPPIs are handled by the handle_percpu_devid_irq flow.\n\nThis also allows the removal of some duplicated code.\n\nCc: Kukjin Kim \u003ckgene.kim@samsung.com\u003e\nCc: David Brown \u003cdavidb@codeaurora.org\u003e\nCc: Bryan Huntsman \u003cbryanh@codeaurora.org\u003e\nCc: Tony Lindgren \u003ctony@atomide.com\u003e\nCc: Paul Mundt \u003clethal@linux-sh.org\u003e\nCc: Magnus Damm \u003cmagnus.damm@gmail.com\u003e\nCc: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nAcked-by: David Brown \u003cdavidb@codeaurora.org\u003e\nTested-by: David Brown \u003cdavidb@codeaurora.org\u003e\nTested-by: Shawn Guo \u003cshawn.guo@linaro.org\u003e\nSigned-off-by: Marc Zyngier \u003cmarc.zyngier@arm.com\u003e\n" }, { "commit": "b55fa18817743c3c4aef14f0c6fc0e21d7bc1e62", "tree": "13f32c0c822db2e6b763c4e3272aadef5999951b", "parents": [ "628e1110feebeb834359fd6f44ec7e346bdf9611" ], "author": { "name": "Afzal Mohammed", "email": "afzal@ti.com", "time": "Thu Oct 20 19:32:07 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Oct 20 22:03:57 2011 +0100" }, "message": "ARM: 7137/1: Fix error upon adding LL debug\n\nUpon adding new board LL debug support, if the resultant code\naddition would not cause PC relative offset of \"hexbuf\" from\n\"adr r2, hexbuf\" (+2) instruction to be representable in a\nshifted 8-bit value (hence indirectly putting higher aligment\nrequirement on larger offsets), following error occurs,\n\narch/arm/kernel/debug.S: Assembler messages:\narch/arm/kernel/debug.S:138: Error: invalid constant (428) after fixup\n\nFix it by bringing \"hexbuf\" closer so that \"adr\"\ncan have the offset.\n\nSigned-off-by: Afzal Mohammed \u003cafzal@ti.com\u003e\nAcked-by: Tony Lindgren \u003ctony@atomide.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "cefd3e71efca6f4ef7f06f1fc507771d76072741", "tree": "d76cb7969435d5eccdbd3d081555d0a8203ede4a", "parents": [ "a26bce1220a4c5a7a074a779e6aad3cae63a94f7", "0cdc8b921d68817b687755b4f6ae20cd8ff1d026" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Oct 18 13:40:54 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Oct 18 13:40:54 2011 +0100" }, "message": "Merge branch \u0027mach_memory_h\u0027 of git://git.linaro.org/people/nico/linux into devel-stable\n" }, { "commit": "2b034922af2caa19df86f0c502e76cb6f6e910f9", "tree": "023c9962c7f0a53037212b767fa50a8ea346ebec", "parents": [ "7f94e9cc5e965519d865bf20215036f359a1e299" ], "author": { "name": "Lei Wen", "email": "adrian.wenl@gmail.com", "time": "Fri Sep 23 09:04:09 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Oct 17 09:13:41 2011 +0100" }, "message": "ARM: 7098/1: kdump: copy kernel relocation code at the kexec prepare stage\n\nThis copy really don\u0027t need to do at the very second before the kernel\nwould crash.\n\nSigned-off-by: Lei Wen \u003cleiwen@marvell.com\u003e\nAcked-by: Simon Horman \u003chorms@verge.net.au\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "7f94e9cc5e965519d865bf20215036f359a1e299", "tree": "0c3e4254e4d11255b15c64dcc613599f0a149f83", "parents": [ "0744a3ee37784dfda0025963716a36c3f1e3adcc" ], "author": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Tue Aug 23 22:22:11 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Oct 17 09:13:41 2011 +0100" }, "message": "ARM: 7062/1: cache: detect PIPT I-cache using CTR\n\nThe Cache Type Register L1Ip field identifies I-caches with a PIPT\npolicy using the encoding 11b.\n\nThis patch extends the cache policy parsing to identify PIPT I-caches\ncorrectly and prevent them from being treated as VIPT aliasing in cases\nwhere they are sufficiently large.\n\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "0744a3ee37784dfda0025963716a36c3f1e3adcc", "tree": "0f84ecdbda2a0abf8cf12031fb47cc98ab56eef1", "parents": [ "87e040b6456fd3416a1f6831c1eedaef5c0a94ff" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Dec 20 10:37:50 2010 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Oct 17 09:13:41 2011 +0100" }, "message": "ARM: platform fixups: remove mdesc argument to fixup function\n\nGet rid of the mdesc pointer in the fixup function call. No one uses\nthe mdesc pointer, it shouldn\u0027t be modified anyway, and we can\u0027t wrap\nit, so let\u0027s remove it.\n\nPlatform files found by:\n\n $ regexp\u003d$(git grep -h \u0027\\.fixup.*\u003d\u0027 arch/arm |\n\t\tsed \u0027s!.*\u003d *\\([^,]*\\),* *!\\1!\u0027 | sort -u |\n\t\ttr \u0027\\n\u0027 \u0027|\u0027 | sed \u0027s,|$,,;s,|,\\\\|,g\u0027)\n $ git grep $regexp arch/arm\n\nAcked-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "87e040b6456fd3416a1f6831c1eedaef5c0a94ff", "tree": "6a532e73b33c60d0f8b57d0954a055de4a243120", "parents": [ "a675002c797815ec5df4a89748d8cab83158b11d" ], "author": { "name": "Simon Glass", "email": "sjg@chromium.org", "time": "Tue Aug 16 23:44:26 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Oct 17 09:13:41 2011 +0100" }, "message": "ARM: 7017/1: Use generic BUG() handler\n\nARM uses its own BUG() handler which makes its output slightly different\nfrom other archtectures.\n\nOne of the problems is that the ARM implementation doesn\u0027t report the function\nwith the BUG() in it, but always reports the PC being in __bug(). The generic\nimplementation doesn\u0027t have this problem.\n\nCurrently we get something like:\n\nkernel BUG at fs/proc/breakme.c:35!\nUnable to handle kernel NULL pointer dereference at virtual address 00000000\n...\nPC is at __bug+0x20/0x2c\n\nWith this patch it displays:\n\nkernel BUG at fs/proc/breakme.c:35!\nInternal error: Oops - undefined instruction: 0 [#1] PREEMPT SMP\n...\nPC is at write_breakme+0xd0/0x1b4\n\nThis implementation uses an undefined instruction to implement BUG, and sets up\na bug table containing the relevant information. Many versions of gcc do not\nsupport %c properly for ARM (inserting a # when they shouldn\u0027t) so we work\naround this using distasteful macro magic.\n\nv1: Initial version to replace existing ARM BUG() implementation with something\nmore similar to other architectures.\n\nv2: Add Thumb support, remove backtrace whitespace output changes. Change to\nuse macros instead of requiring the asm %d flag to work (thanks to\nDave Martin \u003cdave.martin@linaro.org\u003e)\n\nv3: Remove old BUG() implementation in favor of this one.\nRemove the Backtrace: message (will submit this separately).\nUse ARM_EXIT_KEEP() so that some architectures can dump exit text at link time\nthanks to Stephen Boyd \u003csboyd@codeaurora.org\u003e (although since we always\ndefine GENERIC_BUG this might be academic.)\nRebase to linux-2.6.git master.\n\nv4: Allow BUGS in modules (these were not reported correctly in v3)\n(thanks to Stephen Boyd \u003csboyd@codeaurora.org\u003e for suggesting that.)\nRemove __bug() as this is no longer needed.\n\nv5: Add %progbits as the section flags.\n\nSigned-off-by: Simon Glass \u003csjg@chromium.org\u003e\nReviewed-by: Stephen Boyd \u003csboyd@codeaurora.org\u003e\nTested-by: Stephen Boyd \u003csboyd@codeaurora.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "b380ab4f85d641574d91b12b333848a0731a497c", "tree": "ee8db08db4cef2369d0221ea5f65162c729aa55c", "parents": [ "b3377d1865723cea5334954e6ffcb2182b6689c8" ], "author": { "name": "Laura Abbott", "email": "lauraa@codeaurora.org", "time": "Wed Aug 31 02:04:06 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Oct 17 09:12:41 2011 +0100" }, "message": "ARM: 7068/1: process: change from __backtrace to dump_stack in show_regs\n\nCurrently, show_regs calls __backtrace which does\nnothing if CONFIG_FRAME_POINTER is not set. Switch to\ndump_stack which handles both CONFIG_FRAME_POINTER and\nCONFIG_ARM_UNWIND correctly.\n\n__backtrace is now superseded by dump_stack in general\nand show_regs was the last caller so remove __backtrace\nas well.\n\nSigned-off-by: Laura Abbott \u003clauraa@codeaurora.org\u003e\nAcked-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "ef4c53687e0adf5409896c4fa688b15f8d4dc0c0", "tree": "d5f472200e98e4863f1b34c8308f719ffc87f606", "parents": [ "85519189df91c8aa9c368de0bdcfd7812200e614" ], "author": { "name": "Dave Martin", "email": "dave.martin@linaro.org", "time": "Fri Aug 19 18:00:08 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Oct 17 09:12:41 2011 +0100" }, "message": "ARM: 7031/1: entry: Fix Thumb-2 undef handling for multi-CPU kernels\n\nWhen v6 and \u003e\u003dv7 boards are supported in the same kernel, the\n__und_usr code currently makes a build-time assumption that Thumb-2\ninstructions occurring in userspace don\u0027t need to be supported.\nStrictly speaking this is incorrect.\n\nThis patch fixes the above case by doing a run-time check on the\nCPU architecture in these cases. This only affects kernels which\nsupport v6 and \u003e\u003dv7 CPUs together: plain v6 and plain v7 kernels\nare unaffected.\n\nSigned-off-by: Dave Martin \u003cdave.martin@linaro.org\u003e\nReviewed-by: Jon Medhurst \u003ctixy@yxit.co.uk\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "85519189df91c8aa9c368de0bdcfd7812200e614", "tree": "2f57a4688097542e977497549420e081053f77e6", "parents": [ "2ecccf90f2a6d821af4d33f086d59895e5d3bedc" ], "author": { "name": "Dave Martin", "email": "dave.martin@linaro.org", "time": "Fri Aug 19 17:59:27 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Oct 17 09:12:40 2011 +0100" }, "message": "ARM: 7030/1: entry: Remove unnecessary masking when decoding Thumb-2 instructions\n\nWhen testing whether a Thumb-2 instruction is 32 bits long or not,\nthe masking done in order to test bits 11-15 of the first\ninstruction halfword won\u0027t affect the result of the comparison, so\nremove it.\n\nSigned-off-by: Dave Martin \u003cdave.martin@linaro.org\u003e\nReviewed-by: Jon Medhurst \u003ctixy@yxit.co.uk\u003e\nAcked-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "2ecccf90f2a6d821af4d33f086d59895e5d3bedc", "tree": "d12438e595a0cfa5051187f69a1badddb1b317b3", "parents": [ "40c6d8aee40e373db75e6b0b4230fc8e8259d7a6" ], "author": { "name": "Dave Martin", "email": "dave.martin@linaro.org", "time": "Fri Aug 19 17:58:35 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Oct 17 09:12:40 2011 +0100" }, "message": "ARM: 7029/1: Make cpu_architecture into a global variable\n\nThe CPU architecture really should not be changing at runtime, so\nmake it a global variable instead of a function.\n\nThe cpu_architecture() function declared in \u003casm/system.h\u003e remains\nthe correct way to read this variable from C code.\n\nSigned-off-by: Dave Martin \u003cdave.martin@linaro.org\u003e\nReviewed-by: Jon Medhurst \u003ctixy@yxit.co.uk\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "91c2ebb90b1890abc648ba9dec5608cbc97e1cb9", "tree": "b9f9934aa1b17f3529d2c6423cfacc54bb626724", "parents": [ "8d4e652d1b2539196efaef051956fa29e22e9c10" ], "author": { "name": "Barry Song", "email": "Baohua.Song@csr.com", "time": "Fri Sep 30 14:43:12 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Oct 17 09:11:51 2011 +0100" }, "message": "ARM: 7114/1: cache-l2x0: add resume entry for l2 in secure mode\n\nwe save the l2x0 registers at the first initialization, and platform codes\ncan get them to restore l2x0 status after wakeup.\n\nCc: Lorenzo Pieralisi \u003clorenzo.pieralisi@arm.com\u003e\nSigned-off-by: Barry Song \u003cBaohua.Song@csr.com\u003e\nReviewed-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nTested-by: Shawn Guo \u003cshawn.guo@linaro.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "5a567d78c437e3be1c512734cdfe64b4ae6b82d7", "tree": "5d3afefe2b64fb4d53cbf1ee460f39037d83b76b", "parents": [ "0af8aa0069e43f90d59666510342c05e97d8c4b8" ], "author": { "name": "Jamie Iles", "email": "jamie@jamieiles.com", "time": "Sat Oct 08 11:20:42 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Oct 17 09:02:44 2011 +0100" }, "message": "ARM: 7115/4: move __exception and friends to asm/exception.h\n\nThe definition of __exception_irq_entry for\nCONFIG_FUNCTION_GRAPH_TRACER\u003dy needs linux/ftrace.h, but this creates a\ncircular dependency with it\u0027s current home in asm/system.h. Create\nasm/exception.h and update all current users.\n\nv4:\t- rebase to rmk/for-next\nv3:\t- remove redundant includes of linux/ftrace.h\nv2:\t- document the usage restricitions of __exception*\n\nCc: Zoltan Devai \u003czdevai@gmail.com\u003e\nSigned-off-by: Jamie Iles \u003cjamie@jamieiles.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "0af8aa0069e43f90d59666510342c05e97d8c4b8", "tree": "9d5e75ed9c91f04d5a547bd884ca9c7f457fc1e9", "parents": [ "0b5a1b95dcdfa451125132d5ce3f79a27ffb0950" ], "author": { "name": "Shawn Guo", "email": "shawn.guo@linaro.org", "time": "Thu Oct 06 15:19:14 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Oct 17 09:02:44 2011 +0100" }, "message": "ARM: 7124/1: smp: Add a localtimer handler callable from C code\n\nIn order to be able to handle localtimer directly from C code instead of\nassembly code, introduce handle_local_timer(), which is modeled after\nhandle_IRQ().\n\nSigned-off-by: Shawn Guo \u003cshawn.guo@linaro.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "0b5a1b95dcdfa451125132d5ce3f79a27ffb0950", "tree": "0a2ae9da15b1a9789bf3cc3ccff37b961dacfc1b", "parents": [ "26a527e69d6e6077bff9e2cddcb08337ac33a52d" ], "author": { "name": "Shawn Guo", "email": "shawn.guo@linaro.org", "time": "Thu Oct 06 15:18:14 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Oct 17 09:02:43 2011 +0100" }, "message": "ARM: 7123/1: smp: Add an IPI handler callable from C code\n\nIn order to be able to handle IPI directly from C code instead of\nassembly code, introduce handle_IPI(), which is modeled after handle_IRQ().\n\nSigned-off-by: Marc Zyngier \u003cmarc.zyngier@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "26a527e69d6e6077bff9e2cddcb08337ac33a52d", "tree": "4515bfd0c960ea02cfff0019e265f05a809bba6f", "parents": [ "267840f3397fd9f6a2bdde14de38b9d29d525d7b" ], "author": { "name": "Shawn Guo", "email": "shawn.guo@linaro.org", "time": "Sun Sep 25 08:25:43 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Oct 17 09:02:43 2011 +0100" }, "message": "ARM: 7100/1: smp_scu: remove __init annotation from scu_enable()\n\nWhen Cortex-A9 MPCore resumes from Dormant or Shutdown modes,\nSCU needs to be re-enabled. This patch removes __init annotation\nfrom function scu_enable(), so that platform resume procedure can\ncall it to re-enable SCU.\n\nSigned-off-by: Shawn Guo \u003cshawn.guo@linaro.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "d6257288c4052465feeff7e283e35ec0ed06ca03", "tree": "e9dbc251dfb47716d592681d228bda73a3a63121", "parents": [ "c9018aab8eee24b993c12c7aff7fc99d3d73f298" ], "author": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Tue Aug 23 22:19:29 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Oct 17 09:02:43 2011 +0100" }, "message": "ARM: 7060/1: smp: populate logical CPU mapping during boot\n\nTo allow booting Linux on a CPU with physical ID !\u003d 0, we need to\nprovide a mapping from the logical CPU number to the physical CPU\nnumber.\n\nThis patch adds such a mapping and populates it during boot.\n\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "c9018aab8eee24b993c12c7aff7fc99d3d73f298", "tree": "9c03698cff4bda12364af7c84ed09122219bbc2c", "parents": [ "d0a77454c70d0449a5f87087deb8f0cb15145e90" ], "author": { "name": "Vincent Guittot", "email": "vincent.guittot@linaro.org", "time": "Mon Aug 08 13:21:59 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Mon Oct 17 09:02:43 2011 +0100" }, "message": "ARM: 7011/1: Add ARM cpu topology definition\n\nThe affinity between ARM processors is defined in the MPIDR register.\nWe can identify which processors are in the same cluster,\nand which ones have performance interdependency. We can define the\ncpu topology of ARM platform, that is then used by sched_mc and sched_smt.\n\nThe default state of sched_mc and sched_smt config is disable.\nWhen enabled, the behavior of the scheduler can be modified with\nsched_mc_power_savings and sched_smt_power_savings sysfs interfaces.\n\nChanges since v4 :\n* Remove unnecessary parentheses and blank lines\n\nChanges since v3 :\n* Update the format of printk message\n* Remove blank line\n\nChanges since v2 :\n* Update the commit message and some comments\n\nChanges since v1 :\n* Update the commit message\n* Add read_cpuid_mpidr in arch/arm/include/asm/cputype.h\n* Modify header of arch/arm/kernel/topology.c\n* Modify tests and manipulation of MPIDR\u0027s bitfields\n* Modify the place and dependancy of the config\n* Modify Noop functions\n\nSigned-off-by: Vincent Guittot \u003cvincent.guittot@linaro.org\u003e\nReviewed-by: Amit Kucheria \u003camit.kucheria@linaro.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "29a541f6c1f6e4a85628bb86071b9e72c9f8be2c", "tree": "9f132fd63c08266901f3427d624891ac7e2da7b7", "parents": [ "002ea9eefec98dada56fd5f8e432a4e8570c2a26" ], "author": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Mon Oct 03 18:30:53 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Oct 15 11:04:22 2011 +0100" }, "message": "ARM: 7117/1: perf: fix HW_CACHE_* events on Cortex-A9\n\nUsing COHERENT_LINE_{MISS,HIT} for cache misses and references\nrespectively is completely wrong. Instead, use the L1D events which\nare a better and more useful approximation despite ignoring instruction\ntraffic.\n\nReported-by: Alasdair Grant \u003calasdair.grant@arm.com\u003e\nReported-by: Matt Horsnell \u003cmatt.horsnell@arm.com\u003e\nReported-by: Michael Williams \u003cmichael.williams@arm.com\u003e\nCc: stable@kernel.org\nCc: Jean Pihet \u003cj-pihet@ti.com\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "a26bce1220a4c5a7a074a779e6aad3cae63a94f7", "tree": "b57a67eab4799e63e7fc699acd7682b8148ebbb8", "parents": [ "c825dda905bac330c2da7fabdf5c0ac28758b3cd" ], "author": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Fri Oct 07 15:57:55 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Oct 08 10:05:34 2011 +0100" }, "message": "ARM: 7127/1: hw_breakpoint: skip v7-specific reset on v6 cores\n\nARMv6 cores do not implement the DBGOSLAR register, so we don\u0027t need to\ntry and clear it on boot. Furthermore, the VCR is zeroed out of reset,\nso we don\u0027t need to zero it explicitly when a CPU comes online.\n\nTested-by: Marc Zyngier \u003cmarc.zyngier@arm.com\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "b214bea525c5b62f6f8984557022e4593c441205", "tree": "8c01cd9fbcff7d84245b840518946f20ba1cdb06", "parents": [ "06901bd83412db5a31de7526e637101ed0c2c472" ], "author": { "name": "Arnd Bergmann", "email": "arnd@arndb.de", "time": "Sun Sep 04 22:30:06 2011 +0200" }, "committer": { "name": "Arnd Bergmann", "email": "arnd@arndb.de", "time": "Sat Oct 01 21:11:29 2011 +0200" }, "message": "ARM: pci: always export pcibios_bus_to_resource\n\nSome PCI drivers call pcibios_bus_to_resource directly,\nbut it is only exported when CONFIG_HOTPLUG is set,\nbecause it was initially mean for pccard support.\n\nMoving the export out of the #ifdef lets us avoid these\nbuild errors:\n\nERROR: \"pcibios_bus_to_resource\" [drivers/video/vt8623fb.ko] undefined!\nERROR: \"pcibios_bus_to_resource\" [drivers/video/arkfb.ko] undefined!\nERROR: \"pcibios_bus_to_resource\" [drivers/video/s3fb.ko] undefined!\n\nSigned-off-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n" }, { "commit": "15e0d9e37c7fe9711b60f47221c394d45553ad8c", "tree": "fd46b3ef48612d8c39a80627ee5c8fa9c422e15e", "parents": [ "82b9c18dc0ee38b5c78c5d09b9cffc79d98613c5" ], "author": { "name": "Arnd Bergmann", "email": "arnd@arndb.de", "time": "Sat Oct 01 21:09:39 2011 +0200" }, "committer": { "name": "Arnd Bergmann", "email": "arnd@arndb.de", "time": "Sat Oct 01 21:09:39 2011 +0200" }, "message": "ARM: pm: let platforms select cpu_suspend support\n\nSupport for the cpu_suspend functions is only built-in\nwhen CONFIG_PM_SLEEP is enabled, but omap3/4, exynos4\nand pxa always call cpu_suspend when CONFIG_PM is enabled.\n\nSigned-off-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n" }, { "commit": "63216d3c235d662726d6f5c55ceca91c70bb3eda", "tree": "b9db375e61be2c55a1013bf75364a31493ebbc78", "parents": [ "c6a389f123b9f68d605bb7e0f9b32ec1e3e14132" ], "author": { "name": "Arnd Bergmann", "email": "arnd@arndb.de", "time": "Fri Jun 10 13:58:30 2011 +0000" }, "committer": { "name": "Arnd Bergmann", "email": "arnd@arndb.de", "time": "Sat Oct 01 21:08:26 2011 +0200" }, "message": "ARM: export rtc_lock for nvram driver\n\nThe rtc_lock is used by both the nvram and rtc drivers, so\nwe need to export it if at least one of the two is built,\nnot just for the rtc driver.\n\nSigned-off-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n" }, { "commit": "1b9f95f8ade9efc2bd49f0e7b9dc61a038ac3eef", "tree": "3e5d06f8e6a0b177ff2e201fb76fdf319a229f8e", "parents": [ "67f462b29310814a8de29d35b422a9ed41d5f39a" ], "author": { "name": "Nicolas Pitre", "email": "nicolas.pitre@linaro.org", "time": "Tue Jul 05 22:52:51 2011 -0400" }, "committer": { "name": "Nicolas Pitre", "email": "nico@fluxnic.net", "time": "Mon Sep 26 10:11:58 2011 -0400" }, "message": "ARM: prepare for removal of a bunch of \u003cmach/memory.h\u003e files\n\nWhen the CONFIG_NO_MACH_MEMORY_H symbol is selected by a particular\nmachine class, the machine specific memory.h include file is no longer\nused and can be removed. In that case the equivalent information can\nbe obtained dynamically at runtime by enabling CONFIG_ARM_PATCH_PHYS_VIRT\nor by specifying the physical memory address at kernel configuration time.\n\nIf/when all instances of mach/memory.h are removed then this symbol could\nbe removed.\n\nSigned-off-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\n" }, { "commit": "639da5ee374ba8f070690bbd355ca30139ce145a", "tree": "21ec04820d870a0cd21f257193057355baa3cbc1", "parents": [ "57c89707dae01e0142e7185b6e8ff71b120f4c4d" ], "author": { "name": "Nicolas Pitre", "email": "nicolas.pitre@linaro.org", "time": "Wed Aug 31 22:55:46 2011 -0400" }, "committer": { "name": "Nicolas Pitre", "email": "nico@fluxnic.net", "time": "Mon Sep 26 10:11:25 2011 -0400" }, "message": "ARM: add an extra temp register to the low level debugging addruart macro\n\nSome platforms (like OMAP not to name it) are doing rather complicated\nhacks just to determine the base UART address to use. Let\u0027s give their\naddruart macro some slack by providing an extra work register which will\nallow for much needed cleanups.\n\nThis is basically a no-op as this commit is only adding the extra argument\nto the macro but no one is using it yet.\n\nSigned-off-by: nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\nReviewed-by: Kevin Hilman \u003ckhilman@ti.com\u003e\n" }, { "commit": "b0a37dca72a05b7b579f288d8a67afeed96bffa5", "tree": "a3057a3debd078f569e90e709d7b320006d8cb32", "parents": [ "f70cac8d9c7125f83048f8b3d1c60f5a041a165c", "8e6f83bbdf770014c070c5a41c8e89617cb2a66b" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Sep 22 22:39:23 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Sep 22 22:39:23 2011 +0100" }, "message": "Merge branch \u0027pm\u0027 into devel-stable\n" }, { "commit": "f70cac8d9c7125f83048f8b3d1c60f5a041a165c", "tree": "0d0efd72c1a41f973a919b16aac1d8210ed1ee30", "parents": [ "4722cd7741c6404f967f7a7b8b666540b6c1663e", "08aab447c56a5388cf0c768da476ad022f00fef8" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Sep 21 08:48:33 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Sep 21 08:48:33 2011 +0100" }, "message": "Merge branch \u0027kprobes-test\u0027 of git://git.yxit.co.uk/linux into devel-stable\n" }, { "commit": "6760b109603c794e4bd281c0014fef069c019b6a", "tree": "f0656ff7de073301d75200264d672282e6b7f558", "parents": [ "4dfa33868d9f8595717047eb058322e0999691cc" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Sep 20 23:35:15 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Sep 20 23:42:31 2011 +0100" }, "message": "ARM: fix vmlinux.lds.S discarding sections\n\nWe are seeing linker errors caused by sections being discarded, despite\nthe linker script trying to keep them. The result is (eg):\n\n`.exit.text\u0027 referenced in section `.alt.smp.init\u0027 of drivers/built-in.o: defined in discarded section `.exit.text\u0027 of drivers/built-in.o\n`.exit.text\u0027 referenced in section `.alt.smp.init\u0027 of net/built-in.o: defined in discarded section `.exit.text\u0027 of net/built-in.o\n\nThis is the relevent part of the linker script (reformatted to make it\nclearer):\n| SECTIONS\n| {\n| /*\n| * unwind exit sections must be discarded before the rest of the\n| * unwind sections get included.\n| */\n| /DISCARD/ : {\n| *(.ARM.exidx.exit.text)\n| *(.ARM.extab.exit.text)\n| }\n| ...\n| .exit.text : {\n| *(.exit.text)\n| *(.memexit.text)\n| }\n| ...\n| /DISCARD/ : {\n| *(.exit.text)\n| *(.memexit.text)\n| *(.exit.data)\n| *(.memexit.data)\n| *(.memexit.rodata)\n| *(.exitcall.exit)\n| *(.discard)\n| *(.discard.*)\n| }\n| }\n\nNow, this is what the linker manual says about discarded output sections:\n\n| The special output section name `/DISCARD/\u0027 may be used to discard\n| input sections. Any input sections which are assigned to an output\n| section named `/DISCARD/\u0027 are not included in the output file.\n\nNo questions, no exceptions. It doesn\u0027t say \"unless they are listed\nbefore the /DISCARD/ section.\" Now, this is what asn-generic/vmlinux.lds.S\nsays:\n| /*\n| * Default discarded sections.\n| *\n| * Some archs want to discard exit text/data at runtime rather than\n| * link time due to cross-section references such as alt instructions,\n| * bug table, eh_frame, etc. DISCARDS must be the last of output\n| * section definitions so that such archs put those in earlier section\n| * definitions.\n| */\n\nAnd guess what - the list _always_ includes .exit.text etc.\n\nNow, what\u0027s actually happening is that the linker is reading the script,\nand it finds the first /DISCARD/ output section at the beginning of the\nscript. It continues reading the script, and finds the \u0027DISCARD\u0027 macro\nat the end, which having been postprocessed results in another\n/DISCARD/ output section. As the linker already contains the earlier\n/DISCARD/ output section, it adds it to that existing section, so it\neffectively is placed at the start. This can be seen by using the -M\noption to ld:\n\n| Linker script and memory map\n|\n| 0xc037c080 jiffies \u003d jiffies_64\n|\n| /DISCARD/\n| *(.ARM.exidx.exit.text)\n| *(.ARM.extab.exit.text)\n| *(.exit.text)\n| *(.memexit.text)\n| *(.exit.data)\n| *(.memexit.data)\n| *(.memexit.rodata)\n| *(.exitcall.exit)\n| *(.discard)\n| *(.discard.*)\n|\n| 0xc0008000 . \u003d 0xc0008000\n|\n| .head.text 0xc0008000 0x1d0\n| 0xc0008000 _text \u003d .\n| *(.head.text)\n| .head.text 0xc0008000 0x1d0 arch/arm/kernel/head.o\n| 0xc0008000 stext\n|\n| .text 0xc0008200 0x2d78d0\n| 0xc0008200 _stext \u003d .\n| 0xc0008200 __exception_text_start \u003d .\n| *(.exception.text)\n| .exception.text\n| ...\n\nAs you can see, all the discarded sections are grouped together - and\nas a result of it being the first output section, they all appear before\nany other section.\n\nThe result is that not only is the unwind information discarded (as\nintended), but also the .exit.text, despite us wanting to have the\n.exit.text preserved.\n\nWe can\u0027t move the unwind information elsewhere, because it\u0027ll then be\nincluded even when we do actually discard the .exit.text (and similar)\nsections.\n\nSo, work around this by avoiding the generic DISCARDS macro, and instead\nconditionalize the sections to be discarded ourselves. This avoids the\nambiguity in how the linker assigns input sections to output sections,\nmaking our script less dependent on undocumented linker behaviour.\n\nReported-by: Rob Herring \u003crobherring2@gmail.com\u003e\nTested-by: Mark Brown \u003cbroonie@opensource.wolfsonmicro.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "8e6f83bbdf770014c070c5a41c8e89617cb2a66b", "tree": "c8c66226bd52a6b26229f0a95bf45851bef8974b", "parents": [ "abda1bd5f4e04054ce083c298fcd68a743e9df03" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Sep 01 11:57:59 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Sep 20 23:33:47 2011 +0100" }, "message": "ARM: pm: add L2 cache cleaning for suspend\n\nWe need to ensure that state is pushed out from the L2 cache when\nsuspending so that the resume paths can access their data before the\nMMU and caches have been re-initialized. Add the necessary calls to\n__cpu_suspend_save().\n\nTested-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nTested-by: Shawn Guo \u003cshawn.guo@linaro.org\u003e\nTested-by: Lorenzo Pieralisi \u003clorenzo.pieralisi@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "abda1bd5f4e04054ce083c298fcd68a743e9df03", "tree": "bdbc41f348d17a6cdb7259a0604d3f501801f3b6", "parents": [ "62b2d07c0ea9db40a1787d2d0ab49f03c3e0613c" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Sep 01 11:52:33 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Sep 20 23:33:44 2011 +0100" }, "message": "ARM: pm: convert some assembly to C\n\nConvert some of the sleep.S guts to C code, which makes it easier to\nuse our macros and to add L2 cache handling. We provide a helper\nfunction, __cpu_suspend_save(), which deals with saving the common\nstate, setting up for resume, and flushing caches.\n\nThe remainder left as assembly code is the saving of the CPU general\npurpose registers, and allocating space on the stack to save the CPU\nspecific registers and resume state.\n\nTested-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nTested-by: Shawn Guo \u003cshawn.guo@linaro.org\u003e\nTested-by: Lorenzo Pieralisi \u003clorenzo.pieralisi@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "62b2d07c0ea9db40a1787d2d0ab49f03c3e0613c", "tree": "55c2f172adea7fba22fdedbb922f4628ba9523df", "parents": [ "1aede681ac159884c77817d33230eed9185b6f6c" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Aug 31 23:26:18 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Sep 20 23:33:42 2011 +0100" }, "message": "ARM: pm: get rid of cpu_resume_turn_mmu_on\n\nWe don\u0027t require cpu_resume_turn_mmu_on as we can combine the ldr\ninstruction with the following code provided we ensure that\ncpu_resume_mmu is aligned for older CPUs. Note that we also align\nto a 32-byte boundary to ensure that the code can\u0027t cross a section\nboundary.\n\nTested-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nTested-by: Shawn Guo \u003cshawn.guo@linaro.org\u003e\nTested-by: Lorenzo Pieralisi \u003clorenzo.pieralisi@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "de8e71ca4f2e17329f6718ae88d5c8336cb249ee", "tree": "cec0f26c5f4c9efd601edc1ac716aed168f65e1f", "parents": [ "e8ce0eb5e2254b85415e4b58e73f24a5d13846a1" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Aug 27 22:39:09 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Sep 20 23:33:38 2011 +0100" }, "message": "ARM: pm: only use preallocated page table during resume\n\nOnly use the preallocated page table during the resume, not while\nsuspending. This avoids the overhead of having to switch unnecessarily\nto the resume page table in the suspend path.\n\nTested-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nTested-by: Shawn Guo \u003cshawn.guo@linaro.org\u003e\nTested-by: Lorenzo Pieralisi \u003clorenzo.pieralisi@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "e8ce0eb5e2254b85415e4b58e73f24a5d13846a1", "tree": "26aaee04d5a4bb872eea215f65073825258ecd76", "parents": [ "f5fa68d9674156ddaafa12a058ccc93c8866d5f9" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Aug 26 20:28:52 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Sep 20 23:33:36 2011 +0100" }, "message": "ARM: pm: preallocate a page table for suspend/resume\n\nPreallocate a page table and setup an identity mapping for the MMU\nenable code. This means we don\u0027t have to \"borrow\" a page table to\ndo this, avoiding complexities with L2 cache coherency.\n\nTested-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nTested-by: Shawn Guo \u003cshawn.guo@linaro.org\u003e\nTested-by: Lorenzo Pieralisi \u003clorenzo.pieralisi@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "f5fa68d9674156ddaafa12a058ccc93c8866d5f9", "tree": "51d3a321a18512c05491d321911f754d8b5cd2f8", "parents": [ "25904157168ddc8841748a729914f00e53d7e049" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Aug 27 11:17:36 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Sep 20 23:33:28 2011 +0100" }, "message": "ARM: pm: force non-zero return value from __cpu_suspend when aborting\n\nEnsure that the return value from __cpu_suspend is non-zero when\naborting. Zero indicates a successful suspend occurred.\n\nTested-by: Santosh Shilimkar \u003csantosh.shilimkar@ti.com\u003e\nTested-by: Shawn Guo \u003cshawn.guo@linaro.org\u003e\nTested-by: Lorenzo Pieralisi \u003clorenzo.pieralisi@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "08aab447c56a5388cf0c768da476ad022f00fef8", "tree": "9760a037d3ac283b9985c03479b170c386920434", "parents": [ "ce5af3bad0e03e94d01c002698ca6b2697b51836" ], "author": { "name": "Jon Medhurst", "email": "tixy@yxit.co.uk", "time": "Sun Aug 28 16:52:14 2011 +0100" }, "committer": { "name": "Jon Medhurst", "email": "tixy@yxit.co.uk", "time": "Tue Sep 20 18:17:44 2011 +0000" }, "message": "ARM: kprobes: Add introductory comment to test code\n\nSigned-off-by: Jon Medhurst \u003ctixy@yxit.co.uk\u003e\nAcked-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\n" }, { "commit": "ce5af3bad0e03e94d01c002698ca6b2697b51836", "tree": "34f47fdaba1cc0311deb804605dff8a6044698fc", "parents": [ "963780dfe390e80e148eb84f0c84a01533a64d28" ], "author": { "name": "Jon Medhurst", "email": "tixy@yxit.co.uk", "time": "Sun Aug 28 16:44:30 2011 +0100" }, "committer": { "name": "Jon Medhurst", "email": "tixy@yxit.co.uk", "time": "Tue Sep 20 18:17:44 2011 +0000" }, "message": "ARM: kprobes: Add some benchmarking to test module\n\nThese benchmarks show the basic speed of kprobes and verify the success\nof optimisations done to the emulation of typical function entry\ninstructions (i.e. push/stmdb).\n\nSigned-off-by: Jon Medhurst \u003ctixy@yxit.co.uk\u003e\nAcked-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\n" }, { "commit": "963780dfe390e80e148eb84f0c84a01533a64d28", "tree": "f89638b13a62b240886bc9363f857df6c8d4b290", "parents": [ "68f360e753668b61366b7b4b2a5aa77ac5157c37" ], "author": { "name": "Jon Medhurst", "email": "tixy@yxit.co.uk", "time": "Sun Aug 28 16:38:35 2011 +0100" }, "committer": { "name": "Jon Medhurst", "email": "tixy@yxit.co.uk", "time": "Tue Sep 20 18:17:44 2011 +0000" }, "message": "ARM: kprobes: Add decoding table test coverage analysis\n\nThis is used to verify that all combinations of CPU instructions\ndescribed by the kprobes decoding tables have a test case.\n\nSigned-off-by: Jon Medhurst \u003ctixy@yxit.co.uk\u003e\nAcked-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\n" }, { "commit": "68f360e753668b61366b7b4b2a5aa77ac5157c37", "tree": "41d56fb8ab553eb24da427f56e1cef6ad7da9830", "parents": [ "2c89240b630e94c1a5949860b7bfcf28130bd9c8" ], "author": { "name": "Jon Medhurst", "email": "tixy@yxit.co.uk", "time": "Sun Aug 28 16:35:11 2011 +0100" }, "committer": { "name": "Jon Medhurst", "email": "tixy@yxit.co.uk", "time": "Tue Sep 20 18:17:43 2011 +0000" }, "message": "ARM: kprobes: Add decoding table self-consistency tests\n\nThese check that the bitmask and match value used in the decoding tables\nare self consistent.\n\nSigned-off-by: Jon Medhurst \u003ctixy@yxit.co.uk\u003e\nAcked-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\n" }, { "commit": "2c89240b630e94c1a5949860b7bfcf28130bd9c8", "tree": "3a1ebde30df22d74fd31a2bcbf0ae40b0aaecfe9", "parents": [ "c0cc6df16394da020242a54d577848f9edd9dc50" ], "author": { "name": "Jon Medhurst", "email": "tixy@yxit.co.uk", "time": "Sat Aug 27 12:37:44 2011 +0100" }, "committer": { "name": "Jon Medhurst", "email": "tixy@yxit.co.uk", "time": "Tue Sep 20 18:17:43 2011 +0000" }, "message": "ARM: kprobes: Add exports for test code\n\nThe test code will be using kprobes\u0027 internal decoding tables so we\nneed to export these for when then the tests are compiled as a module.\n\nSigned-off-by: Jon Medhurst \u003ctixy@yxit.co.uk\u003e\nAcked-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\n" }, { "commit": "c0cc6df16394da020242a54d577848f9edd9dc50", "tree": "5a4da2ef6eeffad38d5771cd1ed8a000a6dbf037", "parents": [ "c7054aad538c18bc4c311e74a24cb2e205f02e04" ], "author": { "name": "Jon Medhurst", "email": "tixy@yxit.co.uk", "time": "Sat Aug 27 12:41:05 2011 +0100" }, "committer": { "name": "Jon Medhurst", "email": "tixy@yxit.co.uk", "time": "Tue Sep 20 18:17:43 2011 +0000" }, "message": "ARM: kprobes: Add ARM instruction simulation test cases\n\nSigned-off-by: Jon Medhurst \u003ctixy@yxit.co.uk\u003e\nAcked-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\n" }, { "commit": "c7054aad538c18bc4c311e74a24cb2e205f02e04", "tree": "436e5b6bf57c756ab1b6fd1c95064b49edb49334", "parents": [ "a43bc69b39484a448293f2eddc7e98ff15437414" ], "author": { "name": "Jon Medhurst", "email": "tixy@yxit.co.uk", "time": "Sat Aug 27 12:40:30 2011 +0100" }, "committer": { "name": "Jon Medhurst", "email": "tixy@yxit.co.uk", "time": "Tue Sep 20 18:17:43 2011 +0000" }, "message": "ARM: kprobes: Add Thumb instruction simulation test cases\n\nSigned-off-by: Jon Medhurst \u003ctixy@yxit.co.uk\u003e\nAcked-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\n" }, { "commit": "a43bc69b39484a448293f2eddc7e98ff15437414", "tree": "5c40ccc0517618971a1e9660b6816dbf2b6b096a", "parents": [ "9eed1797720ae633cf17b03dd804d8744f1d3b5c" ], "author": { "name": "Jon Medhurst", "email": "tixy@yxit.co.uk", "time": "Sun Aug 28 16:18:43 2011 +0100" }, "committer": { "name": "Jon Medhurst", "email": "tixy@yxit.co.uk", "time": "Tue Sep 20 18:17:43 2011 +0000" }, "message": "ARM: kprobes: Framework for instruction set test cases\n\nOn ARM we have to simulate/emulate CPU instructions in order to\nsinglestep them. This patch adds a framework which can be used to\nconstruct test cases for different instruction forms. It is described in\ndetail in the in-source comments of kprobes-test.c\n\nSigned-off-by: Jon Medhurst \u003ctixy@yxit.co.uk\u003e\nAcked-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\n" }, { "commit": "9eed1797720ae633cf17b03dd804d8744f1d3b5c", "tree": "c57a2a32f8129b602bda54f58afe9c723cf661c2", "parents": [ "4189bc71ff2cd3c1920b69a01f6796caf3f1edb3" ], "author": { "name": "Jon Medhurst", "email": "tixy@yxit.co.uk", "time": "Sun Aug 28 16:02:38 2011 +0100" }, "committer": { "name": "Jon Medhurst", "email": "tixy@yxit.co.uk", "time": "Tue Sep 20 18:17:43 2011 +0000" }, "message": "ARM: kprobes: Add basic API tests\n\nThese test that the different kinds of probes can be successfully placed\ninto ARM and Thumb code and that the handlers are called correctly when\nthis code is executed.\n\nSigned-off-by: Jon Medhurst \u003ctixy@yxit.co.uk\u003e\nAcked-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\n" }, { "commit": "f630c1bdfbf8fe423325beaf60027cfc7fd7c610", "tree": "9091179ae505fcb5aff937315c4f9c96602cba9a", "parents": [ "279b1e0fd90ef63c7acb34a5ca573f065a6fefb4" ], "author": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Thu Sep 15 11:45:15 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Sep 17 12:47:17 2011 +0100" }, "message": "ARM: 7091/1: errata: D-cache line maintenance operation by MVA may not succeed\n\nThis patch implements a workaround for erratum 764369 affecting\nCortex-A9 MPCore with two or more processors (all current revisions).\nUnder certain timing circumstances, a data cache line maintenance\noperation by MVA targeting an Inner Shareable memory region may fail to\nproceed up to either the Point of Coherency or to the Point of\nUnification of the system. This workaround adds a DSB instruction before\nthe relevant cache maintenance functions and sets a specific bit in the\ndiagnostic control register of the SCU.\n\nCc: \u003cstable@kernel.org\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nTested-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "4722cd7741c6404f967f7a7b8b666540b6c1663e", "tree": "877b7d8efe1e4e4ce48416186b4f45da3a5fccac", "parents": [ "1db3706b05b11abcf2673ffbed5ad43b4c90ed11", "4fb0d2ea397ab207fdecbd88ad0e37b36ce68a62" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Sep 16 21:45:16 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Sep 16 21:45:16 2011 +0100" }, "message": "Merge branch \u0027for-rmk\u0027 of git://linux-arm.org/linux-2.6-wd into devel-stable\n\nConflicts:\n\tarch/arm/mach-imx/mach-cpuimx27.c\n" }, { "commit": "1db3706b05b11abcf2673ffbed5ad43b4c90ed11", "tree": "09fa867d9d9db6ed475eaa889da143603441e1a6", "parents": [ "ad30a2bbdc20cf0111156e2aa6d2cc3e3c0d1893", "63d15148b6058ab0037343390e8918503ed81968" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Sep 15 00:02:28 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Sep 15 00:02:28 2011 +0100" }, "message": "Merge branch \u0027zImage_DTB_append\u0027 of git://git.linaro.org/people/nico/linux into devel-stable\n" }, { "commit": "bd31b85960a7fcb2d7ede216460b8da71a88411c", "tree": "f2ab1a1105705856c5cdfc71bcf3f7b5f897d30d", "parents": [ "a1741e7fcbc19a67520115df480ab17012cc3d0b" ], "author": { "name": "Thomas Gleixner", "email": "tglx@linutronix.de", "time": "Fri Jul 03 08:44:46 2009 -0500" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Tue Sep 13 11:12:14 2011 +0200" }, "message": "locking, ARM: Annotate low level hw locks as raw\n\nAnnotate the low level hardware locks which must not be preempted.\n\nIn mainline this change documents the low level nature of\nthe lock - otherwise there\u0027s no functional difference. Lockdep\nand Sparse checking will work as usual.\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "4fb0d2ea397ab207fdecbd88ad0e37b36ce68a62", "tree": "f0ebe12652b7ad1c2fc5016dfb31b633b7458a3f", "parents": [ "d12443363e590461655d4e9ccc31e40ad9078283", "7325eaec439cd0cc8c9b61b59d41d99abace1b23" ], "author": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Wed Aug 31 10:50:37 2011 +0100" }, "committer": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Wed Aug 31 10:50:37 2011 +0100" }, "message": "Merge branches \u0027hwbreak\u0027, \u0027perf/updates\u0027 and \u0027perf/system-pmus\u0027 into for-rmk\n" }, { "commit": "7325eaec439cd0cc8c9b61b59d41d99abace1b23", "tree": "802b05381659791a59db17827702f60202a4afbd", "parents": [ "0ce47080dfffe71edd433b35dcdada24c61079eb" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue Aug 23 11:59:49 2011 +0100" }, "committer": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Wed Aug 31 10:50:13 2011 +0100" }, "message": "ARM: perf: Remove unnecessary armpmu-\u003eenable()s\n\nCurrently, armpmu_enable iterates through the events for a given\ncounter set, calling armpmu-\u003eenable on each before calling\narmpmu-\u003estart to start the PMU\u0027s counters.\n\nAs armpmu-\u003eenable is called when each event is added, each event is\nalready configured in hardware. Due to this, calling armpmu-\u003eenable\nin armpmu_enable is unnecessary and confusing.\n\nThis patch removes the unnecessary calls to armpmu-\u003eenable.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\n" }, { "commit": "0ce47080dfffe71edd433b35dcdada24c61079eb", "tree": "93b84dc2cbfae0cb4dd59450a880db2c742b4117", "parents": [ "8be3f9a2385f91f7bf5c58f351e24b9247898e8f" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu May 19 10:07:57 2011 +0100" }, "committer": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Wed Aug 31 10:50:13 2011 +0100" }, "message": "ARM: perf: move arm_pmu into \u003casm/pmu.h\u003e\n\nCurrently, struct arm_pmu and related functions are only visible to\n{,arch/arm/}/kernel/perf_event.c. This prevents new drivers from using\nthe framework.\n\nThis patch moves declarations to asm/pmu.h, allowing new PMU drivers\nto use the framework.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nReviewed-by: Jamie Iles \u003cjamie@jamieiles.com\u003e\nReviewed-by: Ashwin Chaugule \u003cashwinc@codeaurora.org\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\n" }, { "commit": "8be3f9a2385f91f7bf5c58f351e24b9247898e8f", "tree": "5e293c7702f36b7eafd611bd5e8e710719643ac4", "parents": [ "3fc2c83087717dc88003428245d97b9d432fff2d" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue May 17 11:20:11 2011 +0100" }, "committer": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Wed Aug 31 10:50:12 2011 +0100" }, "message": "ARM: perf: remove cpu-related misnomers\n\nCurrently struct cpu_hw_events stores data on events running on a\nPMU associated with a CPU. As this data is general enough to be used\nfor system PMUs, this name is a misnomer, and may cause confusion when\nit is used for system PMUs.\n\nAdditionally, \u0027armpmu\u0027 is commonly used as a parameter name for an\ninstance of struct arm_pmu. The name is also used for a global instance\nwhich represents the CPU\u0027s PMU.\n\nAs cpu_hw_events is now not tied to CPU PMUs, it is renamed to\npmu_hw_events, with instances of it renamed similarly. As the global\n\u0027armpmu\u0027 is CPU-specfic, it is renamed to cpu_pmu. This should make it\nclearer which code is generic, and which is coupled with the CPU.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nReviewed-by: Jamie Iles \u003cjamie@jamieiles.com\u003e\nReviewed-by: Ashwin Chaugule \u003cashwinc@codeaurora.org\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\n" }, { "commit": "3fc2c83087717dc88003428245d97b9d432fff2d", "tree": "5dc3f1633c40df8a0b52f046754013355a9f65c1", "parents": [ "8a16b34e21199eb5fcf2c5050d3bc414fc5d6563" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Fri Jun 24 11:30:59 2011 +0100" }, "committer": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Wed Aug 31 10:50:11 2011 +0100" }, "message": "ARM: perf: remove event limit from pmu_hw_events\n\nCurrently the event accounting data in pmu_hw_events is stored in\nfixed-sized arrays within the structure.\n\nThis patch refactors the accounting data to allow any number of events\nto be managed.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nReviewed-by: Jamie Iles \u003cjamie@jamieiles.com\u003e\nReviewed-by: Ashwin Chaugule \u003cashwinc@codeaurora.org\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\n" }, { "commit": "8a16b34e21199eb5fcf2c5050d3bc414fc5d6563", "tree": "40a6c739285b7c1f389bf5597d9ae746080c0736", "parents": [ "e1f431b57ef9e4a68281540933fa74865cbb7a74" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Apr 28 16:27:54 2011 +0100" }, "committer": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Wed Aug 31 10:50:10 2011 +0100" }, "message": "ARM: perf: add support for multiple PMUs\n\nCurrently, a single static instance of struct pmu is used when\nregistering an ARM PMU with the main perf subsystem. This limits\nthe ARM perf code to supporting a single PMU.\n\nThis patch replaces the static struct pmu instance with a member\nvariable on struct arm_pmu. This provides bidirectional mapping\nbetween the two structs, and therefore allows for support of multiple\nPMUs. The function \u0027to_arm_pmu\u0027 is provided for convenience.\n\nPMU-generic functions are also updated to use the new mapping, and\nPMU-generic initialisation of the member variables is moved into a new\nfunction: armpmu_init.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nReviewed-by: Jamie Iles \u003cjamie@jamieiles.com\u003e\nReviewed-by: Ashwin Chaugule \u003cashwinc@codeaurora.org\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\n" }, { "commit": "e1f431b57ef9e4a68281540933fa74865cbb7a74", "tree": "895e018faee0a504c82c02b69a8784433c3a057e", "parents": [ "7ae18a5717cbbf1879bdd5b66d7009a9958e5aef" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Apr 28 15:47:10 2011 +0100" }, "committer": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Wed Aug 31 10:50:09 2011 +0100" }, "message": "ARM: perf: refactor event mapping\n\nCurrently mapping an event type to a hardware configuration value\ndepends on the data being pointed to from struct arm_pmu. These fields\n(cache_map, event_map, raw_event_mask) are currently specific to CPU\nPMUs, and do not serve the general case well.\n\nThis patch replaces the event map pointers on struct arm_pmu with a new\n\u0027map_event\u0027 function pointer. Small shim functions are used to reuse\nthe existing common code.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nReviewed-by: Jamie Iles \u003cjamie@jamieiles.com\u003e\nReviewed-by: Ashwin Chaugule \u003cashwinc@codeaurora.org\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\n" }, { "commit": "7ae18a5717cbbf1879bdd5b66d7009a9958e5aef", "tree": "877bd254703c985de0db15df76a2bf3ead1ea06f", "parents": [ "0f78d2d5ccf72ec834da6901886a40fd8e3b7615" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Mon Jun 06 10:37:50 2011 +0100" }, "committer": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Wed Aug 31 10:50:08 2011 +0100" }, "message": "ARM: perf: add type field to struct arm_pmu\n\nCurrently, the ARM perf code assumes all PMUs it will handle are\nCPU PMUs, having ARM_PMU_DEVICE_CPU hardcoded when reserving or\nreleasing hardware. This means that currently, the ARM perf code can\u0027t\nsupport system PMUs.\n\nThis patch adds a \u0027type\u0027 field to struct arm_pmu, which allows the code\nto reserve \u0026 release the hardware regardless of the PMU type.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nReviewed-by: Jamie Iles \u003cjamie@jamieiles.com\u003e\nReviewed-by: Ashwin Chaugule \u003cashwinc@codeaurora.org\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\n" }, { "commit": "0f78d2d5ccf72ec834da6901886a40fd8e3b7615", "tree": "da1262d040b2c10d95c6fc313b44e18801bcb4a3", "parents": [ "1b69beb7684c79673995607939d8acab51056b63" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Thu Apr 28 10:17:04 2011 +0100" }, "committer": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Wed Aug 31 10:50:07 2011 +0100" }, "message": "ARM: perf: lock PMU registers per-CPU\n\nCurrently, a single lock serialises access to CPU PMU registers. This\nglobal locking is unnecessary as PMU registers are local to the CPU\nthey monitor.\n\nThis patch replaces the global lock with a per-CPU lock. As the lock is\nin struct cpu_hw_events, PMUs providing a single cpu_hw_events instance\ncan be locked globally.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nReviewed-by: Jamie Iles \u003cjamie@jamieiles.com\u003e\nReviewed-by: Ashwin Chaugule \u003cashwinc@codeaurora.org\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\n" }, { "commit": "1b69beb7684c79673995607939d8acab51056b63", "tree": "20e15b0d5d54866190e8fb2599ff5ebfb73317ba", "parents": [ "92f701e1f429e007f9619469d548022061c41ecc" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Mon Aug 08 14:56:02 2011 +0100" }, "committer": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Wed Aug 31 10:50:06 2011 +0100" }, "message": "ARM: perf: remove unnecessary armpmu-\u003estop\n\nAs armpmu_disable will call armpmu-\u003estop when the last event has been\nremoved, this is pointless and simply adds to the noise when debugging.\nAdditionally, due to this call occurring in a preemptible context, this\nis problematic for per-cpu locking of PMU registers (where we will\nattempt to access per-cpu spinlock for use with raw_spin_lock_irqsave).\n\nThis patch removes the call to armpmu-\u003estop.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nReviewed-by: Jamie Iles \u003cjamie@jamieiles.com\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\n" }, { "commit": "92f701e1f429e007f9619469d548022061c41ecc", "tree": "ce70ecb1b103c52f7ddee02a935f940a59c7d76e", "parents": [ "a9356a04fab912289b886824cb4b1d461987a910" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Wed May 04 09:23:51 2011 +0100" }, "committer": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Wed Aug 31 10:50:05 2011 +0100" }, "message": "ARM: perf: indirect access to cpu_hw_events\n\nCurrently, cpu_hw_events is a global per-CPU variable. To enable\nsupport for multiple PMUs, there needs to be a mapping from an instance\nof arm_pmu to its cpu_hw_events. Additionally, as system PMUs are not\nCPU-affine, they should not have this stored per-CPU.\n\nThis patch moves access to the hardware events data behind an accessor\nfunction (arm_pmu::get_hw_events). This allows each instance to have\nits own hardware event data, which can be stored per-CPU or globally as\nrequired.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nReviewed-by: Jamie Iles \u003cjamie@jamieiles.com\u003e\nReviewed-by: Ashwin Chaugule \u003cashwinc@codeaurora.org\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\n" }, { "commit": "a9356a04fab912289b886824cb4b1d461987a910", "tree": "786f8b29224b3039a856fd87765f3f116d84e500", "parents": [ "03b7898d300de62078cc130fbc83b84b1d1e0f8d" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Wed May 04 09:23:15 2011 +0100" }, "committer": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Wed Aug 31 10:50:04 2011 +0100" }, "message": "ARM: perf: move platform device to struct arm_pmu\n\nCurrently the ARM perf code supports having a single struct\nplatform_device to supply IRQ numbers, limiting it to supporting a\nsingle PMU.\n\nThis patch makes a platform_device instance variable on struct arm_pmu.\nThis should allow for multiple PMUs to be supported in future.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nReviewed-by: Jamie Iles \u003cjamie@jamieiles.com\u003e\nReviewed-by: Ashwin Chaugule \u003cashwinc@codeaurora.org\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\n" }, { "commit": "03b7898d300de62078cc130fbc83b84b1d1e0f8d", "tree": "d0956ed5223569c138f1222d3b8897282c1536c7", "parents": [ "c47f8684baefa2bf52c4320f894e73db08dc8a0a" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Wed Apr 27 11:20:11 2011 +0100" }, "committer": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Wed Aug 31 10:50:03 2011 +0100" }, "message": "ARM: perf: move active_events into struct arm_pmu\n\nThis patch moves the active_events counter into struct arm_pmu, in\npreparation for supporting multiple PMUs. This also moves\npmu_reserve_mutex, as it is used to guard accesses to active_events.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nReviewed-by: Jamie Iles \u003cjamie@jamieiles.com\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\n" }, { "commit": "c47f8684baefa2bf52c4320f894e73db08dc8a0a", "tree": "685df6d09e03620e12d50c31cbf20e69b9e6ee32", "parents": [ "7b9f72c62ed047a200b1ef8c70bee0b58e880af8" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue Jul 19 09:37:10 2011 +0100" }, "committer": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Wed Aug 31 10:50:02 2011 +0100" }, "message": "ARM: perf: remove active_mask\n\nCurrently, pmu_hw_events::active_mask is used to keep track of which\nevents are active in hardware. As we can stop counters and their\ninterrupts, this is unnecessary.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nReviewed-by: Jamie Iles \u003cjamie@jamieiles.com\u003e\nReviewed-by: Ashwin Chaugule \u003cashwinc@codeaurora.org\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\n" }, { "commit": "7b9f72c62ed047a200b1ef8c70bee0b58e880af8", "tree": "1858fa358eaf3a40d892ff86705b724f1be8c3c7", "parents": [ "48957155f8791964d8567479e6986f88343aba38" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Wed Apr 27 16:22:21 2011 +0100" }, "committer": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Wed Aug 31 10:50:01 2011 +0100" }, "message": "ARM: perf: clean up event group validation\n\nCurrently, event group validation compares each event\u0027s \u0027pmu\u0027 pointer\nagainst the static \u0027pmu\u0027 pointer. This limits the code to supporting\nonly 1 PMU.\n\nThis patch changes the behaviour to consider an event\u0027s group leader\u0027s\n\u0027pmu\u0027 pointer as canonical for validation. This should ease later\ngeneralisation of the code to support multiple PMUs at once.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nReviewed-by: Jamie Iles \u003cjamie@jamieiles.com\u003e\nReviewed-by: Ashwin Chaugule \u003cashwinc@codeaurora.org\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\n" }, { "commit": "48957155f8791964d8567479e6986f88343aba38", "tree": "676a538a8d99cd2864525a4b62789ef203e6075c", "parents": [ "5f12a761937373d2f9b557d7519e6f1cf738b8f0" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Wed Apr 27 10:31:51 2011 +0100" }, "committer": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Wed Aug 31 10:50:00 2011 +0100" }, "message": "ARM: perf: only register a CPU PMU when present\n\nCurrently, an \"empty\" struct pmu is registered as the CPU PMU,\nregardless of whether there is a physical PMU. This burdens the\naccessor functions with checks to see whether a PMU is actually\npresent.\n\nThis patch changes initialisation to register a PMU only if there is a\nsupported PMU present, and removes the checks that this change makes\nredundant.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nReviewed-by: Jamie Iles \u003cjamie@jamieiles.com\u003e\nReviewed-by: Ashwin Chaugule \u003cashwinc@codeaurora.org\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\n" }, { "commit": "d12443363e590461655d4e9ccc31e40ad9078283", "tree": "b285b8aa719d4e1c094d38a5fb7253a51bea7af1", "parents": [ "0d352e3d006c9589f22580212c3822cf62b6d775" ], "author": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Thu Aug 04 14:46:23 2011 +0100" }, "committer": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Wed Aug 31 10:42:48 2011 +0100" }, "message": "ARM: hw_breakpoint: reduce the number of WARN_ONCE invocations\n\nThe ARM hw_breakpoint backend is currently a bit too noisy when things\nstart to go awry.\n\nThis patch removes a couple of over-zealous WARN_ONCE invocations and\nreplaces then with pr_warnings instead.\n\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\n" }, { "commit": "0d352e3d006c9589f22580212c3822cf62b6d775", "tree": "3bfaf9313cab84333380789471b7a9329f3f60fd", "parents": [ "6f26aa05c9edffff6a4c2cd71774bc659a5cceec" ], "author": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Mon Aug 08 14:26:53 2011 +0100" }, "committer": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Wed Aug 31 10:42:48 2011 +0100" }, "message": "ARM: hw_breakpoint: trap undef instruction exceptions in reset_ctrl_regs\n\nThe ARM debug registers can only be accessed if the DBGSWENABLE signal\nto the core is driven HIGH by the DAP. The architecture does not provide\na way to detect the value of this signal, so the best we can do is\nregister an undef_hook to trap debug register co-processor accesses and\nthen fail if the trap is taken.\n\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\n" }, { "commit": "6f26aa05c9edffff6a4c2cd71774bc659a5cceec", "tree": "a2db63a03389e2153004347ddd93805486d1076b", "parents": [ "c512de955f0982aafa49d3f00d5643052a6790e5" ], "author": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Tue Aug 02 16:16:57 2011 +0100" }, "committer": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Wed Aug 31 10:42:48 2011 +0100" }, "message": "ARM: hw_breakpoint: add support for multiple watchpoints\n\nARM debug architecture 7.1 mandates that the DFAR is updated on a\nwatchpoint debug exception to contain the faulting virtual address\nof the memory access. This allows us to determine which watchpoints\nhave fired and therefore report useful information to userspace.\n\nThis patch adds support for using the DFAR in the watchpoint handler,\nwhich allows us to support multiple watchpoints on CPUs implementing\nthe new debug architecture.\n\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\n" }, { "commit": "c512de955f0982aafa49d3f00d5643052a6790e5", "tree": "5bf3d463211f174ccf724e82be07cdf800b3168d", "parents": [ "b5d5b8f98641edac6641af9e19e933083ade603b" ], "author": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Tue Aug 02 13:01:17 2011 +0100" }, "committer": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Wed Aug 31 10:42:48 2011 +0100" }, "message": "ARM: hw_breakpoint: reserve one breakpoint for watchpoint stepping\n\nThe current hw_breakpoint code on ARM reserves 1 breakpoint for each\nwatchpoint that is available. Since debug architectures prior to 7.1\nare restricted to 1 watchpoint anyway, only one breakpoint was ever\nreserved.\n\nThis patch changes the reservation strategy so that a single breakpoint\nis reserved, regardless of the number of watchpoints. This is in\npreparation for multiple-watchpoint support on debug architectures\nfrom 7.1 onwards.\n\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\n" }, { "commit": "b5d5b8f98641edac6641af9e19e933083ade603b", "tree": "e68c07f25ddd2e90160abb2d8696eac046cc2e93", "parents": [ "90e93648c41bd29a72f6ec55ce27a23c209eab8c" ], "author": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Fri Jul 22 18:27:37 2011 +0100" }, "committer": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Wed Aug 31 10:42:47 2011 +0100" }, "message": "ARM: hw_breakpoint: add initial Cortex-A15 (debug v7.1) support\n\nThis patch adds initial support for Cortex-A15 (debug architecture v7.1)\nto the hw_breakpoint ARM backend.\n\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\n" }, { "commit": "a505addc366525cd8d9358298be0dc8655be5953", "tree": "3a2fcfc4ed7659bed5743558ec2fcd937dfa889c", "parents": [ "05d22fde3c0b86c8395d8f12ac01fbbc524d73ca" ], "author": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Tue Jul 19 13:53:36 2011 +0100" }, "committer": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Wed Aug 31 10:18:01 2011 +0100" }, "message": "ARM: perf: add mode exclusion for Cortex-A15 PMU\n\nThe Cortex-A15 PMU implements the PMUv2 specification and therefore\nhas support for some mode exclusion.\n\nThis patch adds support for excluding user, kernel and hypervisor counts\nfrom a given event.\n\nAcked-by: Jamie Iles \u003cjamie@jamieiles.com\u003e\nReviewed-by: Jean Pihet \u003cj-pihet@ti.com\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\n" }, { "commit": "05d22fde3c0b86c8395d8f12ac01fbbc524d73ca", "tree": "e0ea6c8b2a90a8dc02c7bcea9288b9176b3f7b69", "parents": [ "ecf5a893211c26e02b9d4cfd6ba2183473ac0203" ], "author": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Tue Jul 19 11:57:30 2011 +0100" }, "committer": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Wed Aug 31 10:18:01 2011 +0100" }, "message": "ARM: perf: allow armpmu to implement mode exclusion\n\nModern PMUs allow for mode exclusion, so we no longer wish to return\n-EPERM if it is requested.\n\nThis patch provides a hook in the armpmu structure for implementing\nmode exclusion. The hw_perf_event initialisation is slightly delayed so\nthat the backend code can update the structure if required.\n\nAcked-by: Jamie Iles \u003cjamie@jamieiles.com\u003e\nReviewed-by: Jean Pihet \u003cj-pihet@ti.com\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\n" }, { "commit": "ecf5a893211c26e02b9d4cfd6ba2183473ac0203", "tree": "accf48ac99027c2b3fcc81217569abae827ad80d", "parents": [ "d2b41f7456223ba6abd3b38d7b54be97914f3aa5" ], "author": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Tue Jul 19 22:43:28 2011 +0100" }, "committer": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Wed Aug 31 10:18:01 2011 +0100" }, "message": "ARM: perf: index PMU registers from zero\n\nARM PMU code used to use 1-based indices for PMU registers. This caused\nseveral data structures (pmu_hw_events::{active_events, used_mask, events})\nto have an unused element at index zero. ARMPMU_MAX_HWEVENTS still takes\nthis indexing into account, and currently equates to 33.\n\nThis patch updates the core ARM perf code to use the 0th index again.\n\nAcked-by: Jamie Iles \u003cjamie@jamieiles.com\u003e\nReviewed-by: Jean Pihet \u003cj-pihet@ti.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\n" }, { "commit": "d2b41f7456223ba6abd3b38d7b54be97914f3aa5", "tree": "08ffd6f54daa58de58ae3ae7f5017f26bed6f9aa", "parents": [ "c691bb6249b25104fcb6dad31bd772c139ce4a50" ], "author": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Tue Jul 19 22:41:36 2011 +0100" }, "committer": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Wed Aug 31 10:18:00 2011 +0100" }, "message": "ARM: perf: index Xscale and ARMv6 event counters starting from zero\n\nNow that the ARMv7 PMU backend indexes event counters from zero, follow\nsuit and do the same for ARMv6 and Xscale.\n\nAcked-by: Jamie Iles \u003cjamie@jamieiles.com\u003e\nReviewed-by: Jean Pihet \u003cj-pihet@ti.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\n" }, { "commit": "c691bb6249b25104fcb6dad31bd772c139ce4a50", "tree": "0bcff4d0b191d91ab6738aa3a3120a3cc5425b17", "parents": [ "25e29c7c0f4fcbe911b77a69f015bd6424cedcd0" ], "author": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Tue Jul 19 22:25:55 2011 +0100" }, "committer": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Wed Aug 31 10:18:00 2011 +0100" }, "message": "ARM: perf: index ARMv7 event counters starting from zero\n\nThe current ARMv7 PMU backend indexes event counters from two, with\nindex zero being reserved and index one being used to represent the\ncycle counter.\n\nThis patch tidies up the code by indexing from one instead (with zero\nfor the cycle counter). This allows us to remove many of the accessor\nmacros along with the counter enumeration and makes the code much more\nreadable.\n\nAcked-by: Jamie Iles \u003cjamie@jamieiles.com\u003e\nReviewed-by: Jean Pihet \u003cj-pihet@ti.com\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\n" }, { "commit": "25e29c7c0f4fcbe911b77a69f015bd6424cedcd0", "tree": "5055018f21809859c9f008ac586507e83fdb34bb", "parents": [ "6330aae7dcd54df893813392e310141be7aa5323" ], "author": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Tue Jul 19 22:17:48 2011 +0100" }, "committer": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Wed Aug 31 10:18:00 2011 +0100" }, "message": "ARM: perf: use integers for ARMv7 event indices\n\nThis patch ensures that integers are used to represent event indices in\nthe ARMv7 PMU backend. This ensures consistency between functions and\nalso with the arm_pmu structure.\n\nAcked-by: Jamie Iles \u003cjamie@jamieiles.com\u003e\nReviewed-by: Jean Pihet \u003cj-pihet@ti.com\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\n" }, { "commit": "6330aae7dcd54df893813392e310141be7aa5323", "tree": "f37299feade875390787fa594097ad85f04f47fa", "parents": [ "0b390e2126e03b6ec41f96fb0550b1526d00e203" ], "author": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Tue Jul 19 14:55:57 2011 +0100" }, "committer": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Wed Aug 31 10:18:00 2011 +0100" }, "message": "ARM: perf: use u32 instead of unsigned long for PMNC register\n\nThe ARMv7 perf backend mixes up u32 and unsigned long, which is rather\nugly.\n\nThis patch makes the ARMv7 PMU code consistently use the u32 type\ninstead.\n\nAcked-by: Jamie Iles \u003cjamie@jamieiles.com\u003e\nReviewed-by: Jean Pihet \u003cj-pihet@ti.com\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\n" }, { "commit": "0b390e2126e03b6ec41f96fb0550b1526d00e203", "tree": "36520568e01918ab82900631c75960016ffe464c", "parents": [ "b0e89590f4f27ea5ff30bdedb9a58ea904a6b353" ], "author": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Wed Jul 27 15:18:59 2011 +0100" }, "committer": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Wed Aug 31 10:17:59 2011 +0100" }, "message": "ARM: perf: use cpumask_t to record active IRQs\n\nCommit 5dfc54e0 (\"ARM: GIC: avoid routing interrupts to offline CPUs\")\nprevents the GIC from setting the affinity of an IRQ to a CPU with\nid \u003e\u003d nr_cpu_ids. This was previously abused by perf on some platforms\nwhere more IRQs were registered than possible CPUs.\n\nThis patch fixes the problem by using a cpumask_t to keep track of the\nactive (requested) interrupts in perf. The same effect could be achieved\nby limiting the number of IRQs to the number of CPUs, but using a mask\ninstead will be useful for adding extended CPU hotplug support in the\nfuture.\n\nAcked-by: Jamie Iles \u003cjamie@jamieiles.com\u003e\nReviewed-by: Jean Pihet \u003cj-pihet@ti.com\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\n" }, { "commit": "b0e89590f4f27ea5ff30bdedb9a58ea904a6b353", "tree": "8d81a0d268dd6780e4c5a7cfa4b9c49708afebc7", "parents": [ "a6c93afed38c242ccf4ec5bcb5ff26ff2521cf36" ], "author": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Tue Jul 26 22:10:28 2011 +0100" }, "committer": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Wed Aug 31 10:17:59 2011 +0100" }, "message": "ARM: PMU: move CPU PMU platform device handling and init into perf\n\nOnce upon a time, OProfile and Perf fought hard over who could play with\nthe PMU. To stop all hell from breaking loose, pmu.c offered an internal\nreserve/release API and took care of parsing PMU platform data passed in\nfrom board support code.\n\nNow that Perf has ingested OProfile, let\u0027s move the platform device\nhandling into the Perf driver and out of the PMU locking code.\nUnfortunately, the lock has to remain to prevent Perf being bitten by\nout-of-tree modules such as LTTng, which still claim a right to the PMU\nwhen Perf isn\u0027t looking.\n\nAcked-by: Jamie Iles \u003cjamie@jamieiles.com\u003e\nReviewed-by: Jean Pihet \u003cj-pihet@ti.com\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\n" }, { "commit": "a6c93afed38c242ccf4ec5bcb5ff26ff2521cf36", "tree": "e99c2b3f3d03df77d497907afff9b7310b772fd1", "parents": [ "90e93648c41bd29a72f6ec55ce27a23c209eab8c" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Fri Apr 15 11:14:38 2011 +0100" }, "committer": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Wed Aug 31 10:16:58 2011 +0100" }, "message": "ARM: perf: de-const struct arm_pmu\n\nThis patch removes const qualifiers from instances of struct arm_pmu,\nand functions initialising them, in preparation for generalising\narm_pmu usage to system (AKA uncore) PMUs.\n\nThis will allow for dynamically modifiable structures (locks,\nstruct pmu) to be added as members of struct arm_pmu.\n\nAcked-by: Jamie Iles \u003cjamie@jamieiles.com\u003e\nReviewed-by: Jean Pihet \u003cj-pihet@ti.com\u003e\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\n" }, { "commit": "90e93648c41bd29a72f6ec55ce27a23c209eab8c", "tree": "705afc522c361f681567187018d80cf028fcb334", "parents": [ "3ae627b5a6c8f6bf992eee6a3399a1854641a476", "25904157168ddc8841748a729914f00e53d7e049" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Aug 29 16:34:07 2011 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Aug 29 16:34:07 2011 -0700" }, "message": "Merge branch \u0027fixes\u0027 of master.kernel.org:/home/rmk/linux-2.6-arm\n\n* \u0027fixes\u0027 of master.kernel.org:/home/rmk/linux-2.6-arm:\n ARM: pm: avoid writing the auxillary control register for ARMv7\n ARM: pm: some ARMv7 requires a dsb in resume to ensure correctness\n ARM: pm: arm920/926: fix number of registers saved\n ARM: pm: CPU specific code should not overwrite r1 (v:p offset)\n ARM: 7066/1: proc-v7: disable SCTLR.TE when disabling MMU\n ARM: 7065/1: kexec: ensure new kernel is entered in ARM state\n ARM: 7003/1: vexpress: Add clock definition for the SP805.\n ARM: 7051/1: cpuimx* boards: fix mach-types errors\n ARM: 7019/1: Footbridge: select CLKEVT_I8253 for ARCH_NETWINDER\n ARM: 7015/1: ARM errata: Possible cache data corruption with hit-under-miss enabled\n ARM: 7014/1: cache-l2x0: Fix L2 Cache size calculation.\n ARM: 6967/1: ep93xx: ts72xx: fix board model detection\n ARM: 6965/1: ep93xx: add model detection for ts-7300 and ts-7400 boards\n ARM: cache: detect VIPT aliasing I-cache on ARMv6\n ARM: twd: register clockevents device before enabling PPI\n ARM: realview: ensure visibility of writes during reset\n ARM: perf: make name of arm_pmu_type consistent\n ARM: perf: fix prototype of release_pmu\n ARM: fix perf build with uclibc toolchains\n" }, { "commit": "96f90c791512bf8ceb50572a0e65d4cabb665c60", "tree": "33ed5d6e4ce2ef005a43b0a5e2b9a70e3866d7f4", "parents": [ "ad30a2bbdc20cf0111156e2aa6d2cc3e3c0d1893", "daece59689e76ed55d8863cae04993679a8e844e" ], "author": { "name": "Nicolas Pitre", "email": "nicolas.pitre@linaro.org", "time": "Mon Aug 29 15:29:00 2011 -0400" }, "committer": { "name": "Nicolas Pitre", "email": "nico@fluxnic.net", "time": "Mon Aug 29 15:29:00 2011 -0400" }, "message": "Merge the enabling by default of ARM_PATCH_PHYS_VIRT\n\nConflicts:\n\tarch/arm/mach-msm/board-msm7x30.c\n" }, { "commit": "552e0c8da8ff7099e6fe060cd7ec36ae11f5465b", "tree": "9cec5232f51a023374a3ee66520ea7da056d9f32", "parents": [ "0ebb962e00a52b644433065d224ed89f72a84756" ], "author": { "name": "Will Deacon", "email": "will.deacon@arm.com", "time": "Fri Aug 26 16:32:57 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Aug 28 10:39:41 2011 +0100" }, "message": "ARM: 7065/1: kexec: ensure new kernel is entered in ARM state\n\nCommit 540b5738 (\"ARM: 6999/1: head, zImage: Always Enter the kernel in\nARM state\") mandates that the kernel should be entered in ARM state.\n\nIf a Thumb-2 kernel kexecs a new kernel image, we need to ensure that\nwe change state when branching to the new code. This patch replaces a\nmov pc, lr with a bx lr on Thumb-2 kernels so that we transition to ARM\nstate if need be.\n\nReviewed-by: Dave Martin \u003cdave.martin@linaro.org\u003e\nSigned-off-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "f5b940997397229975ea073679b03967932a541b", "tree": "a477f440175d67b67928d6d11c845fe98f09eb72", "parents": [ "b727d20269e8ef1de002bfea8099f5e9db9e9f23" ], "author": { "name": "NeilBrown", "email": "neilb@suse.de", "time": "Fri Aug 26 18:03:11 2011 -0400" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Aug 26 15:09:58 2011 -0700" }, "message": "All Arch: remove linkage for sys_nfsservctl system call\n\nThe nfsservctl system call is now gone, so we should remove all\nlinkage for it.\n\nSigned-off-by: NeilBrown \u003cneilb@suse.de\u003e\nSigned-off-by: J. Bruce Fields \u003cbfields@redhat.com\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "e73fc88e19d74fd4dd664cff45b88caab8cde45c", "tree": "2f018afe68b417d43c9f6defc946f94915a4d6a0", "parents": [ "01f461a3a4321a9f98b6b508f32d2396c5704b7c" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Tue Aug 23 14:07:23 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Aug 23 15:30:33 2011 +0100" }, "message": "ARM: 7059/1: LPAE: Use PMD_(SHIFT|SIZE|MASK) instead of PGDIR_*\n\nPGDIR_SHIFT and PMD_SHIFT for the classic 2-level page table format have\nthe same value (21). This patch converts the PGDIR_* uses in the kernel\nto the PMD_* equivalent so that LPAE builds can reuse the same code.\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "af6871683e25100813d35b3d802f1ed7b90b9f3a", "tree": "9774f14b5f6e178d924344de2c42320431243e88", "parents": [ "0cc9311fad9eab567cea0b94e37ef73aef7a8cee" ], "author": { "name": "Nicolas Pitre", "email": "nicolas.pitre@linaro.org", "time": "Tue Jul 05 22:38:19 2011 -0400" }, "committer": { "name": "Nicolas Pitre", "email": "nico@fluxnic.net", "time": "Sun Aug 21 17:15:24 2011 -0400" }, "message": "ARM: remove boot_params from struct machine_desc\n\nNow that there is no more users, we can remove it from the kernel.\n\nSigned-off-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n" }, { "commit": "2bb9839e312ed55a6d5824ffa6077ce3d7d63b1e", "tree": "c71d4cc38c828784a96d5cbbc6bfb53ef336a911", "parents": [ "93ee7a9340d64f20295aacc3fb6a22b759323280" ], "author": { "name": "Nicolas Pitre", "email": "nicolas.pitre@linaro.org", "time": "Tue Jul 05 22:38:10 2011 -0400" }, "committer": { "name": "Nicolas Pitre", "email": "nico@fluxnic.net", "time": "Sun Aug 21 17:09:13 2011 -0400" }, "message": "ARM: introduce atag_offset to replace boot_params\n\nThe boot_params member of the mdesc structure is used to provide a\ndefault physical address for the ATAG list. Since this value is fixed\nat compile time and sometimes based on constants such as ARCH_PHYS_OFFSET,\nit gets in the way of runtime PHYS_OFFSET and CONFIG_ARM_PATCH_PHYS_VIRT\nusage.\n\nLet\u0027s introduce atag_offset which should contains only the relative\noffset from PHYS_OFFSET instead of an absolute value, in preparation\nto move all instance of boot_params over to it.\n\nSigned-off-by: Nicolas Pitre \u003cnicolas.pitre@linaro.org\u003e\nTested-by: H Hartley Sweeten \u003chsweeten@visionengravers.com\u003e\nTested-by: Petr Štetiar \u003cynezz@true.cz\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n" }, { "commit": "5e4cdb83edd69d24b744cd88a9537680e905a518", "tree": "51d4b1998608d4caeb56ee64d428e56e37fc35e5", "parents": [ "06cf0b5468f204754f32e571f8415b20cedbe5f0" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Jul 07 11:40:52 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Aug 17 08:44:16 2011 +0100" }, "message": "ARM: io: RiscPC: make EASI_BASE a void iomem pointer\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "06cf0b5468f204754f32e571f8415b20cedbe5f0", "tree": "b876f9bcdada5de5ab7a5aa958fd8308d8a6f881", "parents": [ "1ace756628443ac41e8b6b409277fc4ee847472e" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Jul 07 11:07:36 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Aug 17 08:44:16 2011 +0100" }, "message": "ARM: io: ecard: remove ioaddr() from ecard.c\n\nRemove ioaddr() usage from ecard.c, updating (and renaming) the\nconstants in RiscPC\u0027s hardware.h to contain the proper translation.\nAs this gets rid of the last ioaddr() usage, kill that too.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "1ace756628443ac41e8b6b409277fc4ee847472e", "tree": "9e7e9f9064cfcdf617e81de7c7afa76989c021f1", "parents": [ "d0a84e72eb755f58ba350d9988bfbdffd6f5a22c" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Jul 07 10:56:41 2011 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Aug 17 08:44:16 2011 +0100" }, "message": "ARM: io: ecard: move ioaddr() inside __ecard_address\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" } ], "next": "daece59689e76ed55d8863cae04993679a8e844e" }