)]}' { "log": [ { "commit": "1c8d7b0a562da06d3ebe83f01b1ed553205d1ae4", "tree": "79c84432f5aed5a08b3bef262a10d933daae6a9b", "parents": [ "f2440d9acbe866b917b16cc0f927366341ce9215" ], "author": { "name": "Matthew Wilcox", "email": "willy@linux.intel.com", "time": "Tue Mar 17 08:54:10 2009 -0400" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 10:48:14 2009 -0700" }, "message": "PCI MSI: Add support for multiple MSI\n\nAdd the new API pci_enable_msi_block() to allow drivers to\nrequest multiple MSI and reimplement pci_enable_msi in terms of\npci_enable_msi_block. Ensure that the architecture back ends don\u0027t\nhave to know about multiple MSI.\n\nSigned-off-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f2440d9acbe866b917b16cc0f927366341ce9215", "tree": "ed868ca5b61fcadaf782f85c9a900b06e77fc3ce", "parents": [ "264d9caaa1c574c0274b019a810abfe957391005" ], "author": { "name": "Matthew Wilcox", "email": "willy@linux.intel.com", "time": "Tue Mar 17 08:54:09 2009 -0400" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 10:48:13 2009 -0700" }, "message": "PCI MSI: Refactor interrupt masking code\n\nSince most of the callers already know whether they have an MSI or\nan MSI-X capability, split msi_set_mask_bits() into msi_mask_irq()\nand msix_mask_irq(). The only callers which don\u0027t (mask_msi_irq()\nand unmask_msi_irq()) can share code in msi_set_mask_bit(). This then\nbecomes the only caller of msix_flush_writes(), so we can inline it.\nThe flushing read can be to any address that belongs to the device,\nso we can eliminate the calculation too.\n\nWe can also get rid of maskbits_mask from struct msi_desc and simply\nrecalculate it on the rare occasion that we need it. The single-bit\n\u0027masked\u0027 element is replaced by a copy of the 32-bit \u0027masked\u0027 register,\nso this patch does not affect the size of msi_desc.\n\nSigned-off-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "264d9caaa1c574c0274b019a810abfe957391005", "tree": "06ac3d9df11a0e64e2f8571145e8865424fb7dc6", "parents": [ "379f5327a86f7822a51ec7d088a085167724df75" ], "author": { "name": "Matthew Wilcox", "email": "willy@linux.intel.com", "time": "Tue Mar 17 08:54:08 2009 -0400" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 10:48:13 2009 -0700" }, "message": "PCI MSI: Use mask_pos instead of mask_base when appropriate\n\nMSI interrupts have a mask_pos where MSI-X have a mask_base. Use a\ntransparent union to get rid of some ugly casts.\n\nSigned-off-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "24d27553390c69d11cdbd930d635193956fc295f", "tree": "1ed673378c02eba46e6f427e1ab2ca06558f9045", "parents": [ "c41ade2ee1dc146d2de2ee470a87cd6b878a08f4" ], "author": { "name": "Matthew Wilcox", "email": "willy@linux.intel.com", "time": "Tue Mar 17 08:54:06 2009 -0400" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 10:48:12 2009 -0700" }, "message": "PCI MSI: Replace \u0027type\u0027 with \u0027is_msix\u0027\n\nBy changing from a 5-bit field to a 1-bit field, we free up some bits\nthat can be used by a later patch. Also rearrange the fields for better\npacking on 64-bit platforms (reducing the size of msi_desc from 72 bytes\nto 64 bytes).\n\nSigned-off-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "3145e941fcfe2548fa2270afb1a05bab3a6bc418", "tree": "5bd08b9de84d1be58be040058ac77a4dd8c8d7b2", "parents": [ "be5d5350a937cd8513b258739f1099420129e96f" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Fri Dec 05 18:58:34 2008 -0800" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Mon Dec 08 14:31:59 2008 +0100" }, "message": "x86, MSI: pass irq_cfg and irq_desc\n\nImpact: simplify code\n\nPass irq_desc and cfg around, instead of raw IRQ numbers - this way\nwe dont have to look it up again and again.\n\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "8e149e09f91098fd72bf9ac5b4a77a693abf721e", "tree": "e0aae800a75a478820494ddce42291f896014012", "parents": [ "2768f92c06a59c3ebf17a6b86002c3f33ab61a28" ], "author": { "name": "Yinghai Lu", "email": "yhlu.kernel.send@gmail.com", "time": "Wed Apr 23 14:56:30 2008 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@hobbes.lan", "time": "Tue Apr 29 09:11:12 2008 -0700" }, "message": "pci/irq: restore mask_bits in msi shutdown -v3\n\n[PATCH 1/2] pci/irq: restore mask_bits in msi shutdown -v3\n\nYinghai found that kexec\u0027ing a RHEL 5.1 kernel with 2.6.25-rc3+ kernels\nprevents his NIC from working. He bisected to\n\n| commit 89d694b9dbe769ca1004e01db0ca43964806a611\n| Author: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n| Date: Mon Feb 18 18:25:17 2008 +0100\n|\n| genirq: do not leave interupts enabled on free_irq\n|\n| The default_disable() function was changed in commit:\n|\n| 76d2160147f43f982dfe881404cfde9fd0a9da21\n| genirq: do not mask interrupts by default\n|\n\nFor MSI, default_shutdown will call mask_bit for msi device. All mask bits\nwill left disabled after free_irq. Then in the kexec case, the next kernel\ncan only use msi_enable bit, so all device\u0027s MSI can not be used.\n\nSo lets to restore the mask bit to its pci reset defined value (enabled) when\nwe disable the kernels use of msi to be a little friendlier to kexec\u0027d kernels.\n\nExtend msi_set_mask_bit to msi_set_mask_bits to take mask, so we can fully\nrestore that to 0x00 instead of 0xfe.\n\nSigned-off-by: Yinghai Lu \u003cyhlu.kernel@gmail.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@hobbes.lan\u003e\n" }, { "commit": "032de8e2fe3c0eec5fb0ffe4d38aa602dad397dc", "tree": "b9ad28ab3642c2dfba8e059fc72bd8e86c667449", "parents": [ "9c8313343c83c0ca731ceb8d2a4ab1e022ed9c94" ], "author": { "name": "Michael Ellerman", "email": "michael@ellerman.id.au", "time": "Wed Apr 18 19:39:22 2007 +1000" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Wed May 02 19:02:38 2007 -0700" }, "message": "MSI: Give archs the option to free all MSI/Xs at once.\n\nThis patch introduces an optional function, arch_teardown_msi_irqs(),\nwhich gives an arch the opportunity to do per-device teardown for\nMSI/X. If that\u0027s not required, the default version simply calls\narch_teardown_msi_irq() for each msi irq required.\n\narch_teardown_msi_irqs() is simply passed a pdev, attached to the pdev\nis a list of msi_descs, it is up to the arch to free the irq associated\nwith each of these as appropriate.\n\nFor archs that _don\u0027t_ implement arch_teardown_msi_irqs(), all msi_descs\nwith irq \u003d\u003d 0 are considered unallocated, and the arch teardown routine\nis not called on them.\n\nSigned-off-by: Michael Ellerman \u003cmichael@ellerman.id.au\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n" }, { "commit": "9c8313343c83c0ca731ceb8d2a4ab1e022ed9c94", "tree": "1e37ef3ebcdcb344adb74c1667ad04cf87010f5e", "parents": [ "7fe3730de729b758e9f69b862b9255d998671b5f" ], "author": { "name": "Michael Ellerman", "email": "michael@ellerman.id.au", "time": "Wed Apr 18 19:39:21 2007 +1000" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Wed May 02 19:02:38 2007 -0700" }, "message": "MSI: Give archs the option to allocate all MSI/Xs at once.\n\nThis patch introduces an optional function, arch_setup_msi_irqs(),\n(note the plural) which gives an arch the opportunity to do per-device\nsetup for MSI/X and then allocate all the requested MSI/Xs at once.\n\nIf that\u0027s not required by the arch, the default version simply calls\narch_setup_msi_irq() for each MSI irq required.\n\narch_setup_msi_irqs() is passed a pdev, attached to the pdev is a list\nof msi_descs with irq \u003d\u003d 0, it is up to the arch to connect these up to\nan irq (via set_irq_msi()) or return an error. For convenience the number\nof vectors and the type are passed also.\n\nAll msi_descs with irq !\u003d 0 are considered allocated, and the arch\nteardown routine will be called on them when necessary.\n\nThe existing semantics of pci_enable_msix() are that if the requested\nnumber of irqs can not be allocated, the maximum number that _could_ be\nallocated is returned. To support that, we define that in case of an\nerror from arch_setup_msi_irqs(), the number of msi_descs with irq !\u003d 0\nare considered allocated, and are counted toward the \"max that could be\nallocated\".\n\n\nSigned-off-by: Michael Ellerman \u003cmichael@ellerman.id.au\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n" }, { "commit": "4aa9bc955d61fdf03b5f9cee67db188fe1ffa8b7", "tree": "bd0604f5d7308d63cafbb1e3134580e284d86a50", "parents": [ "bab41e9be75121c473b00df2ffa33af3c44066a7" ], "author": { "name": "Michael Ellerman", "email": "michael@ellerman.id.au", "time": "Thu Apr 05 17:19:10 2007 +1000" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Wed May 02 19:02:37 2007 -0700" }, "message": "MSI: Use a list instead of the custom link structure\n\nThe msi descriptors are linked together with what looks a lot like\na linked list, but isn\u0027t a struct list_head list. Make it one.\n\nThe only complication is that previously we walked a list of irqs, and\ngot the descriptor for each with get_irq_msi(). Now we have a list of\ndescriptors and need to get the irq out of it, so it needs to be in the\nactual struct msi_desc. We use 0 to indicate no irq is setup.\n\nSigned-off-by: Michael Ellerman \u003cmichael@ellerman.id.au\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n" }, { "commit": "c9953a73e92df11edd812d863ff741877ea9e58c", "tree": "27262efa28f6c05e26bfd87ef03af4a81fda3d22", "parents": [ "17bbc12acdb23ffb9613e12ca974fafd31bfcb56" ], "author": { "name": "Michael Ellerman", "email": "michael@ellerman.id.au", "time": "Thu Apr 05 17:19:08 2007 +1000" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Wed May 02 19:02:37 2007 -0700" }, "message": "MSI: Add an arch_msi_check_device()\n\nAdd an arch_check_device(), which gives archs a chance to check the input\nto pci_enable_msi/x. The arch might be interested in the value of nvec so\npass it in. Propagate the error value returned from the arch routine out\nto the caller.\n\nSigned-off-by: Michael Ellerman \u003cmichael@ellerman.id.au\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n" }, { "commit": "392ee1e6dd901db6c4504617476f6442ed91f72d", "tree": "591658a0197244782973674f240cf61895ef498e", "parents": [ "529284a0b649499351495949d05fa3359121cbae" ], "author": { "name": "Eric W. Biederman", "email": "ebiederm@xmission.com", "time": "Thu Mar 08 13:04:57 2007 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Mon Mar 12 16:31:50 2007 -0700" }, "message": "[PATCH] msi: Safer state caching.\n\nThere are two ways pci_save_state and pci_restore_state are used. As\nhelper functions during suspend/resume, and as helper functions around\na hardware reset event. When used as helper functions around a hardware\nreset event there is no reason to believe the calls will be paired, nor\nis there a good reason to believe that if we restore the msi state from\nbefore the reset that it will match the current msi state. Since arch\ncode may change the msi message without going through the driver, drivers\ncurrently do not have enough information to even know when to call\npci_save_state to ensure they will have msi state in sync with the other\nkernel irq reception data structures.\n\nIt turns out the solution is straight forward, cache the state in the\nexisting msi data structures (not the magic pci saved things) and\nhave the msi code update the cached state each time we write to the hardware.\nThis means we never need to read the hardware to figure out what the hardware\nstate should be.\n\nBy modifying the caching in this manner we get to remove our save_state\nroutines and only need to provide restore_state routines.\n\nThe only fields that were at all tricky to regenerate were the msi and msi-x\ncontrol registers and the way we regenerate them currently is a bit dependent\nupon assumptions on how we use the allow msi registers to be configured and used\nmaking the code a little bit brittle. If we ever change what cases we allow\nor how we configure the msi bits we can address the fragility then.\n\nSigned-off-by: Eric W. Biederman \u003cebiederm@xmission.com\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\nAcked-by: Auke Kok \u003cauke-jan.h.kok@intel.com\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "f7feaca77d6ad6bcfcc88ac54e3188970448d6fe", "tree": "3002076ed2b6ab497b3b90232ff11b08de2eca5d", "parents": [ "5b912c108c8b1fcecbfe13d6d9a183db97b682d3" ], "author": { "name": "Eric W. Biederman", "email": "ebiederm@xmission.com", "time": "Sun Jan 28 12:56:37 2007 -0700" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Wed Feb 07 15:50:08 2007 -0800" }, "message": "msi: Make MSI useable more architectures\n\nThe arch hooks arch_setup_msi_irq and arch_teardown_msi_irq are now\nresponsible for allocating and freeing the linux irq in addition to\nsetting up the the linux irq to work with the interrupt.\n\narch_setup_msi_irq now takes a pci_device and a msi_desc and returns\nan irq.\n\nWith this change in place this code should be useable by all platforms\nexcept those that won\u0027t let the OS touch the hardware like ppc RTAS.\n\nSigned-off-by: Eric W. Biederman \u003cebiederm@xmission.com\u003e\nAcked-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n" }, { "commit": "c54c18790700b8b2a503945d729aa425c25691fe", "tree": "90061bba5831aa5112afb08fc2fc89f32582078b", "parents": [ "8255cf35d503db7c1b26ae53b6b7f23ada82316f" ], "author": { "name": "Satoru Takeuchi", "email": "takeuchi_satoru@jp.fujitsu.com", "time": "Thu Jan 18 13:50:05 2007 +0900" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Wed Feb 07 15:50:06 2007 -0800" }, "message": "PCI: cleanup MSI code\n\nCleanup MSI code as follows:\n\n - fix some types\n - fix strange local variable definition\n - delete unnecessary blank line\n - add comment to #endif which is far from corresponding #ifdef\n\nSigned-off-by: Satoru Takeuchi \u003ctakeuchi_satoru@jp.fujitsu.com\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n" }, { "commit": "3b7d1921f4cdd6d6ddb7899ae7a8d413991c5cf4", "tree": "5f809e0c4310f60dfa6f65d54fbaf9f01e2ebff9", "parents": [ "277bc33bc2479707e88b0b2ae6fe56e8e4aabe81" ], "author": { "name": "Eric W. Biederman", "email": "ebiederm@xmission.com", "time": "Wed Oct 04 02:16:59 2006 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Wed Oct 04 07:55:29 2006 -0700" }, "message": "[PATCH] msi: refactor and move the msi irq_chip into the arch code\n\nIt turns out msi_ops was simply not enough to abstract the architecture\nspecific details of msi. So I have moved the resposibility of constructing\nthe struct irq_chip to the architectures, and have two architecture specific\nfunctions arch_setup_msi_irq, and arch_teardown_msi_irq.\n\nFor simple architectures those functions can do all of the work. For\narchitectures with platform dependencies they can call into the appropriate\nplatform code.\n\nWith this msi.c is finally free of assuming you have an apic, and this\nactually takes less code.\n\nThe helpers for the architecture specific code are declared in the linux/msi.h\nto keep them separate from the msi functions used by drivers in linux/pci.h\n\nSigned-off-by: Eric W. Biederman \u003cebiederm@xmission.com\u003e\nCc: Ingo Molnar \u003cmingo@elte.hu\u003e\nCc: Tony Luck \u003ctony.luck@intel.com\u003e\nCc: Andi Kleen \u003cak@suse.de\u003e\nCc: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: Greg KH \u003cgreg@kroah.com\u003e\nCc: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" } ] }