)]}' { "log": [ { "commit": "ebd8c56c5ae154e2c6cfb7453a76a4e7265b2377", "tree": "155df85100a1316ac103dcaed140d20ddc72c855", "parents": [ "101d5c18a928ef82b6c7bf99a9eaa536b5ccf593" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Fri Feb 17 08:38:06 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:13:24 2006 -0800" }, "message": "[SPARC64]: Fix uniprocessor IRQ targetting on SUN4V.\n\nWe need to use the real hardware processor ID when\ntargetting interrupts, not the \"define to 0\" thing\nthe uniprocessor build gives us.\n\nAlso, fill in the Node-ID and Agent-ID fields properly\non sun4u/Safari.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "72aff53f1fe74153eccef303ab2f79de888d248c", "tree": "a229645be99274d36bed04bed355d74ec3c0baa2", "parents": [ "19a0d585e80e84b54bb9bf120bf0c826045dd3dd" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Fri Feb 17 01:29:17 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:13:22 2006 -0800" }, "message": "[SPARC64]: Get SUN4V SMP working.\n\nThe sibling cpu bringup is extremely fragile. We can only\nperform the most basic calls until we take over the trap\ntable from the firmware/hypervisor on the new cpu.\n\nThis means no accesses to %g4, %g5, %g6 since those can\u0027t be\nTLB translated without our trap handlers.\n\nIn order to achieve this:\n\n1) Change sun4v_init_mondo_queues() so that it can operate in\n several modes.\n\n It can allocate the queues, or install them in the current\n processor, or both.\n\n The boot cpu does both in it\u0027s call early on.\n\n Later, the boot cpu allocates the sibling cpu queue, starts\n the sibling cpu, then the sibling cpu loads them in.\n\n2) init_cur_cpu_trap() is changed to take the current_thread_info()\n as an argument instead of reading %g6 directly on the current\n cpu.\n\n3) Create a trampoline stack for the sibling cpus. We do our basic\n kernel calls using this stack, which is locked into the kernel\n image, then go to our proper thread stack after taking over the\n trap table.\n\n4) While we are in this delicate startup state, we put 0xdeadbeef\n into %g4/%g5/%g6 in order to catch accidental accesses.\n\n5) On the final prom_set_trap_table*() call, we put \u0026init_thread_union\n into %g6. This is a hack to make prom_world(0) work. All that\n wants to do is restore the %asi register using\n get_thread_current_ds().\n\nLonger term we should just do the OBP calls to set the trap table by\nhand just like we do for everything else. This would avoid that silly\nprom_world(0) issue, then we can remove the init_thread_union hack.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "4ff7ac417d4b628c23df3ae8301d17e29e6e8f16", "tree": "8a0ad85722f0e927ac6c1388032481636424fb10", "parents": [ "22780e23c629303474797d17e7f09ad7721ef55b" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Feb 16 16:22:26 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:13:18 2006 -0800" }, "message": "[SPARC64]: Add GET_GL_GLOBAL() macro for SUN4V.\n\nSo we can read the %gl register for debugging.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "94f8762db9a80ed34252e9fe5fa38be87bb7826b", "tree": "22279c62d2d4d583c64f1d2c6122f4eb98b429a6", "parents": [ "bc45e32e0fbf661d0c5c5b9c981bc0fe5da4901f" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Feb 16 14:26:53 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:13:16 2006 -0800" }, "message": "[SPARC64]: Add sun4v_cpu_qconf() hypervisor call.\n\nCall it from register_one_mondo().\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "bc45e32e0fbf661d0c5c5b9c981bc0fe5da4901f", "tree": "cf4a313304153b39bd155c062b934d607500f2ae", "parents": [ "8e42550c683b2ad4869fc4fa438204841fd9b7cc" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sun Mar 05 16:46:58 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:13:15 2006 -0800" }, "message": "[SPARC]: Kill off these __put_user_ret things.\n\nThey are bogus and haven\u0027t been referenced in years.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "9d29a3fafd06534ad73427fee3c968c094d05b9b", "tree": "4afd7455d6249d9143acea6c4704f69aa98d311a", "parents": [ "7890f794e0e6f7dce2a5f4a03ba64b0b3fe306bd" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Feb 15 19:48:54 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:13:05 2006 -0800" }, "message": "[SPARC64]: Decode virtual-devices interrupts correctly.\n\nNeed to translate through the interrupt-map{,-mask] properties.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "7890f794e0e6f7dce2a5f4a03ba64b0b3fe306bd", "tree": "a9cc7c67498616a47108c667a9c001f9fe468318", "parents": [ "63c2a0e598c2fa769a08a6e9ad124bf270b4436e" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Feb 15 02:26:54 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:13:04 2006 -0800" }, "message": "[SPARC64]: Add prom_{start,stop}cpu_cpuid().\n\nUse prom_startcpu_cpuid() on SUN4V instead of prom_startcpu().\n\nWe should really test for \"SUNW,start-cpu-by-cpuid\" presence\nand use it if present even on SUN4U.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "7c3514e4501565d76f9e4dec43e1fc17389f4811", "tree": "e3f4766232189faaa98a59d53a44e424025e9561", "parents": [ "f03b8a546868fcf43feb455b69b152eb867606b2" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Feb 15 00:41:47 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:13:02 2006 -0800" }, "message": "[SPARC64]: Fixup TSTATE layout diagram in asm/pstate.h\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "50f4f23c3bd95afc82e931254a71e7b1b3699fd2", "tree": "5ed7cc71e1140a3a839c8d65ca95b755012d4bde", "parents": [ "3af6e01e9acfb786c5dd2862f57f206b0b3cb889" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Tue Feb 14 01:32:29 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:53 2006 -0800" }, "message": "[SPARC64]: Fix gcc-3.3.x warnings.\n\nIt doesn\u0027t like const variables being passed into\n\"i\" constraing asm operations. It\u0027s a bug, but\nthere is nothing we can really do but work around\nit.\n\nBased upon a report from Andrew Morton.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "c4bea2883974a59ab7a0ac6c01d34f7ae0e8cd8e", "tree": "3d32f942cd0a62f6ca89fe7781f59708845d7a38", "parents": [ "4bf447d6f7c2357dec8bdc24ce0fcffd71cc29c0" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Feb 13 22:56:27 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:51 2006 -0800" }, "message": "[SPARC64]: Make error codes available from sun4v_intr_get*().\n\nAnd check for errors at call sites.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "5259d5bfaf5b2953b130e9a500277a905bd37823", "tree": "3768df7a92c63a2eeec0d29aadca60ce57f36de7", "parents": [ "f4266ab45a3f08bd76c2d414a2d7a1a9dc2501c0" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Feb 13 21:15:44 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:46 2006 -0800" }, "message": "[SPARC64]: Fix comment typo in asm/hypervisor.h\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "e77227eb4e17591a6a511b9c0ff6e8ad7350c575", "tree": "be8b7f13fd2ff0543879286b04045f6c3587dda3", "parents": [ "d5eb4004303b4dd04ec83b926b5fc2d9ceda4b2e" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Feb 13 20:42:16 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:44 2006 -0800" }, "message": "[SPARC64]: Probe virtual-devices root node on sun4v.\n\nThis is where we learn how to get the interrupts\nfor things like the hypervisor console device.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "e3999574b48125c9bb0c95e3e9f1c696bf96c3e3", "tree": "a6651da06fa36c3dde33a7be5f0b7192b8442cd7", "parents": [ "10804828fd06a43ce964e9d9852332e7ff1507b1" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Feb 13 18:16:10 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:40 2006 -0800" }, "message": "[SPARC64]: Generic sun4v_build_irq().\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "6c0f402f6cc62314ef83b975f3430350dcb6055f", "tree": "394a2e981ee8fff3e6eda7aec2d20be8542ecae1", "parents": [ "85dfa19ba92f88fa1c1482f655c7247119dfdcd5" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Feb 13 00:23:32 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:37 2006 -0800" }, "message": "[SPARC64]: Implement rest of generic interrupt hypervisor calls.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "85dfa19ba92f88fa1c1482f655c7247119dfdcd5", "tree": "28038115f626e5c84bb50ad9ff5eed5dc943fcde", "parents": [ "059833eb817fec3a5a7f62fba9592749c4cebc73" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Feb 13 00:02:16 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:36 2006 -0800" }, "message": "[SPARC64]: Move devino_to_sysino out of pci_sun4v_asm.S\n\nIt is not PCI specific, it is for all system interrupts.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "cf627156c450cd5a0741b31f55181db3400d4887", "tree": "e8f44d2509f5544ee5b5d583da3e10ac99ca3629", "parents": [ "ff02e0d26f139ad95ec3a7e94f88faccaa180dff" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sun Feb 12 21:10:07 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:32 2006 -0800" }, "message": "[SPARC64]: Use inline patching for critical PTE operations.\n\nThis handles the SUN4U vs SUN4V PTE layout differences\nwith near zero performance cost.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "ff02e0d26f139ad95ec3a7e94f88faccaa180dff", "tree": "7a872c9792561c77c672ba640b80134c592d93c7", "parents": [ "221b2fb818c307e1cb47e036a1671ca554d9cd0a" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sun Feb 12 17:07:51 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:31 2006 -0800" }, "message": "[SPARC64]: Move PTE field definitions back into asm/pgtable.h\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "1a7a242c898dd131f2df005c492e9b44fb8900e0", "tree": "5f00961b9c6539951adda7bfaafda030cea39c38", "parents": [ "02fead75055246d01af56a45a9d1b311d506da3e" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sat Feb 11 23:24:30 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:28 2006 -0800" }, "message": "[SPARC64]: Recognize \"virtual-console\" as input and output console device.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "c4bce90ea2069e5a87beac806de3090ab32128d5", "tree": "3983a206c8060ef65ba17945d1c9f69e68d88b3d", "parents": [ "490384e752a43aa281ed533e9de2da36df25c337" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sat Feb 11 21:57:54 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:25 2006 -0800" }, "message": "[SPARC64]: Deal with PTE layout differences in SUN4V.\n\nYes, you heard it right, they changed the PTE layout for\nSUN4V. Ho hum...\n\nThis is the simple and inefficient way to support this.\nIt\u0027ll get optimized, don\u0027t worry.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "490384e752a43aa281ed533e9de2da36df25c337", "tree": "ec087a27a481b9a63aeda6703971acf4adeab19b", "parents": [ "459b6e621e0e15315c25bac47fa7113e5818d45d" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sat Feb 11 14:41:18 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:23 2006 -0800" }, "message": "[SPARC64]: Register kernel TSB with hypervisor.\n\nWe do this right after we take over the trap table from OBP.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "459b6e621e0e15315c25bac47fa7113e5818d45d", "tree": "4bbff0ec1dafb7fba8b247c84ad708f54cc687fe", "parents": [ "fd05068d7b22b64211f9202aa67ad44b51d44242" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sat Feb 11 12:21:20 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:23 2006 -0800" }, "message": "[SPARC64]: Fix some SUN4V TLB miss bugs.\n\nCode patching did not sign extend negative branch\noffsets correctly.\n\nKernel TLB miss path needs patching and %g4 register\npreservation in order to handle SUN4V correctly.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "02fd473bd4844befc74f7ca67cd60891e0a2d890", "tree": "4c338418dcfdd73c88d3ca8e969944be42cde60e", "parents": [ "4bdff41464c2954c6f62f849df0e73eb9fa21c65" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sat Feb 11 02:25:21 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:18 2006 -0800" }, "message": "[SPARC64]: Add SUN4V Hypervisor Console driver.\n\nSince it can do things like BREAK and HUP, we implement\nthis as a serial uart driver.\n\nThis still needs interrupt probing code, as I haven\u0027t figured\nout how interrupts will work or be probed for on SUN4V yet.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "12eaa328f9fb2d3fcb5afb682c762690d05a3cd8", "tree": "cce4e68b971757010a3e0bbf035fc65a381a3cd4", "parents": [ "18397944642cbca7fcd4a109b43ed5b4652e95b9" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Fri Feb 10 15:39:51 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:15 2006 -0800" }, "message": "[SPARC64]: Use ASI_SCRATCHPAD address 0x0 properly.\n\nThis is where the virtual address of the fault status\narea belongs.\n\nTo set it up we don\u0027t make a hypervisor call, instead\nwe call OBP\u0027s SUNW,set-trap-table with the real address\nof the fault status area as the second argument. And\nright before that call we write the virtual address into\nASI_SCRATCHPAD vaddr 0x0.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "dedacf623283cb24933ec9f7d5bf539f19173cd4", "tree": "e628dffa192236c89e3d646eb62c49ef1c98aab4", "parents": [ "7eae642f75e0f7fbce7c37b2dfe0641ff1e9ebfd" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Feb 09 22:26:34 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:13 2006 -0800" }, "message": "[SPARC64]: Add HV_PCI_TSBID() macro.\n\nFor constructing hypervisor PCI TSB IDs.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "bade5622167181844cd4e60087971c1f949e149f", "tree": "0bd0144e472786f8ba5b37a2bb90204ff6bf204b", "parents": [ "8f6a93a196ba6c569c3e8daa6e81cca7e3ba81b1" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Feb 09 22:05:54 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:11 2006 -0800" }, "message": "[SPARC64]: More SUN4V PCI controller work.\n\nAdd assembler file for PCI hypervisor calls.\nSetup basic skeleton of SUN4V PCI controller driver.\n\nAdd 32-bit devhandle to PBM struct, as this is needed for\nhypervisor calls.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "8f6a93a196ba6c569c3e8daa6e81cca7e3ba81b1", "tree": "80d4747608148c56fd8c67baf016ad4fc58610ea", "parents": [ "4cce4b7cc56abc3d7b269d09224b8297aad15138" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Feb 09 21:32:07 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:10 2006 -0800" }, "message": "[SPARC64]: Beginnings of SUN4V PCI controller support.\n\nAbstract out IOMMU operations so that we can have a different\nset of calls on sun4v, which needs to do things through\nhypervisor calls.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "5fe91cf6254c8f23d90efb5fc11fff57dd5ab8dd", "tree": "3a5d3ec9a752a7996f8e9060710fee322f2d5214", "parents": [ "ed6b0b45437dcf7ef1c48b3be413bebcc84771d8" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Feb 09 20:45:26 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:08 2006 -0800" }, "message": "[SPARC]: Clean up idprom header files.\n\nDelete unused macros, and use fixed sized types in\nsparc32 header.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "618e9ed98aed924a1fc664eb6522db4a5e927043", "tree": "08ace6185b8f9709cb22a23d329def1dae622666", "parents": [ "aa9143b9719c07fb6f1f6207790c9c5086ae07e7" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Feb 09 17:21:53 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:06 2006 -0800" }, "message": "[SPARC64]: Hypervisor TSB context switching.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "aa9143b9719c07fb6f1f6207790c9c5086ae07e7", "tree": "74d56ecc53ed0542f200d6c6257c8f051095111c", "parents": [ "12816ab38adddc9d7e9b3315d1739655dedc7c9f" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Feb 09 16:12:22 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:05 2006 -0800" }, "message": "[SPARC64]: Implement sun4v TSB miss handlers.\n\nWhen we register a TSB with the hypervisor, so that it or hardware can\nhandle TLB misses and do the TSB walk for us, the hypervisor traps\ndown to these trap when it incurs a TSB miss.\n\nProcessing is simple, we load the missing virtual address and context,\nand do a full page table walk.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "d82ace7dc4073b090a55b9740700e32b9a9ae302", "tree": "d5aa8e10664b05bbfe31eacf95e2066c03cab102", "parents": [ "1d2f1f90a1e004b0c1b8a73ed4394a93f09104b3" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Feb 09 02:52:44 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:03 2006 -0800" }, "message": "[SPARC64]: Detect sun4v early in boot process.\n\nWe look for \"SUNW,sun4v\" in the \u0027compatible\u0027 property\nof the root OBP device tree node.\n\nProtect every %ver register access, to make sure it is\nnot touched on sun4v, as %ver is hyperprivileged there.\n\nLock kernel TLB entries using hypervisor calls instead of\ncalls into OBP.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "1d2f1f90a1e004b0c1b8a73ed4394a93f09104b3", "tree": "2fcc0840b52218631020311d7b6d785e9a15db6a", "parents": [ "5b0c0572fcd6204675c5f7ddfa572b5017f817dd" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Feb 08 16:41:20 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:02 2006 -0800" }, "message": "[SPARC64]: Sun4v cross-call sending support.\n\nTechnically the hypervisor call supports sending in a list\nof all cpus to get the cross-call, but I only pass in one\ncpu at a time for now.\n\nThe multi-cpu support is there, just ifdef\u0027d out so it\u0027s easy to\nenable or delete it later.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "5b0c0572fcd6204675c5f7ddfa572b5017f817dd", "tree": "1075a61338e887bd6d4ecd4517646ef95dc09fbc", "parents": [ "ac29c11d4cd4fa1fac968e99998a956405732f2f" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Feb 08 02:53:50 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:12:01 2006 -0800" }, "message": "[SPARC64]: Sun4v interrupt handling.\n\nSun4v has 4 interrupt queues: cpu, device, resumable errors,\nand non-resumable errors. A set of head/tail offset pointers\nhelp maintain a work queue in physical memory. The entries\nare 64-bytes in size.\n\nEach queue is allocated then registered with the hypervisor\nas we bring cpus up.\n\nThe two error queues each get a kernel side buffer that we\nuse to quickly empty the main interrupt queue before we\ncall up to C code to log the event and possibly take evasive\naction.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "7202c55c5c57d2ad4611a751544c9368d7fba93a", "tree": "282219004791550b35f7de50d449d96f396be8f6", "parents": [ "3bfd6f3e77f58479ec53aa91d0b078abbb4c0868" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Tue Feb 07 22:53:56 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:58 2006 -0800" }, "message": "[SPARC64]: Add sun4v mondo queue bases to struct trap_per_cpu.\n\nAlso, correct TRAP_PER_CPU_FAULT_INFO define, it should be\n0x40 not 0x20.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "3bfd6f3e77f58479ec53aa91d0b078abbb4c0868", "tree": "1ec49afc137feed4e70b1be7728920165e90b838", "parents": [ "8b11bd12aff76e02cdc2cbc9e439bba88d281223" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Tue Feb 07 22:49:38 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:57 2006 -0800" }, "message": "[SPARC64]: Fix some comment typos in asm/hypervisor.h\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "8b11bd12aff76e02cdc2cbc9e439bba88d281223", "tree": "903ab8830616bfbe5a821e4359f642842c8060a4", "parents": [ "481295f982b21b1dbe71cbf41d3a93028fee30d1" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Tue Feb 07 22:13:05 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:56 2006 -0800" }, "message": "[SPARC64]: Patch up mmu context register writes for sun4v.\n\nsun4v uses ASI_MMU instead of ASI_DMMU\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "481295f982b21b1dbe71cbf41d3a93028fee30d1", "tree": "5b1af84a7f83021698bcf138c8875d7290e65282", "parents": [ "89a5264f065672a882f555228000614a6b2182b7" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Tue Feb 07 21:51:08 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:55 2006 -0800" }, "message": "[SPARC64]: Register per-cpu fault status area with sun4v hypervisor.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "89a5264f065672a882f555228000614a6b2182b7", "tree": "4fa226fed4b8119096e50ff8c915d2c0f8d6cd6d", "parents": [ "8591e3027235d6d11b958e43379f2ee7b7114841" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Tue Feb 07 21:15:41 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:55 2006 -0800" }, "message": "[SPARC64]: asm/cpudata.h needs asm/asi.h\n\nFor the expansion of __GET_CPUID() on SMP.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "df7d6aec96ab98cb182dd5138a85bdc363a9bf0d", "tree": "d71808a328639a32b16c53b24ce8a6b641f43ad2", "parents": [ "d257d5da39a78b32721ca84b2ba7f461f2f7ed7f" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Tue Feb 07 00:00:16 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:53 2006 -0800" }, "message": "[SPARC64]: Rename gl_{1,2}insn_patch --\u003e sun4v_{1,2}insn_patch\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "d257d5da39a78b32721ca84b2ba7f461f2f7ed7f", "tree": "ac28d377688ebe13a4d38e05f4ff65ba73d8652a", "parents": [ "840aaef8db32572b6d11e0d5cb5e6efcbc812000" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Feb 06 23:44:37 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:52 2006 -0800" }, "message": "[SPARC64]: Initial sun4v TLB miss handling infrastructure.\n\nThings are a little tricky because, unlike sun4u, we have\nto:\n\n1) do a hypervisor trap to do the TLB load.\n2) do the TSB lookup calculations by hand\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "45fec05f805a113372c9a7ff4c653ac749f6921c", "tree": "36fc99d10656775acb8e9442719447d64ac30a03", "parents": [ "314981ac7177a933319e3c071a5cf0a579205e6e" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sun Feb 05 22:27:28 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:50 2006 -0800" }, "message": "[SPARC64]: Sanitize %pstate writes for sun4v.\n\nIf we\u0027re just switching between different alternate global\nsets, nop it out on sun4v. Also, get rid of all of the\nalternate global save/restore in the OBP CIF trampoline code.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "314981ac7177a933319e3c071a5cf0a579205e6e", "tree": "11895da391ba91195d6d7a67debaa32a28c1215e", "parents": [ "936f482af1743141d637483ec10eb881537c26dc" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sun Feb 05 21:59:03 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:49 2006 -0800" }, "message": "[SPARC64]: Kill all %pstate changes in context switch code.\n\nThey are totally unnecessary because:\n\n1) Interrupts are already disabled when switch_to()\n runs.\n\n2) We don\u0027t use hard-coded alternate globals any longer.\n\nThis found a case in rtrap, which still assumed alternate\nglobal %g6 was current_thread_info(), and that is fixed\nby this changeset as well.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "936f482af1743141d637483ec10eb881537c26dc", "tree": "913da89a4d9f4038c510c9ecf2f5957b0f6d167f", "parents": [ "6e02493a7f33ac89e698b980a657d77ab2749eaf" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sun Feb 05 21:29:28 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:48 2006 -0800" }, "message": "[SPARC64]: Add initial code to twiddle %gl on trap entry/exit.\n\nInstead of setting/clearing PSTATE_AG we have to change\nthe %gl register value on sun4v.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "d619d7f11670f5b1cfca30e6645e44c8a6014820", "tree": "cad4f39ece5f59f2a16327a13e25863d2f466f14", "parents": [ "d96b81533ba3d5775e45aee6986b2aa33c10801c" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sat Feb 04 23:59:38 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:46 2006 -0800" }, "message": "[SPARC64]: Add define for \"GL\" field of sun4v %tstate register.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "d96b81533ba3d5775e45aee6986b2aa33c10801c", "tree": "334af39452d650cc14b389c58a30cc54e9e130dd", "parents": [ "e1c21c4f476f2270c98aad1fe55e5f33e25f77f5" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sat Feb 04 15:40:53 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:45 2006 -0800" }, "message": "[SPARC64]: Add sun4v case to __GET_CPUID() patch tables.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "e1c21c4f476f2270c98aad1fe55e5f33e25f77f5", "tree": "830ae146cd0cf807d949b09641ec8e82c6ed8149", "parents": [ "277b6dd9600613b01f66cadef2f0065514fecf69" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sat Feb 04 03:12:14 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:44 2006 -0800" }, "message": "[SPARC64]: Sun4v interrupt queue register definitions.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "277b6dd9600613b01f66cadef2f0065514fecf69", "tree": "f9e9f42f05b3204fe17778a999fecd9fa63b1e7e", "parents": [ "d398ee230f94a8ba386d8abb63f4fea129e4eaba" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sat Feb 04 03:12:02 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:44 2006 -0800" }, "message": "[SPARC64]: Sun4v scratchpad register layout.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "d398ee230f94a8ba386d8abb63f4fea129e4eaba", "tree": "bcad4a48333ddbdd04f890d7136c0e3efb829cec", "parents": [ "398d10830843bda7798f71052b54a5341a8ddd53" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sat Feb 04 03:11:50 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:43 2006 -0800" }, "message": "[SPARC64]: Sun4v specific ASI defines.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "30ddbdb03339fc62480ddbff800a44066bb14455", "tree": "6d064ae396014418601acd8fc678463750f2bffa", "parents": [ "a43fe0e789f5445f5224511034f410adf11f153b" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sat Feb 04 03:11:17 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:41 2006 -0800" }, "message": "[SPARC64]: Add Niagara init-store twin-load ASI defines.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "1633a53c79498455b16d051451f4e3f83ab4e7dd", "tree": "3f28700c60a0464879833a6d76875f387388e20c", "parents": [ "52bf082f0a6e49e08ed99d4d9518c662dc735c7a" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sat Feb 04 03:09:03 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:39 2006 -0800" }, "message": "[SPARC64]: Add \u0027hypervisor\u0027 to ultra_tlb_type enumeration.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "766f861fbbd968a1850295ed6dec4504b4500dcc", "tree": "76729285f448b58c812469b1bddf64f92e9f8d6e", "parents": [ "314ef6859750b6539eac48d78059bb7986f29cb1" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sat Feb 04 03:01:45 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:37 2006 -0800" }, "message": "[SPARC64]: SUN4V hypervisor interface defines.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "314ef6859750b6539eac48d78059bb7986f29cb1", "tree": "26c7da386349c1cf377225356e1012ae62da6f07", "parents": [ "ffe483d55229fadbaf4cc7316d47024a24ecd1a2" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sat Feb 04 00:10:01 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:36 2006 -0800" }, "message": "[SPARC64]: Refine register window trap handling.\n\nWhen saving and restoing trap state, do the window spill/fill\nhandling inline so that we never trap deeper than 2 trap levels.\nThis is important for chips like Niagara.\n\nThe window fixup code is massively simplified, and many more\nimprovements are now possible.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "ffe483d55229fadbaf4cc7316d47024a24ecd1a2", "tree": "70bdb6c94d5b3512a7b2a3ff06979ac2e4e869bf", "parents": [ "92704a1c63c3b481870d02636d0b5a70c7e21cd1" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Thu Feb 02 21:55:10 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:35 2006 -0800" }, "message": "[SPARC64]: Add explicit register args to trap state loading macros.\n\nThis, as well as making the code cleaner, allows a simplification in\nthe TSB miss handling path.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "92704a1c63c3b481870d02636d0b5a70c7e21cd1", "tree": "098f96da6ab50a1d878425e2b91a9cf22f78ac80", "parents": [ "f4e841da30b4bcbb8f1cc20a01157a788ff58b21" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sun Feb 26 23:27:19 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:35 2006 -0800" }, "message": "[SPARC64]: Refine code sequences to get the cpu id.\n\nOn uniprocessor, it\u0027s always zero for optimize that.\n\nOn SMP, the jmpl to the stub kills the return address stack in the cpu\nbranch prediction logic, so expand the code sequence inline and use a\ncode patching section to fix things up. This also always better and\nexplicit register selection, which will be taken advantage of in a\nfuture changeset.\n\nThe hard_smp_processor_id() function is big, so do not inline it.\n\nFix up tests for Jalapeno to also test for Serrano chips too. These\ntests want \"jbus Ultra-IIIi\" cases to match, so that is what we should\ntest for.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "7bec08e38a7d0f088994f6eec9b6374652ea71fb", "tree": "df0c24e8417d08aff3d3de7d9dc7b13c4e05931b", "parents": [ "517af33237ecfc3c8a93b335365fa61e741ceca4" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Thu Feb 02 01:20:18 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:33 2006 -0800" }, "message": "[SPARC64]: Correctable ECC errors cannot occur at trap level \u003e 0.\n\nThe are distrupting, which by the sparc v9 definition means they\ncan only occur when interrupts are enabled in the %pstate register.\nThis never occurs in any of the trap handling code running at\ntrap levels \u003e 0.\n\nSo just mark it as an unexpected trap.\n\nThis allows us to kill off the cee_stuff member of struct thread_info.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "517af33237ecfc3c8a93b335365fa61e741ceca4", "tree": "58eff40eb4c517c4fd49fd347d38273ee1e1ee4b", "parents": [ "b0fd4e49aea8a460afab7bc67cd618e2d19291d4" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Wed Feb 01 15:55:21 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:32 2006 -0800" }, "message": "[SPARC64]: Access TSB with physical addresses when possible.\n\nThis way we don\u0027t need to lock the TSB into the TLB.\nThe trick is that every TSB load/store is registered into\na special instruction patch section. The default uses\nvirtual addresses, and the patch instructions use physical\naddress load/stores.\n\nWe can\u0027t do this on all chips because only cheetah+ and later\nhave the physical variant of the atomic quad load.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "b0fd4e49aea8a460afab7bc67cd618e2d19291d4", "tree": "a596c793cbc918bdcea462bcfe2f2f41fe8afeb2", "parents": [ "30a6ecad9670d97c9d0fbfa7d80970aeb339bdec" ], "author": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Tue Jan 31 23:13:29 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:31 2006 -0800" }, "message": "[SPARC64]: Kill out-of-date commentary in asm-sparc64/tsb.h\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "86b818687d4894063ecd1190e54717a0cce8c009", "tree": "d2951295358502c88f7fe0c02517d729cff4eb9a", "parents": [ "9954863975910a1b9372b7d5006a6cba43bdd288" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jan 31 18:34:51 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:29 2006 -0800" }, "message": "[SPARC64]: Fix race in LOAD_PER_CPU_BASE()\n\nSince we use %g5 itself as a temporary, it can get clobbered\nif we take an interrupt mid-stream and thus cause end up with\nthe final %g5 value too early as a result of rtrap processing.\n\nSet %g5 at the very end, atomically, to avoid this problem.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "2f7ee7c63f08b7f883b710a29d91c1891b81b8e1", "tree": "c0539482cecfd3cbc0b983a23058315811dc8b55", "parents": [ "a8b900d801697609d1b56cc9c110148c64678068" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jan 31 18:33:49 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:26 2006 -0800" }, "message": "[SPARC64]: Increase swapper_tsb size to 32K.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "a8b900d801697609d1b56cc9c110148c64678068", "tree": "47602480aba29d17f8a79cc76dfe8af4d62f2599", "parents": [ "3487d1d4414fbfab5d98ec559e6f84f55520cb15" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jan 31 18:33:37 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:25 2006 -0800" }, "message": "[SPARC64]: Kill sole argument passed to setup_tba().\n\nNo longer used, and move extern declaration to a header file.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "4753eb2ac7022b999e5e484f1a5dc001dba22bd3", "tree": "138321ebd3b3c3aeb99517ec5158a65f556da774", "parents": [ "96c6e0d8e2a0eb1338751598be47fa1ffed91704" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jan 31 18:32:44 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:21 2006 -0800" }, "message": "[SPARC64]: Fix incorrect TSB lock bit handling.\n\nThe TSB_LOCK_BIT define is actually a special\nvalue shifted down by 32-bits for the assembler\ncode macros.\n\nIn C code, this isn\u0027t what we want.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "b70c0fa1613c4f69b4a340a0e2bee387560ebbb1", "tree": "f7bf22ab75cb9118f5772353fef6efd923faa212", "parents": [ "bd40791e1d289d807b8580abe1f117e9c62894e4" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jan 31 18:32:04 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:19 2006 -0800" }, "message": "[SPARC64]: Preload TSB entries from update_mmu_cache().\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "bd40791e1d289d807b8580abe1f117e9c62894e4", "tree": "2b47e24c8dc0e668dfd7ba0e3879165180c49c65", "parents": [ "98c5584cfc47932c4f3ccf5eee2e0bae1447b85e" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jan 31 18:31:38 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:18 2006 -0800" }, "message": "[SPARC64]: Dynamically grow TSB in response to RSS growth.\n\nAs the RSS grows, grow the TSB in order to reduce the likelyhood\nof hash collisions and thus poor hit rates in the TSB.\n\nThis definitely needs some serious tuning.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "98c5584cfc47932c4f3ccf5eee2e0bae1447b85e", "tree": "c067ac8bfc081bbe0b3073374cb15708458e04ab", "parents": [ "09f94287f7260e03bbeab497e743691fafcc22c3" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jan 31 18:31:20 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:17 2006 -0800" }, "message": "[SPARC64]: Add infrastructure for dynamic TSB sizing.\n\nThis also cleans up tsb_context_switch(). The assembler\nroutine is now __tsb_context_switch() and the former is\nan inline function that picks out the bits from the mm_struct\nand passes it into the assembler code as arguments.\n\nsetup_tsb_parms() computes the locked TLB entry to map the\nTSB. Later when we support using the physical address quad\nload instructions of Cheetah+ and later, we\u0027ll simply use\nthe physical address for the TSB register value and set\nthe map virtual and PTE both to zero.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "09f94287f7260e03bbeab497e743691fafcc22c3", "tree": "ebdb365a7cfe25a1587a930d852f2eaa0e1e773a", "parents": [ "56fb4df6da76c35dca22036174e2d1edef83ff1f" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jan 31 18:31:06 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:16 2006 -0800" }, "message": "[SPARC64]: TSB refinements.\n\nMove {init_new,destroy}_context() out of line.\n\nDo not put huge pages into the TSB, only base page size translations.\nThere are some clever things we could do here, but for now let\u0027s be\ncorrect instead of fancy.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "56fb4df6da76c35dca22036174e2d1edef83ff1f", "tree": "b39f152ec9ed682edceca965a85680fd4bf736a7", "parents": [ "3c936465249f863f322154ff1aaa628b84ee5750" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sun Feb 26 23:24:22 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:16 2006 -0800" }, "message": "[SPARC64]: Elminate all usage of hard-coded trap globals.\n\nUltraSPARC has special sets of global registers which are switched to\nfor certain trap types. There is one set for MMU related traps, one\nset of Interrupt Vector processing, and another set (called the\nAlternate globals) for all other trap types.\n\nFor what seems like forever we\u0027ve hard coded the values in some of\nthese trap registers. Some examples include:\n\n1) Interrupt Vector global %g6 holds current processors interrupt\n work struct where received interrupts are managed for IRQ handler\n dispatch.\n\n2) MMU global %g7 holds the base of the page tables of the currently\n active address space.\n\n3) Alternate global %g6 held the current_thread_info() value.\n\nSuch hardcoding has resulted in some serious issues in many areas.\nThere are some code sequences where having another register available\nwould help clean up the implementation. Taking traps such as\ncross-calls from the OBP firmware requires some trick code sequences\nwherein we have to save away and restore all of the special sets of\nglobal registers when we enter/exit OBP.\n\nWe were also using the IMMU TSB register on SMP to hold the per-cpu\narea base address, which doesn\u0027t work any longer now that we actually\nuse the TSB facility of the cpu.\n\nThe implementation is pretty straight forward. One tricky bit is\ngetting the current processor ID as that is different on different cpu\nvariants. We use a stub with a fancy calling convention which we\npatch at boot time. The calling convention is that the stub is\nbranched to and the (PC - 4) to return to is in register %g1. The cpu\nnumber is left in %g6. This stub can be invoked by using the\n__GET_CPUID macro.\n\nWe use an array of per-cpu trap state to store the current thread and\nphysical address of the current address space\u0027s page tables. The\nTRAP_LOAD_THREAD_REG loads %g6 with the current thread from this\ntable, it uses __GET_CPUID and also clobbers %g1.\n\nTRAP_LOAD_IRQ_WORK is used by the interrupt vector processing to load\nthe current processor\u0027s IRQ software state into %g6. It also uses\n__GET_CPUID and clobbers %g1.\n\nFinally, TRAP_LOAD_PGD_PHYS loads the physical address base of the\ncurrent address space\u0027s page tables into %g7, it clobbers %g1 and uses\n__GET_CPUID.\n\nMany refinements are possible, as well as some tuning, with this stuff\nin place.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "3c936465249f863f322154ff1aaa628b84ee5750", "tree": "2bd7a229236f197d20a655133370e5d0c1bf886c", "parents": [ "05e28f9de65a38bb0c769080e91b6976e7e1e70c" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jan 31 18:30:27 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:14 2006 -0800" }, "message": "[SPARC64]: Kill pgtable quicklists and use SLAB.\n\nTaking a nod from the powerpc port.\n\nWith the per-cpu caching of both the page allocator and SLAB, the\npgtable quicklist scheme becomes relatively silly and primitive.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "05e28f9de65a38bb0c769080e91b6976e7e1e70c", "tree": "e1d3fcc1381ea6612ce4c082ca8596e84b637216", "parents": [ "74bf4312fff083ab25c3f357cc653ada7995e5f6" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jan 31 18:30:13 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:13 2006 -0800" }, "message": "[SPARC64]: No need to D-cache color page tables any longer.\n\nUnlike the virtual page tables, the new TSB scheme does not\nrequire this ugly hack.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "74bf4312fff083ab25c3f357cc653ada7995e5f6", "tree": "c23dea461e32485f4cd7ca4b8c33c632655eb906", "parents": [ "30d4d1ffed7098afe2641536d67eef150499da02" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Jan 31 18:29:18 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Mon Mar 20 01:11:13 2006 -0800" }, "message": "[SPARC64]: Move away from virtual page tables, part 1.\n\nWe now use the TSB hardware assist features of the UltraSPARC\nMMUs.\n\nSMP is currently knowingly broken, we need to find another place\nto store the per-cpu base pointers. We hid them away in the TSB\nbase register, and that obviously will not work any more :-)\n\nAnother known broken case is non-8KB base page size.\n\nAlso noticed that flush_tlb_all() is not referenced anywhere, only\nthe internal __flush_tlb_all() (local cpu only) is used by the\nsparc64 port, so we can get rid of flush_tlb_all().\n\nThe kernel gets it\u0027s own 8KB TSB (swapper_tsb) and each address space\ngets it\u0027s own private 8K TSB. Later we can add code to dynamically\nincrease the size of per-process TSB as the RSS grows. An 8KB TSB is\ngood enough for up to about a 4MB RSS, after which the TSB starts to\nincur many capacity and conflict misses.\n\nWe even accumulate OBP translations into the kernel TSB.\n\nAnother area for refinement is large page size support. We could use\na secondary address space TSB to handle those.\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "4657190936883adb819f81957e33439d447c0035", "tree": "70342debfb779a8b10d2a8440c1ae99593806079", "parents": [ "4a29cc2e503b33a1e96db4c3f9a94165f153f259", "9007c9a2b03ea325ee593a161dbf01dbb8222d7e" ], "author": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Sun Mar 19 21:12:00 2006 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Sun Mar 19 21:12:00 2006 -0800" }, "message": "Merge branch \u0027upstream\u0027 of git://ftp.linux-mips.org/pub/scm/upstream-linus\n\n* \u0027upstream\u0027 of git://ftp.linux-mips.org/pub/scm/upstream-linus:\n [MIPS] SB1: Check for -mno-sched-prolog if building corelis debug kernel.\n [MIPS] Sibyte: Fix race in sb1250_gettimeoffset().\n [MIPS] Sibyte: Fix interrupt timer off by one bug.\n [MIPS] Sibyte: Fix M_SCD_TIMER_INIT and M_SCD_TIMER_CNT wrong field width.\n [MIPS] Protect more of timer_interrupt() by xtime_lock.\n [MIPS] Work around bad code generation for \u003casm/io.h\u003e.\n [MIPS] Simple patch to power off DBAU1200\n [MIPS] Fix DBAu1550 software power off.\n [MIPS] local_r4k_flush_cache_page fix\n [MIPS] SB1: Fix interrupt disable hazard.\n [MIPS] Get rid of the IP22-specific code in arclib.\n Update MAINTAINERS entry for MIPS.\n" }, { "commit": "4a29cc2e503b33a1e96db4c3f9a94165f153f259", "tree": "74645b5ef3a92ad9857ed63d6446e2be0535060c", "parents": [ "c7c694d196a39af6e644e24279953d04f30362db" ], "author": { "name": "Michael Chan", "email": "mchan@broadcom.com", "time": "Sun Mar 19 13:21:12 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sun Mar 19 13:21:12 2006 -0800" }, "message": "[TG3]: 40-bit DMA workaround part 2\n\nThe 40-bit DMA workaround recently implemented for 5714, 5715, and\n5780 needs to be expanded because there may be other tg3 devices\nbehind the EPB Express to PCIX bridge in the 5780 class device.\n\nFor example, some 4-port card or mother board designs have 5704 behind\nthe 5714.\n\nAll devices behind the EPB require the 40-bit DMA workaround.\n\nThanks to Chris Elmquist again for reporting the problem and testing\nthe patch.\n\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "c7c694d196a39af6e644e24279953d04f30362db", "tree": "cb78fead47ce86245179fe0a52119c70b30b59cb", "parents": [ "60a6dc55b93b3321afa52f650a149fb7e87fa85a" ], "author": { "name": "Ralf Baechle DL5RB", "email": "ralf@linux-mips.org", "time": "Sun Mar 19 13:20:06 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sun Mar 19 13:20:06 2006 -0800" }, "message": "[AX.25]: Fix potencial memory hole.\n\nIf the AX.25 dialect chosen by the sysadmin is set to DAMA master / 3\n(or DAMA slave / 2, if CONFIG_AX25_DAMA_SLAVE\u003dn) ax25_kick() will fall\nthrough the switch statement without calling ax25_send_iframe() or any\nother function that would eventually free skbn thus leaking the packet.\n\nFix by restricting the sysctl inferface to allow only actually supported\nAX.25 dialects.\n\nThe system administration mistake needed for this to happen is rather\nunlikely, so this is an uncritical hole.\n\nCoverity #651.\n\nSigned-off-by: Ralf Baechle DL5RB \u003cralf@linux-mips.org\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "a904f7478561464f9fe74929b81fec237b6ff4c3", "tree": "6018ab25ea391aad0f4f33f0613e2b9fdbe36637", "parents": [ "4308cb16286c96d980570cc5319173b524220c06" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Wed Mar 15 00:03:29 2006 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Mar 18 16:59:30 2006 +0000" }, "message": "[MIPS] Sibyte: Fix race in sb1250_gettimeoffset().\n \nFrom Dave Johnson \u003cdjohnson+linuxmips@sw.starentnetworks.com\u003e:\n \nsb1250_gettimeoffset() simply reads the current cpu 0 timer remaining\nvalue, however once this counter reaches 0 and the interrupt is raised,\nit immediately resets and begins to count down again.\n \nIf sb1250_gettimeoffset() is called on cpu 1 via do_gettimeofday() after\nthe timer has reset but prior to cpu 0 processing the interrupt and\ntaking write_seqlock() in timer_interrupt() it will return a full value\n(or close to it) causing time to jump backwards 1ms. Once cpu 0 handles\nthe interrupt and timer_interrupt() gets far enough along it will jump\nforward 1ms.\n \nFix this problem by implementing mips_hpt_*() on sb1250 using a spare\ntimer unrelated to the existing periodic interrupt timers. It runs at\n1Mhz with a full 23bit counter. This eliminated the custom\ndo_gettimeoffset() for sb1250 and allowed use of the generic\nfixed_rate_gettimeoffset() using mips_hpt_*() and timerhi/timerlo.\n \nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "a77f124294822203660b0926392b963cfa72fcf4", "tree": "f35e524abbfe9f6d75b99ffbc35a7592b9f4964d", "parents": [ "d6bd0e6b32ea72be91e5789b1e838c244f8a05d9" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Mar 14 23:47:35 2006 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Mar 18 16:59:29 2006 +0000" }, "message": "[MIPS] Sibyte: Fix M_SCD_TIMER_INIT and M_SCD_TIMER_CNT wrong field width.\n \nFrom Dave Johnson \u003cdjohnson+linuxmips@sw.starentnetworks.com\u003e:\n \nField width should be 23 bits not 20 bits.\n \nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "966f4406d903a4214fdc74bec54710c6232a95b8", "tree": "20d7f57eae99fe83b8fbdae112a6a0facc5b552d", "parents": [ "66a9a4ffda3474b193f36ed579cee06c597952f3" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Wed Mar 15 11:36:31 2006 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Mar 18 16:59:28 2006 +0000" }, "message": "[MIPS] Work around bad code generation for \u003casm/io.h\u003e.\n \nIf a call to set_io_port_base() was being followed by usage of\nmips_io_port_base in the same function gcc was possibly using the old\nvalue due to some clever abuse of const. Adding a barrier will keep\nthe optimization and result in correct code with latest gcc.\n \nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "de62893bc0725f8b5f0445250577cd7a10b2d8f8", "tree": "3a5d77b8e8aa66113431ebe287c552749c2e8fee", "parents": [ "a3c4946db4fe64cb21b66a09e89890678aac6d65" ], "author": { "name": "Atsushi Nemoto", "email": "anemo@mba.ocn.ne.jp", "time": "Mon Mar 13 18:23:03 2006 +0900" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Mar 18 16:59:27 2006 +0000" }, "message": "[MIPS] local_r4k_flush_cache_page fix\n \nIf dcache_size !\u003d icache_size or dcache_size !\u003d scache_size, or\nset-associative cache, icache/scache does not flushed properly. Make\nblast_?cache_page_indexed() masks its index value correctly. Also,\nuse physical address for physically indexed pcache/scache.\n \nSigned-off-by: Atsushi Nemoto \u003canemo@mba.ocn.ne.jp\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "a3c4946db4fe64cb21b66a09e89890678aac6d65", "tree": "3b63d5e765af3eedbc1cda84135f1b702a43a6f2", "parents": [ "3a2f735700332621274aca752be3b6f839fa47e7" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Mar 13 16:16:29 2006 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Mar 18 16:59:26 2006 +0000" }, "message": "[MIPS] SB1: Fix interrupt disable hazard.\n \nThe SB1 core has a three cycle interrupt disable hazard but we were\nwrongly treating it as fully interlocked.\n \nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "265a92856b17524c87da0258ac0d3cec80ae1d35", "tree": "31ebb3ef3c990ea64a1b93a1785d2abafe8534ec", "parents": [ "6f5e6b9e69bf043074a0edabe3d271899c34eb79" ], "author": { "name": "Alexey Kuznetsov", "email": "kuznet@ms2.inr.ac.ru", "time": "Fri Mar 17 16:05:43 2006 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Fri Mar 17 16:05:43 2006 -0800" }, "message": "[NET]: Fix race condition in sk_wait_event().\n\nIt is broken, the condition is checked out of socket lock. It is\nwonderful the bug survived for so long time.\n\n[ This fixes bugzilla #6233:\n race condition in tcp_sendmsg when connection became established ]\n\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "485ff09990416c75ae9593ddc71619939ab9dd51", "tree": "ca5a5681ba24ca74b296af07d5b4269a9564e60b", "parents": [ "5466eb5d0ad5e9d4238da71a2a9bd216985a4849", "1ae5db3742a0cfaf347231ff0bf181132c64e883" ], "author": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Thu Mar 16 09:13:34 2006 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Thu Mar 16 09:13:34 2006 -0800" }, "message": "Merge git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc-merge\n\n* git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc-merge:\n powerpc: update defconfigs\n [PATCH] powerpc: properly configure DDR/P5IOC children devs\n [PATCH] powerpc: remove duplicate EXPORT_SYMBOLS\n [PATCH] powerpc: RTC memory corruption\n [PATCH] powerpc: enable NAP only on cpus who support it to avoid memory corruption\n [PATCH] powerpc: Clarify wording for CRASH_DUMP Kconfig option\n [PATCH] powerpc/64: enable CONFIG_BLK_DEV_SL82C105\n [PATCH] powerpc: correct cacheflush loop in zImage\n powerpc: Fix problem with time going backwards\n powerpc: Disallow lparcfg being a module\n" }, { "commit": "92eb4602eb5c37db86cd9d2b1f4c8ca304fbc49f", "tree": "d6f53b85f0071e914cd1fa5d363259d584f1d3b2", "parents": [ "920573bd03bf690135967b5022362d34ede589c3" ], "author": { "name": "John Rose", "email": "johnrose@austin.ibm.com", "time": "Tue Mar 14 17:46:45 2006 -0600" }, "committer": { "name": "Paul Mackerras", "email": "paulus@samba.org", "time": "Thu Mar 16 16:55:07 2006 +1100" }, "message": "[PATCH] powerpc: properly configure DDR/P5IOC children devs\n\nThe dynamic add path for PCI Host Bridges can fail to configure children\nadapters under P5IOC controllers. It fails to properly fixup bus/device\nresources, and it fails to properly enable EEH. Both of these steps\nneed to occur before any children devices are enabled in\npci_bus_add_devices().\n\nSigned-off-by: John Rose \u003cjohnrose@austin.ibm.com\u003e\nSigned-off-by: Paul Mackerras \u003cpaulus@samba.org\u003e\n" }, { "commit": "dabaeff06cca86048cfa3f74ce59688bc3addba9", "tree": "58fbe5c7cf2770f529b7b01c7823e295f2aba632", "parents": [ "84dff1a73013dbdd7d770c332ab84cbfed24741b" ], "author": { "name": "Ben Dooks", "email": "ben-linux@fluff.org", "time": "Wed Mar 15 23:17:26 2006 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Mar 15 23:17:26 2006 +0000" }, "message": "[ARM] 3364/1: [cleanup] warning fix - definitions for enable_hlt and disable_hlt\n\nPatch from Ben Dooks\n\nThe enable_hlt and disable_hlt should be declared in\ninclude/asm/setup.h. This fixes sparse errors from\narch/arm/kernel/process.c\n\nSigned-off-by: Ben Dooks \u003cben-linux@fluff.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "7cafae52381395d24b83996eca7a7b53ab6a8827", "tree": "05b3cfb71c7131aaabe3b78b6f0278e91cba5147", "parents": [ "ba244fe9005323452428fee4b4b7d0c70a06b627", "cdaabbd74b15296acf09215355a7f3b07b92b83e" ], "author": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Sun Mar 12 14:56:02 2006 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Sun Mar 12 14:56:02 2006 -0800" }, "message": "Merge master.kernel.org:/home/rmk/linux-2.6-arm\n\n* master.kernel.org:/home/rmk/linux-2.6-arm:\n [ARM] iwmmxt thread state alignment\n [ARM] 3350/1: Enable 1-wire on ARM\n [ARM] 3356/1: Workaround for the ARM1136 I-cache invalidation problem\n [ARM] 3355/1: NSLU2: remove propmt depends\n [ARM] 3354/1: NAS100d: fix power led handling\n [ARM] Fix muldi3.S\n" }, { "commit": "cdaabbd74b15296acf09215355a7f3b07b92b83e", "tree": "da2e2ce07a31eb10cb3649005479a9588ba22809", "parents": [ "04916c0ef482335cb0ae575dbc5a1d97619840cd" ], "author": { "name": "Russell King", "email": "rmk@dyn-67.arm.linux.org.uk", "time": "Sun Mar 12 22:36:06 2006 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Mar 12 22:36:06 2006 +0000" }, "message": "[ARM] iwmmxt thread state alignment\n\nThis patch removes the reliance of iwmmxt on hand coded alignments.\nSince thread_info is always 8K aligned, specifying that fpstate is\n8-byte aligned achieves the same effect without needing to resort\nto hand coded alignments.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "7cd9013be6c22f3ff6f777354f766c8c0b955e17", "tree": "328e45aadb4c5bc9b6cd530be03572070201f5e5", "parents": [ "27d162e26a873883937b64526445877bd3341d23" ], "author": { "name": "Christoph Hellwig", "email": "hch@lst.de", "time": "Sat Mar 11 03:27:18 2006 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Sat Mar 11 09:19:34 2006 -0800" }, "message": "[PATCH] remove __put_task_struct_cb export again\n\nThe patch \u0027[PATCH] RCU signal handling\u0027 [1] added an export for\n__put_task_struct_cb, a put_task_struct helper newly introduced in that\npatch. But the put_task_struct couldn\u0027t be used modular previously as\n__put_task_struct wasn\u0027t exported. There are not callers of it in modular\ncode, and it shouldn\u0027t be exported because we don\u0027t want drivers to hold\nreferences to task_structs.\n\nThis patch removes the export and folds __put_task_struct into\n__put_task_struct_cb as there\u0027s no other caller.\n\n[1] http://www2.kernel.org/git/gitweb.cgi?p\u003dlinux/kernel/git/torvalds/linux-2.6.git;a\u003dcommit;h\u003de56d090310d7625ecb43a1eeebd479f04affb48b\n\nSigned-off-by: Christoph Hellwig \u003chch@lst.de\u003e\nAcked-by: Paul E. McKenney \u003cpaulmck@us.ibm.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" }, { "commit": "0adb25d2e71ab047423d6fc63d5d184590d0a66f", "tree": "0fd00ea22c07c88c3f24085cbf89f0a272f56697", "parents": [ "8bd0ee93fef9733c72fef1817330b3ee2b71cf9d" ], "author": { "name": "Kirill Korotaev", "email": "dev@openvz.org", "time": "Sat Mar 11 03:27:13 2006 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Sat Mar 11 09:19:34 2006 -0800" }, "message": "[PATCH] ext3: ext3_symlink should use GFP_NOFS allocations inside\n\nThis patch fixes illegal __GFP_FS allocation inside ext3 transaction in\next3_symlink(). Such allocation may re-enter ext3 code from\ntry_to_free_pages. But JBD/ext3 code keeps a pointer to current journal\nhandle in task_struct and, hence, is not reentrable.\n\nThis bug led to \"Assertion failure in journal_dirty_metadata()\" messages.\n\nhttp://bugzilla.openvz.org/show_bug.cgi?id\u003d115\n\nSigned-off-by: Andrey Savochkin \u003csaw@saw.sw.com.sg\u003e\nSigned-off-by: Kirill Korotaev \u003cdev@openvz.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" }, { "commit": "8fce4d8e3b9e3cf47cc8afeb6077e22ab795d989", "tree": "4930be5756f7a3893717d38f443f6261f11a1f60", "parents": [ "7b61fcda8a640bb87be23f9f09c1f24357b5c6e1" ], "author": { "name": "Christoph Lameter", "email": "clameter@engr.sgi.com", "time": "Thu Mar 09 17:33:54 2006 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Thu Mar 09 19:47:38 2006 -0800" }, "message": "[PATCH] slab: Node rotor for freeing alien caches and remote per cpu pages.\n\nThe cache reaper currently tries to free all alien caches and all remote\nper cpu pages in each pass of cache_reap. For a machines with large number\nof nodes (such as Altix) this may lead to sporadic delays of around ~10ms.\nInterrupts are disabled while reclaiming creating unacceptable delays.\n\nThis patch changes that behavior by adding a per cpu reap_node variable.\nInstead of attempting to free all caches, we free only one alien cache and\nthe per cpu pages from one remote node. That reduces the time spend in\ncache_reap. However, doing so will lengthen the time it takes to\ncompletely drain all remote per cpu pagesets and all alien caches. The\ntime needed will grow with the number of nodes in the system. All caches\nare drained when they overflow their respective capacity. So the drawback\nhere is only that a bit of memory may be wasted for awhile longer.\n\nDetails:\n\n1. Rename drain_remote_pages to drain_node_pages to allow the specification\n of the node to drain of pcp pages.\n\n2. Add additional functions init_reap_node, next_reap_node for NUMA\n that manage a per cpu reap_node counter.\n\n3. Add a reap_alien function that reaps only from the current reap_node.\n\nFor us this seems to be a critical issue. Holdoffs of an average of ~7ms\ncause some HPC benchmarks to slow down significantly. F.e. NAS parallel\nslows down dramatically. NAS parallel has a 12-16 seconds runtime w/o rotor\ncompared to 5.8 secs with the rotor patches. It gets down to 5.05 secs with\nthe additional interrupt holdoff reductions.\n\nSigned-off-by: Christoph Lameter \u003cclameter@sgi.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" }, { "commit": "7b61fcda8a640bb87be23f9f09c1f24357b5c6e1", "tree": "691c42a07df609934cb1cba15cf94b9c04978654", "parents": [ "b707dbe6c52e143a9afea06aa8f84103135ca873" ], "author": { "name": "Roman Zippel", "email": "zippel@linux-m68k.org", "time": "Thu Mar 09 17:33:53 2006 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Thu Mar 09 19:47:38 2006 -0800" }, "message": "[PATCH] m68k: fix cmpxchg compile errors if CONFIG_RMW_INSNS\u003dn\n\nWe require that all archs implement atomic_cmpxchg(), for the generic\nversion of atomic_add_unless().\n\nSigned-off-by: Roman Zippel \u003czippel@linux-m68k.org\u003e\nCc: Geert Uytterhoeven \u003cgeert@linux-m68k.org\u003e\nCc: Adrian Bunk \u003cbunk@stusta.de\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" }, { "commit": "0ef675d491bd65028fa838015ebc6ce8abefab6f", "tree": "8a2074152fceef8384b2276f4e06a05f9efbe969", "parents": [ "eff2c2f6f569267aa52e2431844cec30637d7ade" ], "author": { "name": "Atsushi Nemoto", "email": "anemo@mba.ocn.ne.jp", "time": "Thu Mar 09 17:33:38 2006 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Thu Mar 09 19:47:37 2006 -0800" }, "message": "[PATCH] mtd: 64 bit fixes\n\nFix some bugs in mtd/jffs2 on 64bit platform.\n\nThe MEMGETBADBLOCK/MEMSETBADBLOCK ioctl are not listed in compat_ioctl.h.\n\nAnd some variables in jffs2 are declared as uint32_t but used to hold\nsize_t values.\n\nSigned-off-by: Atsushi Nemoto \u003canemo@mba.ocn.ne.jp\u003e\nCc: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nAcked-by: David Woodhouse \u003cdwmw2@infradead.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" }, { "commit": "fd2a4f1183d1e6802457d70cea067396236ed64b", "tree": "144fa623d9935bd67c63b71078eb35d1109d7dfb", "parents": [ "1443e483e34d2ead97215bd8496b34b0d3fbc2c0" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Wed Mar 08 16:04:32 2006 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Mar 09 18:05:10 2006 +0000" }, "message": "[MIPS] Undefine scr_writew and scr_readw in \u003casm/vga.h\u003e.\n \nThis is gluing the build of cirrusfb but really the mess that would need\ncleaning and fixing is \u003cvideo/vga.h\u003e and \u003clinux/vt_buffer.h\u003e ...\n \nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "0d514f040ac6629311974889d5b96bcf21c6461a", "tree": "af11d40688eabe88f25d21a1af847a761cb3a843", "parents": [ "5ee1af9f519e6dc5a7d7912e87a1aaec857c8818", "1bd79336a426c5e4f3bab142407059ceb12cadf9" ], "author": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Wed Mar 08 18:11:00 2006 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Wed Mar 08 18:11:00 2006 -0800" }, "message": "Merge git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc-merge\n\n* git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc-merge:\n powerpc: Fix various syscall/signal/swapcontext bugs\n [PATCH] powerpc: incorrect rmo_top handling in prom_init\n [PATCH] powerpc: Fix incorrect pud_ERROR() message\n [PATCH] powerpc: Expose SMT and L1 icache snoop userland features\n [PATCH] powerpc: Fix windfarm_pm112 not starting all control loops\n [PATCH] powerpc: Fix old g5 issues with windfarm\n powerpc32: Fix timebase synchronization on 32-bit powermacs\n powerpc: Turn off verbose debug output in powermac platform functions\n powerpc: Fix might-sleep warning in program check exception handler\n" }, { "commit": "f9262c12c0084ddba445a9a42e98994018e51400", "tree": "b54948e654e68c1e5263d955c76bf3a41dfa14da", "parents": [ "979ce809bab37cf438f0db22bfa732d01a84a8c2" ], "author": { "name": "Andi Kleen", "email": "ak@suse.de", "time": "Wed Mar 08 17:57:25 2006 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Wed Mar 08 18:10:31 2006 -0800" }, "message": "[PATCH] i386: port ATI timer fix from x86_64 to i386 II\n\nATI chipsets tend to generate double timer interrupts for the local APIC\ntimer when both the 8254 and the IO-APIC timer pins are enabled. This is\nbecause they route it to both and the result is anded together and the CPU\nends up processing it twice.\n\nThis patch changes check_timer to disable the 8254 routing for interrupt 0.\n\nI think it would be safe on all chipsets actually (i tested it on a couple\nand it worked everywhere) and Windows seems to do it in a similar way, but\nto be conservative this patch only enables this mode on ATI (and adds\noptions to enable/disable too)\n\nPorted over from a similar x86-64 change.\n\nI reused the ACPI earlyquirk infrastructure for the ATI bridge check, but\ntweaked it a bit to work even without ACPI.\n\nInspired by a patch from Chuck Ebbert, but redone.\n\nCc: Chuck Ebbert \u003c76306.1226@compuserve.com\u003e\nCc: \"Brown, Len\" \u003clen.brown@intel.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" }, { "commit": "2ec5e3a867d63d04932e11c6097f63760d9be3fe", "tree": "bb3ea7b72232ec127a104c37cce0f17881ad5d28", "parents": [ "62287fbb54b4af71dc5a4918350f81a4cd467788" ], "author": { "name": "Michael Matz", "email": "matz@suse.de", "time": "Tue Mar 07 21:55:48 2006 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Wed Mar 08 14:15:04 2006 -0800" }, "message": "[PATCH] fix kexec asm\n\nWhile testing kexec and kdump we hit problems where the new kernel would\nfreeze or instantly reboot. The easiest way to trigger it was to kexec a\nkernel compiled for CONFIG_M586 on an athlon cpu. Compiling for CONFIG_MK7\ninstead would work fine.\n\nThe patch fixes a few problems with the kexec inline asm.\n\nSigned-off-by: Chris Mason \u003cmason@suse.com\u003e\nAcked-by: \"Eric W. Biederman\" \u003cebiederm@xmission.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" }, { "commit": "529bf6be5c04f2e869d07bfdb122e9fd98ade714", "tree": "38514bb3941c4ac2a79266e4483663b79efa2f22", "parents": [ "21a1ea9eb40411d4ee29448c53b9e4c0654d6ceb" ], "author": { "name": "Dipankar Sarma", "email": "dipankar@in.ibm.com", "time": "Tue Mar 07 21:55:35 2006 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Wed Mar 08 14:14:01 2006 -0800" }, "message": "[PATCH] fix file counting\n\nI have benchmarked this on an x86_64 NUMA system and see no significant\nperformance difference on kernbench. Tested on both x86_64 and powerpc.\n\nThe way we do file struct accounting is not very suitable for batched\nfreeing. For scalability reasons, file accounting was\nconstructor/destructor based. This meant that nr_files was decremented\nonly when the object was removed from the slab cache. This is susceptible\nto slab fragmentation. With RCU based file structure, consequent batched\nfreeing and a test program like Serge\u0027s, we just speed this up and end up\nwith a very fragmented slab -\n\nllm22:~ # cat /proc/sys/fs/file-nr\n587730 0 758844\n\nAt the same time, I see only a 2000+ objects in filp cache. The following\npatch I fixes this problem.\n\nThis patch changes the file counting by removing the filp_count_lock.\nInstead we use a separate percpu counter, nr_files, for now and all\naccesses to it are through get_nr_files() api. In the sysctl handler for\nnr_files, we populate files_stat.nr_files before returning to user.\n\nCounting files as an when they are created and destroyed (as opposed to\ninside slab) allows us to correctly count open files with RCU.\n\nSigned-off-by: Dipankar Sarma \u003cdipankar@in.ibm.com\u003e\nCc: \"Paul E. McKenney\" \u003cpaulmck@us.ibm.com\u003e\nCc: \"David S. Miller\" \u003cdavem@davemloft.net\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" }, { "commit": "21a1ea9eb40411d4ee29448c53b9e4c0654d6ceb", "tree": "86e4b681858ac562c953bd3ea3c038defd8ec4f4", "parents": [ "e2bab3d92486fb781f4d06f56339264ed1492392" ], "author": { "name": "Dipankar Sarma", "email": "dipankar@in.ibm.com", "time": "Tue Mar 07 21:55:33 2006 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Wed Mar 08 14:14:01 2006 -0800" }, "message": "[PATCH] rcu batch tuning\n\nThis patch adds new tunables for RCU queue and finished batches. There are\ntwo types of controls - number of completed RCU updates invoked in a batch\n(blimit) and monitoring for high rate of incoming RCUs on a cpu (qhimark,\nqlowmark).\n\nBy default, the per-cpu batch limit is set to a small value. If the input\nRCU rate exceeds the high watermark, we do two things - force quiescent\nstate on all cpus and set the batch limit of the CPU to INTMAX. Setting\nbatch limit to INTMAX forces all finished RCUs to be processed in one shot.\n If we have more than INTMAX RCUs queued up, then we have bigger problems\nanyway. Once the incoming queued RCUs fall below the low watermark, the\nbatch limit is set to the default.\n\nSigned-off-by: Dipankar Sarma \u003cdipankar@in.ibm.com\u003e\nCc: \"Paul E. McKenney\" \u003cpaulmck@us.ibm.com\u003e\nCc: \"David S. Miller\" \u003cdavem@davemloft.net\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" }, { "commit": "e2bab3d92486fb781f4d06f56339264ed1492392", "tree": "0295e1ed29794a8e804c4e28a3ea9e72777e533b", "parents": [ "b884e25784f62a1c740d2e4c1ce19cb89644e986" ], "author": { "name": "Andrew Morton", "email": "akpm@osdl.org", "time": "Tue Mar 07 21:55:31 2006 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Wed Mar 08 14:14:01 2006 -0800" }, "message": "[PATCH] percpu_counter_sum()\n\nImplement percpu_counter_sum(). This is a more accurate but slower version of\npercpu_counter_read_positive().\n\nWe need this for Alex\u0027s speedup-ext3_statfs patch and for the nr_file\naccounting fix. Otherwise these things would be too inaccurate on large CPU\ncounts.\n\nCc: Ravikiran G Thirumalai \u003ckiran@scalex86.org\u003e\nCc: Alex Tomas \u003calex@clusterfs.com\u003e\nCc: \"David S. Miller\" \u003cdavem@davemloft.net\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" }, { "commit": "707ced0d718e89b52b13aa55a64653083e792cca", "tree": "3b3276325c3ad5a1de5205971ae6367eb890a426", "parents": [ "81c29a857d3c8d6ea9c4f20d196c36bf0a07c615" ], "author": { "name": "Atsushi Nemoto", "email": "anemo@mba.ocn.ne.jp", "time": "Tue Mar 07 21:55:28 2006 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Wed Mar 08 14:14:00 2006 -0800" }, "message": "[PATCH] __get_unaligned() gcc-4 fix\n\nIf the \u0027ptr\u0027 is a const, this code cause \"assignment of read-only variable\"\nerror on gcc 4.x.\n\nUse __u64 instead of __typeof__(*(ptr)) for temporary variable to get\nrid of errors on gcc 4.x.\n\nSigned-off-by: Atsushi Nemoto \u003canemo@mba.ocn.ne.jp\u003e\nCc: Ralf Baechle \u003cralf@linux-mips.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" }, { "commit": "1c6cc5fd32978ffdc4d0acf8592d3901adefbdad", "tree": "3dd4636af527cef94f91d834573b812476d4e1b4", "parents": [ "a19cbd4bf258840ade3b6ee9e9256006d0644e09" ], "author": { "name": "Mark Fasheh", "email": "mark.fasheh@oracle.com", "time": "Tue Mar 07 21:55:20 2006 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Wed Mar 08 14:14:00 2006 -0800" }, "message": "[PATCH] powerpc: restore eeh_add_device_late() prototype stub\n\nWe fixed this:\n\narch/powerpc/platforms/pseries/eeh.c: In function `eeh_add_device_tree_late\u0027:\narch/powerpc/platforms/pseries/eeh.c:901: warning: implicit declaration of function `eeh_add_device_late\u0027\narch/powerpc/platforms/pseries/eeh.c: At top level:\narch/powerpc/platforms/pseries/eeh.c:918: error: conflicting types for \u0027eeh_add_device_late\u0027\narch/powerpc/platforms/pseries/eeh.c:901: error: previous implicit declaration of \u0027eeh_add_device_late\u0027 was here\nmake[2]: *** [arch/powerpc/platforms/pseries/eeh.o] Error 1\n\nBut we forgot the !CONFIG_EEH stub.\n\nSigned-off-by: Mark Fasheh \u003cmark.fasheh@oracle.com\u003e\nCc: Paul Mackerras \u003cpaulus@samba.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" }, { "commit": "a19cbd4bf258840ade3b6ee9e9256006d0644e09", "tree": "b532fe78c5ecbe5c8e6aca8b7d6f704a24a52129", "parents": [ "432e7c0dfe884b6ab1c32fd3f17c64c31d8fa7e2" ], "author": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Wed Mar 08 14:03:09 2006 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Wed Mar 08 14:03:09 2006 -0800" }, "message": "Mark the pipe file operations static\n\nThey aren\u0027t used (nor even really usable) outside of pipe.c anyway\n\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" }, { "commit": "1bd79336a426c5e4f3bab142407059ceb12cadf9", "tree": "dd8767b0ab3ce310c7df049822100e3838b37a97", "parents": [ "ab1b55e21f6977e420341727e9f4a50691057b5e" ], "author": { "name": "Paul Mackerras", "email": "paulus@samba.org", "time": "Wed Mar 08 13:24:22 2006 +1100" }, "committer": { "name": "Paul Mackerras", "email": "paulus@samba.org", "time": "Wed Mar 08 13:24:22 2006 +1100" }, "message": "powerpc: Fix various syscall/signal/swapcontext bugs\n\nA careful reading of the recent changes to the system call entry/exit\npaths revealed several problems, plus some things that could be\nsimplified and improved:\n\n* 32-bit wasn\u0027t testing the _TIF_NOERROR bit in the syscall fast exit\n path, so it was only doing anything with it once it saw some other\n bit being set. In other words, the noerror behaviour would apply to\n the next system call where we had to reschedule or deliver a signal,\n which is not necessarily the current system call.\n\n* 32-bit wasn\u0027t doing the call to ptrace_notify in the syscall exit\n path when the _TIF_SINGLESTEP bit was set.\n\n* _TIF_RESTOREALL was in both _TIF_USER_WORK_MASK and\n _TIF_PERSYSCALL_MASK, which is odd since _TIF_RESTOREALL is only set\n by system calls. I took it out of _TIF_USER_WORK_MASK.\n\n* On 64-bit, _TIF_RESTOREALL wasn\u0027t causing the non-volatile registers\n to be restored (unless perhaps a signal was delivered or the syscall\n was traced or single-stepped). Thus the non-volatile registers\n weren\u0027t restored on exit from a signal handler. We probably got\n away with it mostly because signal handlers written in C wouldn\u0027t\n alter the non-volatile registers.\n\n* On 32-bit I simplified the code and made it more like 64-bit by\n making the syscall exit path jump to ret_from_except to handle\n preemption and signal delivery.\n\n* 32-bit was calling do_signal unnecessarily when _TIF_RESTOREALL was\n set - but I think because of that 32-bit was actually restoring the\n non-volatile registers on exit from a signal handler.\n\n* I changed the order of enabling interrupts and saving the\n non-volatile registers before calling do_syscall_trace_leave; now we\n enable interrupts first.\n\nSigned-off-by: Paul Mackerras \u003cpaulus@samba.org\u003e\n" }, { "commit": "6a0e243069b09a323255f6e847c87d531961cd96", "tree": "575a7194c86b2b3e1b9db30e283a2f5705e89e99", "parents": [ "d11d9b2dd2c43dd99a491df8a83ae28401db0044" ], "author": { "name": "Catalin Marinas", "email": "catalin.marinas@arm.com", "time": "Tue Mar 07 14:42:27 2006 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Mar 07 14:42:27 2006 +0000" }, "message": "[ARM] 3352/1: DSB required for the completion of a TLB maintenance operation\n\nPatch from Catalin Marinas\n\nChapter B2.7.3 in the latest ARM ARM (with v6 information) states that\nthe completion of a TLB maintenance operation is only guaranteed by\nthe execution of a DSB (Data Syncronization Barrier, formerly Data\nWrite Barrier or Drain Write Buffer).\n\nNote that a DSB is only needed in the flush_tlb_kernel_* functions\nsince the completion is guaranteed by a mode change (i.e. switching\nback to user mode) for the flush_tlb_user_* functions.\n\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "a615fa83959896f8eac76c235953fb164cd1a9b9", "tree": "535fa704cbb621ce8b7776e131678ab3bff92d02", "parents": [ "78679302fe428f4f3dc853a51ee24f306010d874" ], "author": { "name": "Jack Steiner", "email": "steiner@sgi.com", "time": "Mon Mar 06 15:42:50 2006 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Mon Mar 06 18:40:44 2006 -0800" }, "message": "[PATCH] Increase max kmalloc size for very large systems\n\nSystems with extemely large numbers of nodes or cpus need to kmalloc\nstructures larger than is currently supported. This patch increases the\nmaximum supported size for very large systems.\n\nThis patch should have no effect on current systems.\n\n(akpm: why not just use alloc_pages() for sysfs_cpus?)\n\nSigned-off-by: Jack Steiner \u003csteiner@sgi.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" } ], "next": "78679302fe428f4f3dc853a51ee24f306010d874" }