)]}' { "log": [ { "commit": "133e2a3164771454aa326859c2b293687189b553", "tree": "4e21f63be087738d7ffe7526d41e15140fc63ff0", "parents": [ "20bec8ab1458c24bed0d5492ee15d87807fc415a", "8c6db1bbf80123839ec87bdd6cb364aea384623d" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Apr 03 12:13:45 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Apr 03 12:13:45 2009 -0700" }, "message": "Merge branch \u0027next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx\n\n* \u0027next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx:\n dma: Add SoF and EoF debugging to ipu_idmac.c, minor cleanup\n dw_dmac: add cyclic API to DW DMA driver\n dmaengine: Add privatecnt to revert DMA_PRIVATE property\n dmatest: add dma interrupts and callbacks\n dmatest: add xor test\n dmaengine: allow dma support for async_tx to be toggled\n async_tx: provide __async_inline for HAS_DMA\u003dn archs\n dmaengine: kill some unused headers\n dmaengine: initialize tx_list in dma_async_tx_descriptor_init\n dma: i.MX31 IPU DMA robustness improvements\n dma: improve section assignment in i.MX31 IPU DMA driver\n dma: ipu_idmac driver cosmetic clean-up\n dmaengine: fail device registration if channel registration fails\n" }, { "commit": "8c6db1bbf80123839ec87bdd6cb364aea384623d", "tree": "848b8d42f093c03a046bd9ae204b360b5174ea28", "parents": [ "d9de451989a88a2003ca06e524aca4665c0c7f06" ], "author": { "name": "Guennadi Liakhovetski", "email": "lg@denx.de", "time": "Thu Apr 02 11:36:58 2009 +0200" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Apr 02 16:59:10 2009 -0700" }, "message": "dma: Add SoF and EoF debugging to ipu_idmac.c, minor cleanup\n\nAdd Start-of-Frame and End-of-Frame debugging to ipu_idmac.c, in the\nfuture it might also be needed for the actual video processing in\nmx3-camera, at which point, the ISRs will have to be transferred to\nmx3_camera.c, for which ipu_irq_map() and ipu_irq_unmap() functions will\nhave to be exported.\n\nAlso simplify a couple of pointer-dereferences.\n\nSigned-off-by: Guennadi Liakhovetski \u003clg@denx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "ccccce229c633a92c42cd1a40c0738d7b0d12644", "tree": "a954537ae73f2e03c4431b244796cdc255af7a10", "parents": [ "8d47bae004f062630f69f7f83d098424252e232d" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 25 09:13:24 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 25 09:13:24 2009 -0700" }, "message": "dmaengine: initialize tx_list in dma_async_tx_descriptor_init\n\nCentralize this common initialization (and one case where ipu_idmac is\nduplicating -\u003echan initialization).\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "8d47bae004f062630f69f7f83d098424252e232d", "tree": "68379790587eef10926d029ffce74b763175b10c", "parents": [ "234f2df56f5b05756c444edc9879145deddf69f4" ], "author": { "name": "Guennadi Liakhovetski", "email": "g.liakhovetski@gmx.de", "time": "Wed Mar 25 09:13:24 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 25 09:13:24 2009 -0700" }, "message": "dma: i.MX31 IPU DMA robustness improvements\n\nAdd DMA error handling to the ISR, move common code fragments to functions, fix\nscatter-gather element queuing in the ISR, survive channel freeing and\nre-allocation in a quick succession.\n\nSigned-off-by: Guennadi Liakhovetski \u003clg@denx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "234f2df56f5b05756c444edc9879145deddf69f4", "tree": "6946d1561e3243cbb4046652d1d70b647bb7947d", "parents": [ "0149f7d5dc66dcffbb044ba005a5378a5864d2a3" ], "author": { "name": "Guennadi Liakhovetski", "email": "lg@denx.de", "time": "Wed Mar 25 09:13:24 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 25 09:13:24 2009 -0700" }, "message": "dma: improve section assignment in i.MX31 IPU DMA driver\n\nThe i.MX31 IPU DMA driver is a platform driver, but doesn\u0027t need hotplug, so we\ncan use __init and __exit function attributes.\n\nSigned-off-by: Guennadi Liakhovetski \u003clg@denx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "0149f7d5dc66dcffbb044ba005a5378a5864d2a3", "tree": "9ba399f0c71d62d23563d74308a58cc7eb5baf62", "parents": [ "257b17ca030387cb17314cd1851507bdd1b4ddd5" ], "author": { "name": "Guennadi Liakhovetski", "email": "lg@denx.de", "time": "Wed Mar 25 09:13:23 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 25 09:13:23 2009 -0700" }, "message": "dma: ipu_idmac driver cosmetic clean-up\n\nRemove superfluous semicolons, update comments.\n\nSigned-off-by: Guennadi Liakhovetski \u003clg@denx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "9eb2eb8c40ffd30da322648c4415bae0288eb167", "tree": "b2402fd33314e4a78d11d8429c86ffe15cac8d4c", "parents": [ "9a51157bab06ab54d6ee442e34fe9574ff14c8c3" ], "author": { "name": "Sascha Hauer", "email": "s.hauer@pengutronix.de", "time": "Wed Feb 18 11:55:33 2009 +0100" }, "committer": { "name": "Sascha Hauer", "email": "s.hauer@pengutronix.de", "time": "Fri Mar 13 10:34:32 2009 +0100" }, "message": "MX31 clkdev support\n\nThis patch adds clkdev support for i.MX31. This is done in a\nsimilar way done previously for i.MX27\n\nSigned-off-by: Sascha Hauer \u003cs.hauer@pengutronix.de\u003e\n" }, { "commit": "c74ef1f867d18171c8617519ee5fe40b02903934", "tree": "35aacfe4325ecf38bea4ec484444fc4b04d66b6d", "parents": [ "a09b09ae51ace43d28cd9bc1c8bb97986f2b55a6" ], "author": { "name": "Luotao Fu", "email": "l.fu@pengutronix.de", "time": "Thu Feb 26 12:29:20 2009 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 04 16:04:41 2009 -0700" }, "message": "ipu_idmac: fix spinlock type\n\nfix a probably accidently dropped reference operator while calling\nspin_unlock_restore to an ipu lock.\n\nSigned-off-by: Luotao Fu \u003cl.fu@pengutronix.de\u003e\nCc: Guennadi Liakhovetski \u003clg@denx.de\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "5296b56d1b2000b60fb966be161c1f8fb629786b", "tree": "18277748caa9ba43610f76a310d34a3b2155e1a5", "parents": [ "ef560682a97491f62ef538931a4861b57d66c52c" ], "author": { "name": "Guennadi Liakhovetski", "email": "lg@denx.de", "time": "Mon Jan 19 15:36:21 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Jan 19 15:36:21 2009 -0700" }, "message": "i.MX31: Image Processing Unit DMA and IRQ drivers\n\ni.MX3x SoCs contain an Image Processing Unit, consisting of a Control\nModule (CM), Display Interface (DI), Synchronous Display Controller (SDC),\nAsynchronous Display Controller (ADC), Image Converter (IC), Post-Filter\n(PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC).\nCM contains, among other blocks, an Interrupt Generator (IG) and a Clock\nand Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are\nsupported over dmaengine and irq-chip APIs respectively.\n\nIDMAC is a specialised DMA controller, its DMA channels cannot be used for\ngeneral-purpose operations, even though it might be possible to configure\na memory-to-memory channel for memcpy operation. This driver will not work\nwith generic dmaengine clients, clients, wishing to use it must use\nrespective wrapper structures, they also must specify which channels they\nrequire, as channels are hard-wired to specific IPU functions.\n\nAcked-by: Sascha Hauer \u003cs.hauer@pengutronix.de\u003e\nSigned-off-by: Guennadi Liakhovetski \u003clg@denx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" } ] }