)]}'
{
  "log": [
    {
      "commit": "9f8fcf38e8928cccf8c7b32668d146e457f2ccf2",
      "tree": "b29696373225a93876e7b5ec64bcd51bbf75ee98",
      "parents": [
        "679262578ba975037901556b2ddc6b17a77cf671"
      ],
      "author": {
        "name": "Chris Zankel",
        "email": "chris@zankel.net",
        "time": "Fri Jan 18 16:15:29 2008 -0800"
      },
      "committer": {
        "name": "Chris Zankel",
        "email": "chris@zankel.net",
        "time": "Wed Feb 13 17:43:26 2008 -0800"
      },
      "message": "[XTENSA] Fix cache flush macro for D$/I$ aliasing/non-aliasing\n\nFor configurations that have aliasing in the data cache but\nnot in the instruction cache, we don\u0027t need to flush the\ninstruction cache. Thus, we didn\u0027t define the macros to\nflush the instruction cache. Some cache-flush functions,\nhowerver, were using those macros.\n\nSigned-off-by: Chris Zankel \u003cchris@zankel.net\u003e\n"
    },
    {
      "commit": "6656920b0b50beacb6cb64cf55273cbb686e436e",
      "tree": "dab9fdb81821b455a29779de6ca3306dbdf05dbd",
      "parents": [
        "ff6fd469885aafa5ec387babcb6537f3c00d6df0"
      ],
      "author": {
        "name": "Chris Zankel",
        "email": "chris@zankel.net",
        "time": "Wed Aug 22 10:14:51 2007 -0700"
      },
      "committer": {
        "name": "Chris Zankel",
        "email": "chris@zankel.net",
        "time": "Mon Aug 27 13:54:16 2007 -0700"
      },
      "message": "[XTENSA] Add support for cache-aliasing\n\nAdd support for processors that have cache-aliasing issues, such as\nthe Stretch S5000 processor. Cache-aliasing means that the size of\nthe cache (for one way) is larger than the page size, thus, a page\ncan end up in several places in cache depending on the virtual to\nphysical translation. The method used here is to map a user page\ntemporarily through the auto-refill way 0 and of of the DTLB.\nWe probably will want to revisit this issue and use a better\napproach with kmap/kunmap.\n\nSigned-off-by: Chris Zankel \u003cchris@zankel.net\u003e\n"
    },
    {
      "commit": "ec8c0446b6e2b67b5c8813eb517f4bf00efa99a9",
      "tree": "e7c12d7c486c958a5e38888b41cfcd6a558f1aff",
      "parents": [
        "bcd022801ee514e28c32837f0b3ce18c775f1a7b"
      ],
      "author": {
        "name": "Ralf Baechle",
        "email": "ralf@linux-mips.org",
        "time": "Tue Dec 12 17:14:57 2006 +0000"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@woody.osdl.org",
        "time": "Wed Dec 13 09:27:08 2006 -0800"
      },
      "message": "[PATCH] Optimize D-cache alias handling on fork\n\nVirtually index, physically tagged cache architectures can get away\nwithout cache flushing when forking.  This patch adds a new cache\nflushing function flush_cache_dup_mm(struct mm_struct *) which for the\nmoment I\u0027ve implemented to do the same thing on all architectures\nexcept on MIPS where it\u0027s a no-op.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n"
    },
    {
      "commit": "173d6681380aa1d60dfc35ed7178bd7811ba2784",
      "tree": "9d6d4d2c6dd791499ebab558647efb67ac88ae3a",
      "parents": [
        "fd43fe19b830d6cd0eba08a6c6a5f71a6bd9c1b0"
      ],
      "author": {
        "name": "Chris Zankel",
        "email": "czankel@tensilica.com",
        "time": "Sun Dec 10 02:18:48 2006 -0800"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@woody.osdl.org",
        "time": "Sun Dec 10 09:55:39 2006 -0800"
      },
      "message": "[PATCH] xtensa: remove extra header files\n\nThe Xtensa port contained many header files that were never needed.  This\nrather lengthy patch removes all those files.  Unfortunately, there were\nmany dependencies that needed to be updated, so this patch touches quite a\nfew source files.\n\nSigned-off-by: Chris Zankel \u003cchris@zankel.net\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n"
    },
    {
      "commit": "9a8fd5589902153a134111ed7a40f9cca1f83254",
      "tree": "6f7a06de25bdf0b2d94623794c2cbbc66b5a77f6",
      "parents": [
        "3f65ce4d141e435e54c20ed2379d983d362a2cb5"
      ],
      "author": {
        "name": "Chris Zankel",
        "email": "czankel@tensilica.com",
        "time": "Thu Jun 23 22:01:26 2005 -0700"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@ppc970.osdl.org",
        "time": "Fri Jun 24 00:05:22 2005 -0700"
      },
      "message": "[PATCH] xtensa: Architecture support for Tensilica Xtensa Part 6\n\nThe attached patches provides part 6 of an architecture implementation for the\nTensilica Xtensa CPU series.\n\nSigned-off-by: Chris Zankel \u003cchris@zankel.net\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n"
    }
  ]
}