)]}' { "log": [ { "commit": "6faf17f6f1ffc586d16efc2f9fa2083a7785ee74", "tree": "383d4a10cdc0b02bd8bc3a873613a68a06748cd7", "parents": [ "adda766193ea1cf3137484a9521972d080d0b7af" ], "author": { "name": "Chris Wright", "email": "chrisw@sous-sol.org", "time": "Fri Aug 28 13:00:06 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Sun Aug 30 08:37:25 2009 -0700" }, "message": "PCI SR-IOV: correct broken resource alignment calculations\n\nAn SR-IOV capable device includes an SR-IOV PCIe capability which\ndescribes the Virtual Function (VF) BAR requirements. A typical SR-IOV\ndevice can support multiple VFs whose BARs must be in a contiguous region,\neffectively an array of VF BARs. The BAR reports the size requirement\nfor a single VF. We calculate the full range needed by simply multiplying\nthe VF BAR size with the number of possible VFs and create a resource\nspanning the full range.\n\nThis all seems sane enough except it artificially inflates the alignment\nrequirement for the VF BAR. The VF BAR need only be aligned to the size\nof a single BAR not the contiguous range of VF BARs. This can cause us\nto fail to allocate resources for the BAR despite the fact that we\nactually have enough space.\n\nThis patch adds a thin PCI specific layer over the generic\nresource_alignment() function which is aware of the special nature of\nVF BARs and does sorting and allocation based on the smaller alignment\nrequirement.\n\nI recognize that while resource_alignment is generic, it\u0027s basically a\nPCI helper. An alternative to this patch is to add PCI VF BAR specific\ninformation to struct resource. I opted for the extra layer rather than\nadding such PCI specific information to struct resource. This does\nhave the slight downside that we don\u0027t cache the BAR size and re-read\nfor each alignment query (happens a small handful of times during boot\nfor each VF BAR).\n\nSigned-off-by: Chris Wright \u003cchrisw@sous-sol.org\u003e\nCc: Ivan Kokshaysky \u003cink@jurassic.park.msu.ru\u003e\nCc: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\nCc: Matthew Wilcox \u003cmatthew@wil.cx\u003e\nCc: Yu Zhao \u003cyu.zhao@intel.com\u003e\nCc: stable@kernel.org\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "c82f63e411f1b58427c103bd95af2863b1c96dd1", "tree": "4a18447facd22c384c871e312cb3183c01a44b2c", "parents": [ "6c30c53fd5ae6a99a23ad78e90c428d2c8ffb07f" ], "author": { "name": "Alek Du", "email": "alek.du@intel.com", "time": "Sat Aug 08 08:46:19 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Aug 20 09:08:45 2009 -0700" }, "message": "PCI: check saved state before restore\n\nWithout the check, the config space may be filled with zeros. Though\nthe driver should try to avoid call restoring before saving, but the\npci layer also should check this.\n\nAlso removes the existing check in pci_restore_standard_config, since\nit\u0027s superfluous with the new check in restore_state.\n\nAcked-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Alek Du \u003calek.du@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "9b8f013a8361b05edf511f04fe93b36310b73806", "tree": "1c23961d09cc4a47514a501b6f8a6a0f9290a7c2", "parents": [ "9bcf73f48280ef8cd7f2e38e674da47c409b9906", "94f81a47c4a7a2d7a16fcfdd6d81da381732c101" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Aug 10 11:00:37 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Aug 10 11:00:37 2009 -0700" }, "message": "Merge branch \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6\n\n* \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6:\n PCI hotplug: SGI hotplug: do not use hotplug_slot_attr\n PCI hotplug: SGI hotplug: fix build failure\n" }, { "commit": "94f81a47c4a7a2d7a16fcfdd6d81da381732c101", "tree": "79bf6bfaa9f53127bacde65233b47c959fddfbee", "parents": [ "d25f14389a65c7f95512b01415d8d4a8d62855ab" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Mon Jul 27 12:06:46 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Aug 07 10:36:27 2009 -0700" }, "message": "PCI hotplug: SGI hotplug: do not use hotplug_slot_attr\n\nBy the pci slot changes, callbacks of attributes under slot directory\n(/sys/bus/pci/slots) had been changed to get the pointer to struct\npci_slot instead of struct hotplug_slot. So the path_show() that\nassumes the parameter is a pointer to struct hotplug_slot seems\nbroken.\n\nTested-by: Mike Habeck \u003chabeck@sgi.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "d25f14389a65c7f95512b01415d8d4a8d62855ab", "tree": "45565d54d8ab34a7065405c651b17ae4552dc7d0", "parents": [ "90bc1a658a53f8832ee799685703977a450e5af9" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Mon Jul 27 12:05:38 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Aug 07 10:36:26 2009 -0700" }, "message": "PCI hotplug: SGI hotplug: fix build failure\n\nThe commit bd3d99c17039fd05a29587db3f4a180c48da115a (\"PCI: Remove\nuntested Electromechanical Interlock (EMI) support in pciehp.\"), which\nremoves the definition of \"struct hotplug_slot_attr\", broke SGI\nhotplug driver. By this commit, we get the following compile error.\n\ndrivers/pci/hotplug/sgi_hotplug.c:106: error: variable \u0027sn_slot_path_attr\u0027 has initializer but incomplete type\ndrivers/pci/hotplug/sgi_hotplug.c:106: error: unknown field \u0027attr\u0027 specified in initializer\ndrivers/pci/hotplug/sgi_hotplug.c:106: error: extra brace group at end of initializer\ndrivers/pci/hotplug/sgi_hotplug.c:106: error: (near initialization for \u0027sn_slot_path_attr\u0027)\ndrivers/pci/hotplug/sgi_hotplug.c:106: warning: excess elements in struct initializer\ndrivers/pci/hotplug/sgi_hotplug.c:106: warning: (near initialization for \u0027sn_slot_path_attr\u0027)\ndrivers/pci/hotplug/sgi_hotplug.c:106: error: unknown field \u0027show\u0027 specified in initializer\ndrivers/pci/hotplug/sgi_hotplug.c:106: warning: excess elements in struct initializer\ndrivers/pci/hotplug/sgi_hotplug.c:106: warning: (near initialization for \u0027sn_slot_path_attr\u0027)\ndrivers/pci/hotplug/sgi_hotplug.c: In function \u0027sn_hp_destroy\u0027:\ndrivers/pci/hotplug/sgi_hotplug.c:203: error: invalid use of undefined type \u0027struct hotplug_slot_attribute\u0027\ndrivers/pci/hotplug/sgi_hotplug.c: In function \u0027sn_hotplug_slot_register\u0027:\ndrivers/pci/hotplug/sgi_hotplug.c:655: error: invalid use of undefined type \u0027struct hotplug_slot_attribute\u0027\n\nThis patch fixes this regression by adding the definition of struct\nhotplug_slot_attr into sgi_hotplug.c.\n\nTested-by: Mike Habeck \u003chabeck@sgi.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "c5b1525533c484238015c48c78f86d49a1bfb86b", "tree": "631d4b89cc8c42de84230c09a997eef2e734203b", "parents": [ "33041ec049d39a6e0463c7edc7b6f631d24559e3" ], "author": { "name": "Sheng Yang", "email": "sheng@linux.intel.com", "time": "Thu Aug 06 13:31:56 2009 +0800" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Thu Aug 06 11:35:50 2009 +0100" }, "message": "intel-iommu: Fix enabling snooping feature by mistake\n\nTwo defects work together result in KVM device passthrough randomly can\u0027t\nwork:\n1. iommu_snooping is not initialized to zero when vm_iommu_init() called.\nSo it is possible to get a random value.\n2. One line added by commit 2c2e2c38(\"IOMMU Identity Mapping Support\")\nchange the code path, let it bypass domain_update_iommu_cap(), as well as\nmissing the increment of domain iommu reference count.\n\nThe latter is also likely to cause a leak of domains on repeated VMM \nassignment and deassignment.\n\nSigned-off-by: Sheng Yang \u003csheng@linux.intel.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "33041ec049d39a6e0463c7edc7b6f631d24559e3", "tree": "319c613d743f4beae0b00603266f261d6f1dbbae", "parents": [ "f532959b77e5e567c84c914cb7c7b07d2582448b" ], "author": { "name": "Fenghua Yu", "email": "fenghua.yu@intel.com", "time": "Tue Aug 04 15:10:59 2009 -0700" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Wed Aug 05 09:15:48 2009 +0100" }, "message": "intel-iommu: Mask physical address to correct page size in intel_map_single()\n\nThe physical address passed to domain_pfn_mapping() should be rounded \ndown to the start of the MM page, not the VT-d page.\n\nThis issue causes kernel panic on PAGE_SIZE\u003eVTD_PAGE_SIZE platforms e.g. ia64\nplatforms.\n\nSigned-off-by: Fenghua Yu \u003cfenghua.yu@intel.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "f532959b77e5e567c84c914cb7c7b07d2582448b", "tree": "268d0bf9e6660a8fdecc8dcda446745c8464f53a", "parents": [ "90bc1a658a53f8832ee799685703977a450e5af9" ], "author": { "name": "Fenghua Yu", "email": "fenghua.yu@intel.com", "time": "Tue Aug 04 15:09:37 2009 -0700" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Wed Aug 05 08:59:47 2009 +0100" }, "message": "intel-iommu: Correct sglist size calculation.\n\nIn domain_sg_mapping(), use aligned_nrpages() instead of hand-coded\nrounding code for calculating the size of each sg elem. This means that\non IA64 we correctly round up to the MM page size, not just to the VT-d\npage size.\n\nAlso remove the incorrect mm_to_dma_pfn() when intel_map_sg() calls\ndomain_sg_mapping() -- the \u0027size\u0027 variable is in VT-d pages already.\n\nSigned-off-by: Fenghua Yu \u003cfenghua.yu@intel.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "79896cf42f6a96d7e14f2dc3473443d68d74031d", "tree": "bf4aa83fedfbe51d9a2a60d03007ec69de5a0cd2", "parents": [ "0dd8486b5cfe8048e0613334659d9252ecd1b08a" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun Aug 02 14:04:19 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun Aug 02 14:10:18 2009 -0700" }, "message": "Make pci_claim_resource() use request_resource() rather than insert_resource()\n\nThis function has traditionally used \"insert_resource()\", because before\ncommit cebd78a8c5 (\"Fix pci_claim_resource\") it used to just insert the\nresource into whatever root resource tree that was indicated by\n\"pcibios_select_root()\".\n\nSo there Matthew fixed it to actually look up the proper parent\nresource, which means that now it\u0027s actively wrong to then traverse the\nresource tree any more: we already know exactly where the new resource\nshould go.\n\nAnd when we then did commit a76117dfd6 (\"x86: Use pci_claim_resource\"),\nwhich changed the x86 PCI code from the open-coded\n\n\tpr \u003d pci_find_parent_resource(dev, r);\n\tif (!pr || request_resource(pr, r) \u003c 0) {\n\nto using\n\n\tif (pci_claim_resource(dev, idx) \u003c 0) {\n\nthat \"insert_resource()\" now suddenly became a problem, and causes a\nregression covered by\n\n\thttp://bugzilla.kernel.org/show_bug.cgi?id\u003d13891\n\nwhich this fixes.\n\nReported-and-tested-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nCc: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nCc: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nCc: Linux PCI \u003clinux-pci@vger.kernel.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "405f55712dfe464b3240d7816cc4fe4174831be2", "tree": "96c425ea7fa8b31058b8f83a433c5e5265c8ebc7", "parents": [ "f9fabcb58a6d26d6efde842d1703ac7cfa9427b6" ], "author": { "name": "Alexey Dobriyan", "email": "adobriyan@gmail.com", "time": "Sat Jul 11 22:08:37 2009 +0400" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun Jul 12 12:22:34 2009 -0700" }, "message": "headers: smp_lock.h redux\n\n* Remove smp_lock.h from files which don\u0027t need it (including some headers!)\n* Add smp_lock.h to files which do need it\n* Make smp_lock.h include conditional in hardirq.h\n It\u0027s needed only for one kernel_locked() usage which is under CONFIG_PREEMPT\n\n This will make hardirq.h inclusion cheaper for every PREEMPT\u003dn config\n (which includes allmodconfig/allyesconfig, BTW)\n\nSigned-off-by: Alexey Dobriyan \u003cadobriyan@gmail.com\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "4b99d3527041bec1abe9903263a3a1b7d2ba0c4a", "tree": "c28eb8558d7cdc56607f9eff4c8073928b32d202", "parents": [ "0f2f2221b4ad816567394a52643963428fd353cd" ], "author": { "name": "Sheng Yang", "email": "sheng@linux.intel.com", "time": "Wed Jul 08 11:52:52 2009 +0100" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Jul 08 09:35:10 2009 -0700" }, "message": "intel-iommu: Fix intel_iommu_unmap_range() with size 0\n\nAfter some API change, intel_iommu_unmap_range() introduced a assumption that\nparameter size !\u003d 0, otherwise the dma_pte_clean_range() would have a\noverflowed argument. But the user like KVM don\u0027t have this assumption before,\nthen some BUG() triggered.\n\nFix it by ignoring size \u003d 0.\n\nSigned-off-by: Sheng Yang \u003csheng@linux.intel.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "dc53fffc105f68cb08ca872acd51550e89aa2e67", "tree": "5e2ff1ea44eb76e80f8b0bb4902d4292608d1fd1", "parents": [ "f560902c2d39c255bd67c0211f5dd80edb97a712", "46b952a3c3a94afa339bd4961a4f3d1482436599" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Jul 06 14:07:00 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Jul 06 14:07:00 2009 -0700" }, "message": "Merge branch \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6\n\n* \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6:\n PCI: Fix IRQ swizzling for ARI-enabled devices\n ia64/PCI: adjust section annotation for pcibios_setup()\n x86/PCI: get root CRS before scanning children\n x86/PCI: fix boundary checking when using root CRS\n PCI MSI: Fix restoration of MSI/MSI-X mask states in suspend/resume\n PCI MSI: Unmask MSI if setup failed\n PCI MSI: shorten PCI_MSIX_ENTRY_* symbol names\n PCI: make pci_name() take const argument\n PCI: More PATA quirks for not entering D3\n PCI: fix kernel-doc warnings\n PCI: check if bus has a proper bridge device before triggering SBR\n PCI: remove pci_dac_dma_... APIs on mn10300\n PCI ECRC: Remove unnecessary semicolons\n PCI MSI: Return if alloc_msi_entry for MSI-X failed\n" }, { "commit": "3dfc813d94bba2046c6aed216e0fd69ac93a8e03", "tree": "227c2cecfdab3b9bb86508e9d8b6de51e68bfa70", "parents": [ "6941af2810c6fc970b88f7c0d52ba4e286acbee5" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Jul 04 19:11:08 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Jul 04 19:19:10 2009 +0100" }, "message": "intel-iommu: Don\u0027t use identity mapping for PCI devices behind bridges\n\nOur current strategy for pass-through mode is to put all devices into\nthe 1:1 domain at startup (which is before we know what their dma_mask\nwill be), and only _later_ take them out of that domain, if it turns out\nthat they really can\u0027t address all of memory.\n\nHowever, when there are a bunch of PCI devices behind a bridge, they all\nend up with the same source-id on their DMA transactions, and hence in\nthe same IOMMU domain. This means that we _can\u0027t_ easily move them from\nthe 1:1 domain into their own domain at runtime, because there might be DMA\nin-flight from their siblings.\n\nSo we have to adjust our pass-through strategy: For PCI devices not on\nthe root bus, and for the bridges which will take responsibility for\ntheir transactions, we have to start up _out_ of the 1:1 domain, just in\ncase.\n\nThis fixes the BUG() we see when we have 32-bit-capable devices behind a\nPCI-PCI bridge, and use the software identity mapping.\n\nIt does mean that we might end up using \u0027normal\u0027 mapping mode for some\ndevices which could actually live with the faster 1:1 mapping -- but\nthis is only for PCI devices behind bridges, which presumably aren\u0027t the\ndevices for which people are most concerned about performance.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "6941af2810c6fc970b88f7c0d52ba4e286acbee5", "tree": "6b25279e2ab1c2c6062982dcb04bdbddf1eed7d2", "parents": [ "736768325efcbee7b0861d62670d01a54c2d158b" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Jul 04 18:24:27 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Jul 04 19:19:08 2009 +0100" }, "message": "intel-iommu: Use iommu_should_identity_map() at startup time too.\n\nAt boot time, the dma_mask won\u0027t have been set on any devices, so we\nassume that all devices will be 64-bit capable (and thus get a 1:1 map).\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "736768325efcbee7b0861d62670d01a54c2d158b", "tree": "c0f235e88302ebaac1184aa3097c7f9c7cc2f1c8", "parents": [ "62edf5dc4a524e4cb525e6020b955a1ad593d9ba" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Jul 04 14:08:36 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Jul 04 14:12:01 2009 +0100" }, "message": "intel-iommu: No mapping for non-PCI devices\n\nThis should fix kernel.org bug #11821, where the dcdbas driver makes up\na platform device and then uses dma_alloc_coherent() on it, in an\nattempt to get memory \u003c 4GiB.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "62edf5dc4a524e4cb525e6020b955a1ad593d9ba", "tree": "e811a942b7661fc9e97f1611ee75e7f125d51365", "parents": [ "40e4aa34324bff3938a900014254f88943d05e15" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Jul 04 10:59:46 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Jul 04 10:59:46 2009 +0100" }, "message": "intel-iommu: Restore DMAR_BROKEN_GFX_WA option for broken graphics drivers\n\nWe need to give people a little more time to fix the broken drivers.\nRe-introduce this, but tied in properly with the \u0027iommu\u003dpt\u0027 support this\ntime. Change the config option name and make it default to \u0027no\u0027 too.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "40e4aa34324bff3938a900014254f88943d05e15", "tree": "755ff279d80c99a915328b23c91d4c81dee874a7", "parents": [ "1b7bc0a1618b4de1e6f55c6d95b790f4ab6fcd9e" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Jul 04 10:55:41 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Jul 04 10:55:41 2009 +0100" }, "message": "intel-iommu: Add iommu_should_identity_map() function\n\nWe do this twice, and it\u0027s about to get more complicated. This makes the\ncode slightly clearer about what it\u0027s doing, too.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "1b7bc0a1618b4de1e6f55c6d95b790f4ab6fcd9e", "tree": "fa5fbdc5ce15e3726600a23ecfe362d1df5184f8", "parents": [ "1e4c64c46d413de84cc0b786bd6a9b555ba7d111" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Jul 04 10:49:46 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Jul 04 10:49:46 2009 +0100" }, "message": "intel-iommu: Fix reattaching of devices to identity mapping domain\n\nWhen we reattach a device to the si_domain (because it\u0027s been removed\nfrom a VM), we weren\u0027t calling domain_context_mapping() to actually tell\nthe hardware about that.\n\nWe should really put the call to domain_context_mapping() into\ndomain_add_dev_info() -- we never call the latter without also doing the\nformer, and we can keep the error paths simple that way. But that\u0027s a\ncleanup which can wait for 2.6.32 now.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "1e4c64c46d413de84cc0b786bd6a9b555ba7d111", "tree": "5f7c9aa7801c59f88dacdcae3c6722c5d9149ebf", "parents": [ "5a5e02a614e59db7536cd11029e6674adc41b191" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Jul 04 10:40:38 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Jul 04 10:40:44 2009 +0100" }, "message": "intel-iommu: Don\u0027t set identity mapping for bypassed graphics devices\n\nWe should check iommu_dummy() _first_, because that means it\u0027s attached\nto an iommu that we\u0027ve just disabled completely. At the moment, we might\ntry to put the device into the identity mapping domain.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "5a5e02a614e59db7536cd11029e6674adc41b191", "tree": "11f56f4ca2ea02f14e5cdfaae89e034db23edb28", "parents": [ "405d7ca51597645f3be850574d6c10f01be11e8d" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Jul 04 09:35:44 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Jul 04 09:35:52 2009 +0100" }, "message": "intel-iommu: Fix dma vs. mm page confusion with aligned_nrpages()\n\nThe aligned_nrpages() function rounds up to the next VM page, but\nreturns its result as a number of DMA pages.\n\nPurely theoretical except on IA64, which doesn\u0027t boot with VT-d right\nnow anyway.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "405d7ca51597645f3be850574d6c10f01be11e8d", "tree": "9461326f1f8e8c51f3d325702f6e0c6946fb0f67", "parents": [ "7c5371c403abb29f01bc6cff6c5096abdf2dc524", "6a43e574c5af7d9bd084992b1c9c3cdbc3b6c0e9" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Jul 02 16:51:09 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Jul 02 16:51:09 2009 -0700" }, "message": "Merge git://git.infradead.org/iommu-2.6\n\n* git://git.infradead.org/iommu-2.6: (38 commits)\n intel-iommu: Don\u0027t keep freeing page zero in dma_pte_free_pagetable()\n intel-iommu: Introduce first_pte_in_page() to simplify PTE-setting loops\n intel-iommu: Use cmpxchg64_local() for setting PTEs\n intel-iommu: Warn about unmatched unmap requests\n intel-iommu: Kill superfluous mapping_lock\n intel-iommu: Ensure that PTE writes are 64-bit atomic, even on i386\n intel-iommu: Make iommu\u003dpt work on i386 too\n intel-iommu: Performance improvement for dma_pte_free_pagetable()\n intel-iommu: Don\u0027t free too much in dma_pte_free_pagetable()\n intel-iommu: dump mappings but don\u0027t die on pte already set\n intel-iommu: Combine domain_pfn_mapping() and domain_sg_mapping()\n intel-iommu: Introduce domain_sg_mapping() to speed up intel_map_sg()\n intel-iommu: Simplify __intel_alloc_iova()\n intel-iommu: Performance improvement for domain_pfn_mapping()\n intel-iommu: Performance improvement for dma_pte_clear_range()\n intel-iommu: Clean up iommu_domain_identity_map()\n intel-iommu: Remove last use of PHYSICAL_PAGE_MASK, for reserving PCI BARs\n intel-iommu: Make iommu_flush_iotlb_psi() take pfn as argument\n intel-iommu: Change aligned_size() to aligned_nrpages()\n intel-iommu: Clean up intel_map_sg(), remove domain_page_mapping()\n ...\n" }, { "commit": "6a43e574c5af7d9bd084992b1c9c3cdbc3b6c0e9", "tree": "64f32c60749008747d201b7168b33e1181682bf2", "parents": [ "75e6bf9638992dfc0fec9c3ca10444c8e0d6a638" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Thu Jul 02 12:02:34 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Thu Jul 02 12:02:38 2009 +0100" }, "message": "intel-iommu: Don\u0027t keep freeing page zero in dma_pte_free_pagetable()\n\nCheck dma_pte_present() and only free the page if there _is_ one.\nKind of surprising that there was no warning about this.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "75e6bf9638992dfc0fec9c3ca10444c8e0d6a638", "tree": "bdbabd91d77edb3d623292ea97b17d88d053816e", "parents": [ "7766a3fb905f0b078b05f5d6a6be8df4c64b9f51" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Thu Jul 02 11:21:16 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Thu Jul 02 11:27:13 2009 +0100" }, "message": "intel-iommu: Introduce first_pte_in_page() to simplify PTE-setting loops\n\nOn Wed, 2009-07-01 at 16:59 -0700, Linus Torvalds wrote:\n\u003e I also _really_ hate how you do\n\u003e\n\u003e (unsigned long)pte \u003e\u003e VTD_PAGE_SHIFT \u003d\u003d\n\u003e (unsigned long)first_pte \u003e\u003e VTD_PAGE_SHIFT\n\nKill this, in favour of just looking to see if the incremented pte\npointer has \u0027wrapped\u0027 onto the next page. Which means we have to check\nit _after_ incrementing it, not before.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "46b952a3c3a94afa339bd4961a4f3d1482436599", "tree": "f531c057dd8bf6b7ab552774e41a907c99a6577f", "parents": [ "944c54e7fc5ccf961bef2b5449958436b85de459" ], "author": { "name": "Matthew Wilcox", "email": "matthew@wil.cx", "time": "Wed Jul 01 14:24:30 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Jul 01 14:24:30 2009 -0700" }, "message": "PCI: Fix IRQ swizzling for ARI-enabled devices\n\nFor many purposes, including interrupt-swizzling, devices with ARI\nenabled behave as if they have one device (number 0) and 256 functions.\nThis probably hasn\u0027t bitten us in practice because all ARI devices I\u0027ve\nseen are also IOV devices, and IOV devices are required to use MSI.\nThis isn\u0027t guaranteed, and there are legitimate reasons to use ARI\nwithout IOV, and hence potentially use pin-based interrupts.\n\nSigned-off-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "7766a3fb905f0b078b05f5d6a6be8df4c64b9f51", "tree": "57345b5cf47f50cdc3ba09f4746834e77d22817e", "parents": [ "85b98276f2ffa66b25ae6328b00bfadfd74b74e7" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Wed Jul 01 20:27:03 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Wed Jul 01 20:27:03 2009 +0100" }, "message": "intel-iommu: Use cmpxchg64_local() for setting PTEs\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "85b98276f2ffa66b25ae6328b00bfadfd74b74e7", "tree": "17ae570435b8d46e217803b2c536a41f6e8a0c18", "parents": [ "206a73c102fc480ba072a9388bc2142c303113aa" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Wed Jul 01 19:27:53 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Wed Jul 01 19:54:37 2009 +0100" }, "message": "intel-iommu: Warn about unmatched unmap requests\n\nThis would have found the bug in i386 pci_unmap_addr() a long time ago.\nWe shouldn\u0027t just silently return without doing anything.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "206a73c102fc480ba072a9388bc2142c303113aa", "tree": "0b946089436df51a4444ef23069a9037853d5e61", "parents": [ "c85994e4771025ef2a66533eb1a4c6c2217b9cda" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Wed Jul 01 19:30:28 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Wed Jul 01 19:43:37 2009 +0100" }, "message": "intel-iommu: Kill superfluous mapping_lock\n\nSince we\u0027re using cmpxchg64() anyway (because that\u0027s the only way to do\nan atomic 64-bit store on i386), we might as well ditch the extra\nlocking and just use cmpxchg64() to ensure that we don\u0027t add the page\ntwice.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "c85994e4771025ef2a66533eb1a4c6c2217b9cda", "tree": "9f827d5587a5cac2c8a412317e2997b8add67b9a", "parents": [ "3238c0c4d68d9a9022b411a11a4b933fbdb53a14" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Wed Jul 01 19:21:24 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Wed Jul 01 19:21:24 2009 +0100" }, "message": "intel-iommu: Ensure that PTE writes are 64-bit atomic, even on i386\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "a15a519ed6e5e644f5a33c213c00b0c1d3cfe683", "tree": "8b266ba5c56de55adac09a60119a411bd9b4e894", "parents": [ "788d84bba47ea3eb377f7a3ae4fd1ee84b84877b" ], "author": { "name": "David Woodhouse", "email": "dwmw2@infradead.org", "time": "Wed Jul 01 18:49:06 2009 +0100" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Jul 01 11:19:29 2009 -0700" }, "message": "Fix iommu address space allocation\n\nThis fixes kernel.org bug #13584. The IOVA code attempted to optimise\nthe insertion of new ranges into the rbtree, with the unfortunate result\nthat some ranges just didn\u0027t get inserted into the tree at all. Then\nthose ranges would be handed out more than once, and things kind of go\ndownhill from there.\n\nIntroduced after 2.6.25 by ddf02886cbe665d67ca750750196ea5bf524b10b\n(\"PCI: iova RB tree setup tweak\").\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\nCc: mark gross \u003cmgross@linux.intel.com\u003e\nCc: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nCc: stable@kernel.org\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "f3a0a52fff4dbfdea2dccc908d00c038481d888e", "tree": "956261c5e5a00c115eed6741d1ae10fd71d4a411", "parents": [ "3d7b0e4154b4963d6bd39991ec8eaa09caeb3994" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Tue Jun 30 03:40:07 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Tue Jun 30 03:58:15 2009 +0100" }, "message": "intel-iommu: Performance improvement for dma_pte_free_pagetable()\n\nAs with other functions, batch the CPU data cache flushes and don\u0027t keep\nrecalculating PTE addresses.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "3d7b0e4154b4963d6bd39991ec8eaa09caeb3994", "tree": "8c92261cda93b9635e7f84f218f47b2f6f68814e", "parents": [ "1bf20f0dc5629032ddd07617139d9fbca66c1642" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Tue Jun 30 03:38:09 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Tue Jun 30 03:57:38 2009 +0100" }, "message": "intel-iommu: Don\u0027t free too much in dma_pte_free_pagetable()\n\nThe loop condition was wrong -- we should free a PMD only if its\n_entire_ range is within the range we\u0027re intending to clear. The\nearly-termination condition was right, but not the loop.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "1bf20f0dc5629032ddd07617139d9fbca66c1642", "tree": "6911bea8e9333ea7ed36ad4bc7a2c6001000e41d", "parents": [ "9051aa0268dc1c3e42cd79a802b0af1f2bfcadae" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 22:06:43 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Tue Jun 30 03:55:21 2009 +0100" }, "message": "intel-iommu: dump mappings but don\u0027t die on pte already set\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "9051aa0268dc1c3e42cd79a802b0af1f2bfcadae", "tree": "2439a585889486158728d3d16587738112b67a36", "parents": [ "e1605495c716ef4eebdb7606bcd1b593f28e2837" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 12:30:54 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Tue Jun 30 03:53:31 2009 +0100" }, "message": "intel-iommu: Combine domain_pfn_mapping() and domain_sg_mapping()\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "e1605495c716ef4eebdb7606bcd1b593f28e2837", "tree": "de1144b9697f94dda08b3a9434fa97e0dbaab93f", "parents": [ "875764de6f0ddb23d270c29357d5a339232a0488" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 11:17:38 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Tue Jun 30 03:51:30 2009 +0100" }, "message": "intel-iommu: Introduce domain_sg_mapping() to speed up intel_map_sg()\n\nInstead of calling domain_pfn_mapping() repeatedly with single or\nsmall numbers of pages, just pass the sglist in. It can optimise the\nnumber of cache flushes like domain_pfn_mapping() does, and gives a huge\nspeedup for large scatterlists.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "12abb8ba8444f7c9b355bbdd44a6d0839f7a41b6", "tree": "e1dc48f5c1eeb91f4e5146c51f648952aea5c38a", "parents": [ "7ba1930db02fc3118165338ef4e562869f575583" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Wed Jun 24 12:08:09 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Jun 29 12:18:13 2009 -0700" }, "message": "PCI MSI: Fix restoration of MSI/MSI-X mask states in suspend/resume\n\nThere are 2 problems on mask states in suspend/resume.\n\n[1]:\nIt is better to restore the mask states of MSI/MSI-X to initial states\n(MSI is unmasked, MSI-X is masked) when we release the device.\nThe pci_msi_shutdown() does the restoration of mask states for MSI,\nwhile the msi_free_irqs() does it for MSI-X. In other words, in the\n\"disable\" path both of MSI and MSI-X are handled, but in the \"shutdown\"\npath only MSI is handled.\n\nMSI:\n pci_disable_msi()\n \u003d\u003e pci_msi_shutdown()\n [ mask states for MSI restored ]\n \u003d\u003e msi_set_enable(dev, pos, 0);\n \u003d\u003e msi_free_irqs()\n\nMSI-X:\n pci_disable_msix()\n \u003d\u003e pci_msix_shutdown()\n \u003d\u003e msix_set_enable(dev, 0);\n \u003d\u003e msix_free_all_irqs\n \u003d\u003e msi_free_irqs()\n [ mask states for MSI-X restored ]\n\nThis patch moves the masking for MSI-X from msi_free_irqs() to\npci_msix_shutdown().\n\nThis change has some positive side effects:\n - It prevents OS from touching mask states before reading preserved\n bits in the register, which can be happen if msi_free_irqs() is\n called from error path in msix_capability_init().\n - It also prevents touching the register after turning off MSI-X in\n \"disable\" path, which can be a problem on some devices.\n\n[2]:\nWe have cache of the mask state in msi_desc, which is automatically\nupdated when msi/msix_mask_irq() is called. This cached states are\nused for the resume.\n\nBut since what need to be restored in the resume is the states before\nthe shutdown on the suspend, calling msi/msix_mask_irq() from\npci_msi/msix_shutdown() is not appropriate.\n\nThis patch introduces __msi/msix_mask_irq() that do mask as same\nas msi/msix_mask_irq() but does not update cached state, for use\nin pci_msi/msix_shutdown().\n\n[updated: get rid of msi/msix_mask_irq_nocache() (proposed by Matthew Wilcox)]\n\nReviewed-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "7ba1930db02fc3118165338ef4e562869f575583", "tree": "6d889549aa2e15c6762c7cfc87764adfc3d6af4b", "parents": [ "2c21fd4b333e4c780a46edcd6d1e85bfc6cdf371" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Tue Jun 23 17:39:27 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Jun 29 12:16:19 2009 -0700" }, "message": "PCI MSI: Unmask MSI if setup failed\n\nThe initial state of mask register of MSI is unmasked. We set it\nmasked before calling arch_setup_msi_irqs(). If arch_setup_msi_irq()\nfails, it is better to restore the state of the mask register.\n\nReviewed-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "2c21fd4b333e4c780a46edcd6d1e85bfc6cdf371", "tree": "13ceefadd0221f1494f708dcf16b8bfd74955295", "parents": [ "2fc90f6133a87da8177636866557d4cc5f56e661" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Tue Jun 23 17:40:04 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Jun 29 12:15:19 2009 -0700" }, "message": "PCI MSI: shorten PCI_MSIX_ENTRY_* symbol names\n\nThese names are too long! Drop _OFFSET to save some bytes/lines.\n\nReviewed-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "7a661c6f1082693a7e9627e9ad2d1546a9337fdc", "tree": "e6b30aeeb9e42c89861f128c3d5e634675fde512", "parents": [ "503998ca4a295f7da233689850ba4b9d13cf41e7" ], "author": { "name": "Alan Cox", "email": "alan@linux.intel.com", "time": "Wed Jun 24 16:02:27 2009 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Jun 29 12:14:04 2009 -0700" }, "message": "PCI: More PATA quirks for not entering D3\n\nThe ALi loses some state if it goes into D3. Unfortunately even with the\nchipset documents I can\u0027t figure out how to restore some bits of it.\n\nThe VIA one saves/restores apparently fine but the ACPI _GTM methods break\non some platforms if we do this and this causes cable misdetections.\n\nThese are both effectively regressions as historically nothing matched the\ndevices and then decided not to bind to them. Nowdays something is binding\nto all sorts of devices and a result they get dumped into D3.\n\nSigned-off-by: Alan Cox \u003calan@linux.intel.com\u003e\nAcked-by: Jeff Garzik \u003cjeff@garzik.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "503998ca4a295f7da233689850ba4b9d13cf41e7", "tree": "ddd892dac5a3a6fa2fb15f20c137a6d8872806e9", "parents": [ "654b75e044119bf8e7d773bce41ea039281bbfbe" ], "author": { "name": "Randy Dunlap", "email": "randy.dunlap@oracle.com", "time": "Wed Jun 24 09:18:14 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Jun 29 12:13:56 2009 -0700" }, "message": "PCI: fix kernel-doc warnings\n\nAdd documentation for missing parameters in PCI hotplug code.\n\nSigned-off-by: Randy Dunlap \u003crandy.dunlap@oracle.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "654b75e044119bf8e7d773bce41ea039281bbfbe", "tree": "5c749390a41cbbd59617d5dd1cee5160392b5feb", "parents": [ "977badb2f385db14d8ba3fcf02fbd7ead8e63d0f" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Fri Jun 26 14:04:46 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Jun 29 12:13:13 2009 -0700" }, "message": "PCI: check if bus has a proper bridge device before triggering SBR\n\nFor devices attached to the root bus, we can\u0027t trigger Secondary Bus\nReset because there is no bridge device associated with the bus. So\nneed to check bus-\u003eself again NULL first before using it.\n\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "50e5628a4ac465a52f0d4ca6567343be029731a0", "tree": "f5c083d0b80ed3fc782921d7885200cddf04fcc8", "parents": [ "0d07348931daef854aca8c834a89f1a99ba4ff2b" ], "author": { "name": "Joe Perches", "email": "joe@perches.com", "time": "Sun Jun 28 09:26:40 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Jun 29 12:10:35 2009 -0700" }, "message": "PCI ECRC: Remove unnecessary semicolons\n\nAcked-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Joe Perches \u003cjoe@perches.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "0d07348931daef854aca8c834a89f1a99ba4ff2b", "tree": "3cc936fd7f31d00ce9c452ac39ce772f628fccc3", "parents": [ "2bfdd79eaa0043346e773ba5f6cfd811ea31b73d" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Wed Jun 24 12:08:27 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Jun 29 12:10:10 2009 -0700" }, "message": "PCI MSI: Return if alloc_msi_entry for MSI-X failed\n\nIn current code it continues setup even if alloc_msi_entry() for MSI-X\nis failed due to lack of memory. It means arch_setup_msi_irqs() might\nbe called with msi_desc entries less than its argument nvec.\n\nAt least x86\u0027s arch_setup_msi_irqs() uses list_for_each_entry() for\ndev-\u003emsi_list that suspected to have entries same numbers as nvec, and\nit doesn\u0027t check the number of allocated vectors and passed arg nvec.\nTherefore it will result in success of pci_enable_msix(), with less\nvectors allocated than requested.\n\nThis patch fixes the error route to return -ENOMEM, instead of continuing\nthe setup (proposed by Matthew Wilcox).\n\nNote that there is no iounmap in msi_free_irqs() if no msi_disc is\nallocated.\n\nReviewed-by: Matthew Wilcox \u003cmatthew@wil.cx\u003e\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "875764de6f0ddb23d270c29357d5a339232a0488", "tree": "d122b470ffbe6c3651a3ba5b0441b46067f69a3b", "parents": [ "6f6a00e40aa3fdd3b29c30e3ef1fc9690506bc03" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sun Jun 28 21:20:51 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:39:53 2009 +0100" }, "message": "intel-iommu: Simplify __intel_alloc_iova()\n\nThere\u0027s no need for the separate iommu_alloc_iova() function, and\ncertainly not for it to be global. Remove the underscores while we\u0027re at\nit.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "6f6a00e40aa3fdd3b29c30e3ef1fc9690506bc03", "tree": "ba1f28669888141c99c38cfb8d6b2b6034874e25", "parents": [ "310a5ab93cb4ce29367238f682affd9ac352f4d0" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sun Jun 28 20:38:49 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:39:45 2009 +0100" }, "message": "intel-iommu: Performance improvement for domain_pfn_mapping()\n\nAs with dma_pte_clear_range(), don\u0027t keep flushing a single PTE at a\ntime. And also micro-optimise the setting of PTE values rather than\nusing the helper functions to do all the masking.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "310a5ab93cb4ce29367238f682affd9ac352f4d0", "tree": "dc5bb8f208778ebe0aee0054b7af516a36e2b543", "parents": [ "c5395d5c4a82159889cb650de93b591ea51d8c56" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sun Jun 28 18:52:20 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:39:17 2009 +0100" }, "message": "intel-iommu: Performance improvement for dma_pte_clear_range()\n\nIt\u0027s a bit silly to repeatedly call domain_flush_cache() for each PTE\nindividually, as we clear it. Instead, batch them up and flush a whole\nrange at a time. We might as well refrain from recalculating the PTE\naddress from scratch each time round the loop too.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "c5395d5c4a82159889cb650de93b591ea51d8c56", "tree": "e53e62d8b5edf352e17c061f876589a49f73e875", "parents": [ "1a4a45516d7a57de0691352d899d7008f2e090d1" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sun Jun 28 16:35:56 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:39:12 2009 +0100" }, "message": "intel-iommu: Clean up iommu_domain_identity_map()\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "1a4a45516d7a57de0691352d899d7008f2e090d1", "tree": "022ff1b91357207801dc000caab27004324b3c8b", "parents": [ "03d6a2461ab1704c171ce21081c5022378ef7a91" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sun Jun 28 16:00:42 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:39:05 2009 +0100" }, "message": "intel-iommu: Remove last use of PHYSICAL_PAGE_MASK, for reserving PCI BARs\n\nThis is fairly broken anyway -- it doesn\u0027t take hotplug into account.\nWe should probably be checking page_is_ram() instead.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "03d6a2461ab1704c171ce21081c5022378ef7a91", "tree": "fdc259ab75aa524a1013c8606e0ba75cb310274c", "parents": [ "88cb6a7424d9465faf6caaaadff5af0766c93991" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sun Jun 28 15:33:46 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:38:11 2009 +0100" }, "message": "intel-iommu: Make iommu_flush_iotlb_psi() take pfn as argument\n\nMost of its callers are having to shift for themselves anyway, so we might\nas well do it in iommu_flush_iotlb_psi().\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "88cb6a7424d9465faf6caaaadff5af0766c93991", "tree": "5c50bec9d13911ea295349de24db46ec732c67c7", "parents": [ "b536d24d212c994a7d98469ea3a8891573d45fd4" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sun Jun 28 15:03:06 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:38:04 2009 +0100" }, "message": "intel-iommu: Change aligned_size() to aligned_nrpages()\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "b536d24d212c994a7d98469ea3a8891573d45fd4", "tree": "137751d6969f757e70548bc5ae5abee55e7c6559", "parents": [ "ad05122162b67f64d5a1c6d35e001f7a88619b88" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sun Jun 28 14:49:31 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:35:06 2009 +0100" }, "message": "intel-iommu: Clean up intel_map_sg(), remove domain_page_mapping()\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "ad05122162b67f64d5a1c6d35e001f7a88619b88", "tree": "9c406fd2e65fc6f0f0eb931cc951a07177035f4e", "parents": [ "0ab36de274ab094c3992b50c9c48c5c89072ec94" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sun Jun 28 14:22:28 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:35:00 2009 +0100" }, "message": "intel-iommu: Use domain_pfn_mapping() in intel_iommu_map_range()\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "0ab36de274ab094c3992b50c9c48c5c89072ec94", "tree": "62f7e197958fca2d846bb8821d22fc97e9675231", "parents": [ "61df744314079e8cb8cdec75f517cf0e704e41ef" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sun Jun 28 14:01:43 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:34:24 2009 +0100" }, "message": "intel-iommu: Use domain_pfn_mapping() in __intel_map_single()\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "61df744314079e8cb8cdec75f517cf0e704e41ef", "tree": "55fd23fd2b1e909e203876d3d3b0d2eec879c675", "parents": [ "1c5a46ed49e37f56f8aa9000bb1c2ac59670c372" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sun Jun 28 11:55:58 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:33:59 2009 +0100" }, "message": "intel-iommu: Introduce domain_pfn_mapping()\n\n... and use it in the trivial cases; the other callers want individual\n(and bisectable) attention, since I screwed them up the first time...\n\nMake the BUG_ON() happen on too-large virtual address rather than\nphysical address, too. That\u0027s the one we care about.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "1c5a46ed49e37f56f8aa9000bb1c2ac59670c372", "tree": "70d61d1fdb94824e000a12a7ea086281074823bc", "parents": [ "b026fd28ea23af24a3eea6e5be3f3d0193a8e87d" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sun Jun 28 10:53:37 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:33:11 2009 +0100" }, "message": "intel-iommu: Clean up address handling in domain_page_mapping()\n\nNo more masking and alignment; just use pfns.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "b026fd28ea23af24a3eea6e5be3f3d0193a8e87d", "tree": "557ccb29c1213f39951651fef68d7e7910d9893b", "parents": [ "163cc52ccd2cc5c5ae4e1c886f6fde8547feed2a" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sun Jun 28 10:37:25 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:32:26 2009 +0100" }, "message": "intel-iommu: Change addr_to_dma_pte() to pfn_to_dma_pte()\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "163cc52ccd2cc5c5ae4e1c886f6fde8547feed2a", "tree": "0371640770d8c575779b29cfaea2b27e922ce724", "parents": [ "d794dc9b302c2781c571c10dedb8094e223d31b8" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sun Jun 28 00:51:17 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:31:12 2009 +0100" }, "message": "intel-iommu: Clean up intel_iommu_unmap_range()\n\nUse unaligned address for domain-\u003emax_addr. That algorithm isn\u0027t ideal\nanyway -- we should probably just look at the last iova in the tree.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "d794dc9b302c2781c571c10dedb8094e223d31b8", "tree": "60a410f5b37779db3efd946ec6a32aa7bf50e651", "parents": [ "6660c63a79a639b86e3a709e25a8c4fc3ab24770" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sun Jun 28 00:27:49 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:30:45 2009 +0100" }, "message": "intel-iommu: Make dma_pte_free_pagetable() take pfns as argument\n\nWith some cleanup of intel_unmap_page(), intel_unmap_sg() and\nvm_domain_exit() to no longer play with 64-bit addresses.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "6660c63a79a639b86e3a709e25a8c4fc3ab24770", "tree": "8e9b0f30973bb33f588f9d80dee91bc798ff4127", "parents": [ "595badf5d65d50300319e6178e6df005ea501f70" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Jun 27 22:41:00 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:30:35 2009 +0100" }, "message": "intel-iommu: Make dma_pte_free_pagetable() use pfns\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "595badf5d65d50300319e6178e6df005ea501f70", "tree": "00bb65e865ab8aface12c57634a152b1440364ee", "parents": [ "04b18e65dd5a3e544f07f4bcfa8fb52704a1833b" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Jun 27 22:09:11 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:28:10 2009 +0100" }, "message": "intel-iommu: Make dma_pte_clear_range() take pfns as argument\n\nNoting that this is now an _inclusive_ range.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "04b18e65dd5a3e544f07f4bcfa8fb52704a1833b", "tree": "51b6c12b122a1c186c3f8fea3f723c602a4465d7", "parents": [ "66eae8469e4e4ba6f4ca7ef82103c78f6d645583" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Jun 27 19:15:01 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 13:26:36 2009 +0100" }, "message": "intel-iommu: Make dma_pte_clear_range() use pfns\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "66eae8469e4e4ba6f4ca7ef82103c78f6d645583", "tree": "adb12962ecead5e169265aaefdf7c4472609a504", "parents": [ "a75f7cf94f01717c5103138319b96752ee2a2be9" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Jun 27 19:00:32 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 12:38:42 2009 +0100" }, "message": "intel-iommu: Don\u0027t just mask out too-big physical addresses; BUG() instead\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "a75f7cf94f01717c5103138319b96752ee2a2be9", "tree": "b268deef1584bbc51a19b550d54339ebb276c1d4", "parents": [ "90dcfb5eb2fd427b16135a14f176a6902750b6b4" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Jun 27 17:44:39 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 12:38:40 2009 +0100" }, "message": "intel-iommu: Make dma_pte_clear_one() take pfn not address\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "90dcfb5eb2fd427b16135a14f176a6902750b6b4", "tree": "2951f2a7e9dab02127005937c92dfa8dc0e03e07", "parents": [ "77dfa56c94d2855a25ff552b74980a5538e129f8" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Jun 27 17:14:59 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 12:38:38 2009 +0100" }, "message": "intel-iommu: Change dma_addr_level_pte() to dma_pfn_level_pte()\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "77dfa56c94d2855a25ff552b74980a5538e129f8", "tree": "be0d357d3b62e7b72ad40dcb66512bc6f29221a7", "parents": [ "dd4e831960e4f0214480fa96a53ca9bb7dd04927" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Jun 27 16:40:08 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 12:38:32 2009 +0100" }, "message": "intel-iommu: Change address_level_offset() to pfn_level_offset()\n\nWe\u0027re shifting the inputs for now, but that\u0027ll change...\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "dd4e831960e4f0214480fa96a53ca9bb7dd04927", "tree": "740ef8b4c65d9314d337b618900cf22fdfcbdb17", "parents": [ "c7ab48d2acaf959e4d59c3f55d12fdb7ca9afd7c" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Jun 27 16:21:20 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 12:38:11 2009 +0100" }, "message": "intel-iommu: Change dma_set_pte_addr() to dma_set_pte_pfn()\n\nAdd some helpers for converting between VT-d and normal system pfns,\nsince system pages can be larger than VT-d pages.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "c7ab48d2acaf959e4d59c3f55d12fdb7ca9afd7c", "tree": "5474dadf86c95ddf3b347000f5c114f154e7a0ab", "parents": [ "b213203e475212a69ad6fedfb73464087e317148" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Fri Jun 26 19:10:36 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 12:37:44 2009 +0100" }, "message": "intel-iommu: Clean up identity mapping code, remove CONFIG_DMAR_GFX_WA\n\nThere\u0027s no need for the GFX workaround now we have \u0027iommu\u003dpt\u0027 for the\ncases where people really care about performance. There\u0027s no need to\nhave a special case for just one type of device.\n\nThis also speeds up the iommu\u003dpt path and reduces memory usage by\nsetting up the si_domain _once_ and then using it for all devices,\nrather than giving each device its own private page tables.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "b213203e475212a69ad6fedfb73464087e317148", "tree": "f5969a292e97f50f0bd0d4b7f775641464c3add2", "parents": [ "bf92df30df909710c498d05620e2df1be1ef779b" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Fri Jun 26 18:50:28 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 12:37:42 2009 +0100" }, "message": "intel-iommu: Create new iommu_domain_identity_map() function\n\nWe\u0027ll want to do this to a _domain_ (the si_domain) rather than a PCI device.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "bf92df30df909710c498d05620e2df1be1ef779b", "tree": "9d1e330524fac88a95b6787e0b754e02e62df039", "parents": [ "a679128d30d0303bbf5cac839c8f6f45793ea775" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Mon Jun 29 11:31:45 2009 +0800" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Jun 29 12:34:11 2009 +0100" }, "message": "intel-iommu: Only avoid flushing device IOTLB for domain ID 0 in caching mode\n\nIn caching mode, domain ID 0 is reserved for non-present to present\nmapping flush. Device IOTLB doesn\u0027t need to be flushed in this case.\n\nPreviously we were avoiding the flush for domain zero, even if the IOMMU \nwasn\u0027t in caching mode and domain zero wasn\u0027t special.\n\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "7e25a2422987a37729706b18583d177966919d2a", "tree": "dd7ec2e5912b81d73998efa5ab29089ffc50eef1", "parents": [ "28d0325ce6e0a52f53d8af687e6427fee59004d3" ], "author": { "name": "Chris Wright", "email": "chrisw@redhat.com", "time": "Thu Jun 25 18:52:05 2009 -0700" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Fri Jun 26 11:26:27 2009 +0100" }, "message": "intel-iommu: fix Identity Mapping to be arch independent\n\nDrop the e820 scanning and use existing function for finding valid\nRAM regions to add to 1:1 mapping.\n\nSigned-off-by: Chris Wright \u003cchrisw@redhat.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "0c26d7cc31cd81a82be3b9d7687217d49fe9c47e", "tree": "1a20b590a5d71e588af7034b21f4779e6a8bd949", "parents": [ "936940a9c7e3d99b25859bf1ff140d8c2480183a", "21ab01e2fcbfcc0d1faba2b7336b3c0f7f3c1ac8" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Jun 24 10:17:07 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Jun 24 10:17:07 2009 -0700" }, "message": "Merge branch \u0027release\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-acpi-2.6\n\n* \u0027release\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-acpi-2.6: (72 commits)\n asus-laptop: remove EXPERIMENTAL dependency\n asus-laptop: use pr_fmt and pr_\u003clevel\u003e\n eeepc-laptop: cpufv updates\n eeepc-laptop: sync eeepc-laptop with asus_acpi\n asus_acpi: Deprecate in favor of asus-laptop\n acpi4asus: update MAINTAINER and KConfig links\n asus-laptop: platform dev as parent for led and backlight\n eeepc-laptop: enable camera by default\n ACPI: Rename ACPI processor device bus ID\n acerhdf: Acer Aspire One fan control\n ACPI: video: DMI workaround broken Acer 7720 BIOS enabling display brightness\n ACPI: run ACPI device hot removal in kacpi_hotplug_wq\n ACPI: Add the reference count to avoid unloading ACPI video bus twice\n ACPI: DMI to disable Vista compatibility on some Sony laptops\n ACPI: fix a deadlock in hotplug case\n Show the physical device node of backlight class device.\n ACPI: pdc init related memory leak with physical CPU hotplug\n ACPI: pci_root: remove unused dev/fn information\n ACPI: pci_root: simplify list traversals\n ACPI: pci_root: use driver data rather than list lookup\n ...\n" }, { "commit": "fbe8cddd2d85979d273d7937a2b8a47498694d91", "tree": "2ae3253bfd89337583d36afd783145786ffa531e", "parents": [ "4e8a2372f9255a1464ef488ed925455f53fbdaa1", "e86435eb91b2bff114c5a02e46e16ce21b647ebe", "7fe2a6c275a5bcec52fb3ef643daaf8265b7af0d", "0705495d9010048e293013d9d129cf723363a0a8", "35a7c64fbc77bab4ca8ae477e8ab278ccd679ce2", "152a4e630f7ffdd7ff64427c4ba488dc0bce76af", "86e437f077c68112edcb6854ec036ed7e3f9a7f3", "c8d72a5e76988140bfdfd8722f2228d94e7fa10f", "7a04b8491a077471a34938b8ca060c37220953be", "ee1ca48fae7e575d5e399d4fdcfe0afc1212a64c", "9eccbc2f67efd0d19c47f40182abf2965c287add", "7e275cc4e8e20f82740bf40ae2f5695e9e35ff09", "7b768f07dce463a054c9dd84862d15ccc3d2b712", "8cb24c8fd70ea8431744de1ca0ca34ab45fbbdaa", "113b3a2b901573961509e81a28e9546cf9defef0", "d73772474f6ebbacbe820c31c0fa1cffa7160246", "056c308d3e4859334b519033d62ef050f0e0e261", "871043bc463e7d191e7b5b00436a8852921dd833" ], "author": { "name": "Len Brown", "email": "len.brown@intel.com", "time": "Wed Jun 24 01:19:50 2009 -0400" }, "committer": { "name": "Len Brown", "email": "len.brown@intel.com", "time": "Wed Jun 24 01:19:50 2009 -0400" }, "message": "Merge branches \u0027acerhdf\u0027, \u0027acpi-pci-bind\u0027, \u0027bjorn-pci-root\u0027, \u0027bugzilla-12904\u0027, \u0027bugzilla-13121\u0027, \u0027bugzilla-13396\u0027, \u0027bugzilla-13533\u0027, \u0027bugzilla-13612\u0027, \u0027c3_lock\u0027, \u0027hid-cleanups\u0027, \u0027misc-2.6.31\u0027, \u0027pdc-leak-fix\u0027, \u0027pnpacpi\u0027, \u0027power_nocheck\u0027, \u0027thinkpad_acpi\u0027, \u0027video\u0027 and \u0027wmi\u0027 into release\n" }, { "commit": "f007e99c8e2e322b8331aba72414715119a2920d", "tree": "616bfcdda74341dc8b5d9ea1013bb7506407a961", "parents": [ "c4658b4e777bebf69884f4884a9bfb2f84dd71d9" ], "author": { "name": "Weidong Han", "email": "weidong.han@intel.com", "time": "Sat May 23 00:41:15 2009 +0800" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Tue Jun 23 22:09:17 2009 +0100" }, "message": "Intel-IOMMU, intr-remap: source-id checking\n\nTo support domain-isolation usages, the platform hardware must be\ncapable of uniquely identifying the requestor (source-id) for each\ninterrupt message. Without source-id checking for interrupt remapping\n, a rouge guest/VM with assigned devices can launch interrupt attacks\nto bring down anothe guest/VM or the VMM itself.\n\nThis patch adds source-id checking for interrupt remapping, and then\nreally isolates interrupts for guests/VMs with assigned devices.\n\nBecause PCI subsystem is not initialized yet when set up IOAPIC\nentries, use read_pci_config_byte to access PCI config space directly.\n\nSigned-off-by: Weidong Han \u003cweidong.han@intel.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "c4658b4e777bebf69884f4884a9bfb2f84dd71d9", "tree": "c38cf0924b01e42a936b56d9f5c3d254822d3471", "parents": [ "2c2e2c389d03bb16b8cdf9db3ac615385fac100f" ], "author": { "name": "Weidong Han", "email": "weidong.han@intel.com", "time": "Sat May 23 00:41:14 2009 +0800" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Tue Jun 23 22:09:15 2009 +0100" }, "message": "Intel-IOMMU, intr-remap: set the whole 128bits of irte when modify/free it\n\nInterrupt remapping table entry is 128bits. Currently, it only sets low\n64bits of irte in modify_irte and free_irte. This ignores high 64bits\nsetting of irte, that means source-id setting will be ignored. This patch\nsets the whole 128bits of irte when modify/free it. Following source-id\nchecking patch depends on this.\n\nSigned-off-by: Weidong Han \u003cweidong.han@intel.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "2c2e2c389d03bb16b8cdf9db3ac615385fac100f", "tree": "19af024e80adbbd1536aae0fa0c23ed4249834fe", "parents": [ "687d680985b1438360a9ba470ece8b57cd205c3b" ], "author": { "name": "Fenghua Yu", "email": "fenghua.yu@intel.com", "time": "Fri Jun 19 13:47:29 2009 -0700" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Tue Jun 23 22:07:54 2009 +0100" }, "message": "IOMMU Identity Mapping Support (drivers/pci/intel_iommu.c)\n\nIdentity mapping for IOMMU defines a single domain to 1:1 map all PCI\ndevices to all usable memory.\n\nThis reduces map/unmap overhead in DMA API\u0027s and improve IOMMU\nperformance. On 10Gb network cards, Netperf shows no performance\ndegradation compared to non-IOMMU performance.\n\nThis method may lose some of DMA remapping benefits like isolation.\n\nThe patch sets up identity mapping for all PCI devices to all usable\nmemory. In the DMA API, there is no overhead to maintain page tables,\ninvalidate iotlb, flush cache etc.\n\n32 bit DMA devices don\u0027t use identity mapping domain, in order to access\nmemory beyond 4GiB.\n\nWhen kernel option iommu\u003dpt, pass through is first tried. If pass\nthrough succeeds, IOMMU goes to pass through. If pass through is not\nsupported in hw or fail for whatever reason, IOMMU goes to identity\nmapping.\n\nSigned-off-by: Fenghua Yu \u003cfenghua.yu@intel.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "687d680985b1438360a9ba470ece8b57cd205c3b", "tree": "ae253608531e5c3e823600974c610e722e7de759", "parents": [ "1053414068bad659479e6efa62a67403b8b1ec0a", "008fe148cb0fb51d266baabe2c09997b21cf90c6" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Jun 22 21:38:22 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Jun 22 21:38:22 2009 -0700" }, "message": "Merge git://git.infradead.org/~dwmw2/iommu-2.6.31\n\n* git://git.infradead.org/~dwmw2/iommu-2.6.31:\n intel-iommu: Fix one last ia64 build problem in Pass Through Support\n VT-d: support the device IOTLB\n VT-d: cleanup iommu_flush_iotlb_psi and flush_unmaps\n VT-d: add device IOTLB invalidation support\n VT-d: parse ATSR in DMA Remapping Reporting Structure\n PCI: handle Virtual Function ATS enabling\n PCI: support the ATS capability\n intel-iommu: dmar_set_interrupt return error value\n intel-iommu: Tidy up iommu-\u003egcmd handling\n intel-iommu: Fix tiny theoretical race in write-buffer flush.\n intel-iommu: Clean up handling of \"caching mode\" vs. IOTLB flushing.\n intel-iommu: Clean up handling of \"caching mode\" vs. context flushing.\n VT-d: fix invalid domain id for KVM context flush\n Fix !CONFIG_DMAR build failure introduced by Intel IOMMU Pass Through Support\n Intel IOMMU Pass Through Support\n\nFix up trivial conflicts in drivers/pci/{intel-iommu.c,intr_remapping.c}\n" }, { "commit": "59ef7a83f1127038a433464597df02e2dc9540e7", "tree": "725d262fc2e68eb9c592d76265f878cec73f8f2d", "parents": [ "5165aece0efac6574fc3e32b6f1c2a964820d1c6", "2af5066f664cb011cf17d2e4414491fe24597e07" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Jun 22 11:59:51 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Jun 22 11:59:51 2009 -0700" }, "message": "Merge branch \u0027linux-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6\n\n* \u0027linux-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: (74 commits)\n PCI: make msi_free_irqs() to use msix_mask_irq() instead of open coded write\n PCI: Fix the NIU MSI-X problem in a better way\n PCI ASPM: remove get_root_port_link\n PCI ASPM: cleanup pcie_aspm_sanity_check\n PCI ASPM: remove has_switch field\n PCI ASPM: cleanup calc_Lx_latency\n PCI ASPM: cleanup pcie_aspm_get_cap_device\n PCI ASPM: cleanup clkpm checks\n PCI ASPM: cleanup __pcie_aspm_check_state_one\n PCI ASPM: cleanup initialization\n PCI ASPM: cleanup change input argument of aspm functions\n PCI ASPM: cleanup misc in struct pcie_link_state\n PCI ASPM: cleanup clkpm state in struct pcie_link_state\n PCI ASPM: cleanup latency field in struct pcie_link_state\n PCI ASPM: cleanup aspm state field in struct pcie_link_state\n PCI ASPM: fix typo in struct pcie_link_state\n PCI: drivers/pci/slot.c should depend on CONFIG_SYSFS\n PCI: remove redundant __msi_set_enable()\n PCI PM: consistently use type bool for wake enable variable\n x86/ACPI: Correct maximum allowed _CRS returned resources and warn if exceeded\n ...\n" }, { "commit": "2af5066f664cb011cf17d2e4414491fe24597e07", "tree": "fe9f787a3eac10cfef1bbc7e18ee7800c281f773", "parents": [ "f598282f5145036312d90875d0ed5c14b49fd8a7" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Thu Jun 18 19:20:26 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jun 19 15:11:45 2009 -0700" }, "message": "PCI: make msi_free_irqs() to use msix_mask_irq() instead of open coded write\n\nUse msix_mask_irq() instead of direct use of writel, so as not to clear\npreserved bits in the Vector Control register [31:1].\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f598282f5145036312d90875d0ed5c14b49fd8a7", "tree": "3cb76a5a2cbd161ce03007370f5e38c133efe21d", "parents": [ "5c92ffb1ecc7f13267cdef5dda8a838937912c93" ], "author": { "name": "Matthew Wilcox", "email": "willy@linux.intel.com", "time": "Thu Jun 18 19:15:59 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jun 19 15:11:39 2009 -0700" }, "message": "PCI: Fix the NIU MSI-X problem in a better way\n\nThe previous MSI-X fix (8d181018532dd709ec1f789e374cda92d7b01ce1) had\nthree bugs. First, it didn\u0027t move the write that disabled the vector.\nThis led to writing garbage to the MSI-X vector (spotted by Michael\nEllerman). It didn\u0027t fix the PCI resume case, and it had a race window\nwhere the device could generate an interrupt before the MSI-X registers\nwere programmed (leading to a DMA to random addresses).\n\nFortunately, the MSI-X capability has a bit to mask all the vectors.\nBy setting this bit instead of clearing the enable bit, we can ensure\nthe device will not generate spurious interrupts. Since the capability\nis now enabled, the NIU device will not have a problem with the reads\nand writes to the MSI-X registers being in the original order in the code.\n\nSigned-off-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nReviewed-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "5c92ffb1ecc7f13267cdef5dda8a838937912c93", "tree": "50a5ffeea038549e1195d80f10b183f55c45e4ef", "parents": [ "3647584d9ef35c9ec4abefdbea29959c26c54f13" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:23:57 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 14:02:23 2009 -0700" }, "message": "PCI ASPM: remove get_root_port_link\n\nBy having a pointer to the root port link, we can remove loops in\nget_root_port_link() to search the root port link.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "3647584d9ef35c9ec4abefdbea29959c26c54f13", "tree": "107167bb680a15c1581dfb3f05737cfe514c6c29", "parents": [ "efdf8288819df67d608a186f9d17a7d4051f3c1f" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:23:09 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 14:02:22 2009 -0700" }, "message": "PCI ASPM: cleanup pcie_aspm_sanity_check\n\nMinor cleanup for pcie_aspm_sanity_check().\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "efdf8288819df67d608a186f9d17a7d4051f3c1f", "tree": "3d781654102cafc726bbc1894070260364eac3af", "parents": [ "5e0eaa7d3679c3ef8618803bc9311270e5816641" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:22:26 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 14:02:22 2009 -0700" }, "message": "PCI ASPM: remove has_switch field\n\nWe don\u0027t need the \u0027has_switch\u0027 field in the struct pcie_link_state.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "5e0eaa7d3679c3ef8618803bc9311270e5816641", "tree": "895538798c0fd42aa499ac78ed0cb40a8fec27fa", "parents": [ "7ab709910323a8af20722c066267516b3e7680a2" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:21:48 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 14:02:21 2009 -0700" }, "message": "PCI ASPM: cleanup calc_Lx_latency\n\nCleanup for calc_L0S_latency() and calc_L1_latency().\n\n - Separate exit latency and acceptable latency calculation.\n - Some minor cleanups.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "7ab709910323a8af20722c066267516b3e7680a2", "tree": "d35af8b1894b3813ef1fc7a6aea13fa9dbda78b9", "parents": [ "430842e29d396928989c0a45e05025e988004d79" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:20:48 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 14:02:20 2009 -0700" }, "message": "PCI ASPM: cleanup pcie_aspm_get_cap_device\n\nMinor cleanup for pcie_aspm_get_cap_device().\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "430842e29d396928989c0a45e05025e988004d79", "tree": "ecdfed05c82324784fabf42f5f008efa1d3c6dc5", "parents": [ "f7ea3d7fc03753b08e267fece19c56383e6b856f" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:20:10 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 14:02:19 2009 -0700" }, "message": "PCI ASPM: cleanup clkpm checks\n\nIn the current ASPM implementation, callers of pcie_set_clock_pm() check\nClock PM capability of the link or current Clock PM state of the link.\nThis check should be done in pcie_set_clock_pm() itself.\n\nThis patch moves those checks into pcie_set_clock_pm(). It also\nintroduces pcie_set_clkpm_nocheck() that is equivalent to old\npcie_set_clock_pm(), for the caller who wants to change Clocl PM state\nregardless of the Clock PM capability or current Clock PM state. In\naddition, this patch changes the function name from\npcie_set_clock_pm() to pcie_set_clkpm() for consistency.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f7ea3d7fc03753b08e267fece19c56383e6b856f", "tree": "2ff13c579b8e7dedf3a088b93982e25a3647bdf1", "parents": [ "8d349ace9a5c2a8404bcf4a371fe170480ffbebb" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:19:00 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 14:02:18 2009 -0700" }, "message": "PCI ASPM: cleanup __pcie_aspm_check_state_one\n\nClean up and simplify __pcie_aspm_check_state_one().\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "8d349ace9a5c2a8404bcf4a371fe170480ffbebb", "tree": "6495378f6b3255752cd04af22e653ece36c7d8b7", "parents": [ "5aa63583cbec27482c6f1d761a0509f59b7969a8" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:18:22 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 14:02:15 2009 -0700" }, "message": "PCI ASPM: cleanup initialization\n\nClean up ASPM initialization by refactoring some functionality, renaming\nfunctions, and moving things around.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "5aa63583cbec27482c6f1d761a0509f59b7969a8", "tree": "a989edcd7e85199aee66eff2f087dfd6d94176bb", "parents": [ "5cde89d80172a393e49077d2450545b97ac8d972" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:17:44 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 13:57:26 2009 -0700" }, "message": "PCI ASPM: cleanup change input argument of aspm functions\n\nIn the current ASPM implementation, there are many functions that\ntake a pointer to struct pci_dev corresponding to the upstream component\nof the link as a parameter. But, since those functions handle PCI\nexpress link state, a pointer to struct pcie_link_state is more\nsuitable than a pointer to struct pci_dev. Changing a parameter to a\npointer to struct pcie_link_state makes ASPM code much simpler and\neasier to read. This patch also contains some minor cleanups. This patch\ndoesn\u0027t have any functional change.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "5cde89d80172a393e49077d2450545b97ac8d972", "tree": "86d5810ca54f0be2079c294e90ad3b3c9504bd69", "parents": [ "4d246e458918d469ad645fd5f937ac22982e0466" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:17:04 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 13:57:26 2009 -0700" }, "message": "PCI ASPM: cleanup misc in struct pcie_link_state\n\nCleanup for some fields in pcie_link_state.\n\n- Add comments.\n- make \"downstream_has_switch\" field 1-bit.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "4d246e458918d469ad645fd5f937ac22982e0466", "tree": "7af516967d8f9ef8824f74f9214bf74fdc93d894", "parents": [ "b6c2e54d3ea27719b920faf15db92dfe0260f0d2" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:15:38 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 13:57:25 2009 -0700" }, "message": "PCI ASPM: cleanup clkpm state in struct pcie_link_state\n\nThe \"clk_pm_capable\", \"clk_pm_enable\" and \"bios_clk_state\" fields in\nthe struct pcie_link_state only take 1-bit value. So those fields\ndon\u0027t need to be defined as unsigned int. This patch makes those\nfields 1-bit, and cleans up some related code.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "b6c2e54d3ea27719b920faf15db92dfe0260f0d2", "tree": "407745d063fcae2b390515059e17cee5b2d3c13e", "parents": [ "80bfdbe370d56a1448c7078cd6d286b89241a72e" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:14:58 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 13:57:25 2009 -0700" }, "message": "PCI ASPM: cleanup latency field in struct pcie_link_state\n\nClean up latency related data structures for ASPM.\n\n- Introduce struct acpi_latency for exit latency and acceptable\n latency management. With this change, struct endpoint_state is no\n longer needed.\n\n- We don\u0027t need to hold both upstream latency and downstream latency\n in the current implementation.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "80bfdbe370d56a1448c7078cd6d286b89241a72e", "tree": "4d3f8c82aa87c1bf498946103b1e816f88121292", "parents": [ "dc64cd1131a3b5762e26bd8b01dc79030dd0c555" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:12:43 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 13:57:25 2009 -0700" }, "message": "PCI ASPM: cleanup aspm state field in struct pcie_link_state\n\nThe \"support_state\", \"enabled_state\" and \"bios_aspm_state\" fields in\nthe struct pcie_link_state take 2-bit value. So those fields don\u0027t\nneed to be defined as unsigned int. This patch makes those fields\n2-bit, and cleans up some related code.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "dc64cd1131a3b5762e26bd8b01dc79030dd0c555", "tree": "6a994b4e5fc840e071cc2e7510b35a8c7d549200", "parents": [ "268a03a42d3377d5fb41e6e7cbdec4e0b65cab2e" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed May 13 12:11:33 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 13:57:25 2009 -0700" }, "message": "PCI ASPM: fix typo in struct pcie_link_state\n\nFix a typo in struct pcie_link_state.\n\nThe \"sibiling\" field in the struct pcie_link_state should be\n\"sibling\".\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "268a03a42d3377d5fb41e6e7cbdec4e0b65cab2e", "tree": "3d94d3a53255fc1acc920f64a85445dbef35f06c", "parents": [ "110828c9cdce6e8ec68479ced4ca0bdc1135bb91" ], "author": { "name": "Alex Chiang", "email": "achiang@hp.com", "time": "Wed Jun 17 19:03:57 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 13:57:24 2009 -0700" }, "message": "PCI: drivers/pci/slot.c should depend on CONFIG_SYSFS\n\nThere is no way to interact with a physical PCI slot without\nsysfs, so encode the dependency and prevent this build error:\n\n\tdrivers/pci/slot.c: In function \u0027pci_hp_create_module_link\u0027:\n\tdrivers/pci/slot.c:327: error: \u0027module_kset\u0027 undeclared\n\nThis patch _should_ make pci-sysfs.o depend on CONFIG_SYSFS too,\nbut we cannot (yet) because the PCI core merrily assumes the\nexistence of sysfs:\n\n\tdrivers/built-in.o: In function `pci_bus_add_device\u0027:\n\tdrivers/pci/bus.c:89: undefined reference to `pci_create_sysfs_dev_files\u0027\n\tdrivers/built-in.o: In function `pci_stop_dev\u0027:\n\tdrivers/pci/remove.c:24: undefined reference to `pci_remove_sysfs_dev_files\u0027\n\nSo do the minimal bit for now and figure out how to untangle it\nlater.\n\nReported-by: Randy Dunlap \u003crandy.dunlap@oracle.com\u003e\nAcked-by: Randy Dunlap \u003crandy.dunlap@oracle.com\u003e\nReported-by: Stephen Rothwell \u003csfr@canb.auug.org.au\u003e\nFix-suggested-by: Matthew Wilcox \u003cmatthew@wil.cx\u003e\nSigned-off-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "110828c9cdce6e8ec68479ced4ca0bdc1135bb91", "tree": "6829824540b2047e275a557609606723a52eb429", "parents": [ "7d9a73f6dcf4390d256bf19330c81e91523a26d5" ], "author": { "name": "Matthew Wilcox", "email": "matthew@wil.cx", "time": "Tue Jun 16 06:31:45 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 18 13:57:24 2009 -0700" }, "message": "PCI: remove redundant __msi_set_enable()\n\nWe have the \u0027pos\u0027 of the MSI capability at all locations which call\nmsi_set_enable(), so pass it to msi_set_enable() instead of making it\nfind the capability every time.\n\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "d6aa484c1c0cd39ff3a42f4050b55d2a5b285ef5", "tree": "0ed1b14e195fcdf460c2ab64893a8105495cc262", "parents": [ "97719a8726fe8d3ea12a85fbf4f514a915ba30ec" ], "author": { "name": "Alexander Chiang", "email": "achiang@hp.com", "time": "Wed Jun 10 19:55:50 2009 +0000" }, "committer": { "name": "Len Brown", "email": "len.brown@intel.com", "time": "Wed Jun 17 23:32:00 2009 -0400" }, "message": "PCI Hotplug: acpiphp: convert to acpi_get_pci_dev\n\nNow that acpi_get_pci_dev is available, let\u0027s use it instead of\nacpi_get_pci_id.\n\nSigned-off-by: Alex Chiang \u003cachiang@hp.com\u003e\nAcked-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: Len Brown \u003clen.brown@intel.com\u003e\n" }, { "commit": "275582031f9b3597a1b973f3ff617adfe639faa2", "tree": "7f4e2c43709758108042e5dcf9b89d756e5bf8e5", "parents": [ "ce597bb42aa84bc73db80509b7c37e7fbc0b75c4" ], "author": { "name": "Alexander Chiang", "email": "achiang@hp.com", "time": "Wed Jun 10 19:55:14 2009 +0000" }, "committer": { "name": "Len Brown", "email": "len.brown@intel.com", "time": "Wed Jun 17 23:22:15 2009 -0400" }, "message": "ACPI: Introduce acpi_is_root_bridge()\n\nReturns whether an ACPI CA node is a PCI root bridge or not.\n\nThis API is generically useful, and shouldn\u0027t just be a hotplug function.\n\nThe implementation becomes much simpler as well.\n\nSigned-off-by: Alex Chiang \u003cachiang@hp.com\u003e\nAcked-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Len Brown \u003clen.brown@intel.com\u003e\n" }, { "commit": "cebd78a8c5624b5cf04c39c3335a5fc8670a7b69", "tree": "426b2ef97ee950e11e231fff1286ae06cf1f3423", "parents": [ "7cc47662197b3050a974a6c6aed52291bb38ded0" ], "author": { "name": "Matthew Wilcox", "email": "willy@linux.intel.com", "time": "Wed Jun 17 16:33:33 2009 -0400" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Jun 17 14:04:42 2009 -0700" }, "message": "Fix pci_claim_resource\n\nInstead of starting from the iomem or ioport roots, start from the\nparent bus\u0027 resources. This fixes a bug where child resources would\nappear above their parents resources if they had the same size.\n\nSigned-off-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nTested-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "7d9a73f6dcf4390d256bf19330c81e91523a26d5", "tree": "dddaeb3e6a1f5d5dd8d1b96ed6105566b69a3b21", "parents": [ "f9cde5ffed17bf74f6bef042d99edb0622f58576" ], "author": { "name": "Frans Pop", "email": "elendil@planet.nl", "time": "Wed Jun 17 00:16:15 2009 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Jun 16 15:19:02 2009 -0700" }, "message": "PCI PM: consistently use type bool for wake enable variable\n\nOther functions use type bool, so use that for pci_enable_wake as well.\n\nSigned-off-by: Frans Pop \u003celendil@planet.nl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "ab7de999a2c771482698efa6fe7c7b7fcb1d482a", "tree": "64c3df6ccc31c2ca8ec912fec4699bf13aeab979", "parents": [ "d2abdf62882d982c58e7a6b09ecdcfcc28075e2e" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Tue Jun 16 16:25:40 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Jun 16 14:30:18 2009 -0700" }, "message": "PCI: remove invalid comment of msi_mask_irq()\n\nRemove invalid comment of msi_mask_irq().\n\nReviewed-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "d2abdf62882d982c58e7a6b09ecdcfcc28075e2e", "tree": "d43dd7e66f4de4e044ed632a9eb6d61c61019b78", "parents": [ "c12ff1df5f114484e3d8abd028769a624cc3399f" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Sun Jun 14 21:25:02 2009 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Jun 16 14:30:17 2009 -0700" }, "message": "PCI PM: Fix handling of devices without PM support by pci_target_state()\n\nIf a PCI device is not power-manageable either by the platform, or\nwith the help of the native PCI PM interface, pci_target_state() will\nreturn either PCI_D3hot, or PCI_POWER_ERROR for it, depending on\nwhether or not the device is configured to wake up the system. Alas,\nnone of these return values is correct, because each of them causes\npci_prepare_to_sleep() to return error code, although it should\ncomplete successfully in such a case.\n\nFix this problem by making pci_target_state() always return PCI_D0\nfor devices that cannot be power managed.\n\nCc: stable@kernel.org\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" } ], "next": "c12ff1df5f114484e3d8abd028769a624cc3399f" }