)]}' { "log": [ { "commit": "5fc6d897fde352bad5db5767e7260741a8cdd9e9", "tree": "cb918dd33b8288aadead08b04b9f308f9d8bcbd1", "parents": [ "400fb7f6a0cfe13025cb0296fdb4737da7025a8a" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Oct 07 16:44:50 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Oct 07 17:08:32 2010 -0700" }, "message": "async_tx: make async_tx channel switching opt-in\n\nThe majority of drivers in drivers/dma/ will never establish cross\nchannel operation chains and do not need the extra overhead in struct\ndma_async_tx_descriptor. Make channel switching opt-in by default.\n\nCc: Anatolij Gustschin \u003cagust@denx.de\u003e\nCc: Ira Snyder \u003ciws@ovro.caltech.edu\u003e\nCc: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nCc: Saeed Bishara \u003csaeed@marvell.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "6391987d6f8ced7d0fafaa1440dcc57bb4b34d8f", "tree": "027a3989fceb18c45cf6d435a87b9879e38b8216", "parents": [ "9646b7985e906e5fcea9375f016b4519c8318c21", "e8689e63d4d2046079f2db9d494ac05c6885ac0c", "0d688662aab9d80078be82aa5aea561346643298", "1f1846c6ceed07c03ef036a27864befe0f773997", "20dd63900d238e17b122fe0c7376ff090867f528" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Oct 07 15:19:01 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Oct 07 15:19:01 2010 -0700" }, "message": "Merge branches \u0027dma40\u0027, \u0027pl08x\u0027, \u0027fsldma\u0027, \u0027imx\u0027 and \u0027intel-mid\u0027 into dmaengine\n" }, { "commit": "a86ee03ce6f279ebe581a7a8c0c4393eaeb789ee", "tree": "e662a6492370232e008d405e4ed7bfa4be0aea2e", "parents": [ "cc60f8878eab892c03d06b10f389232b9b66bd83" ], "author": { "name": "Ira Snyder", "email": "iws@ovro.caltech.edu", "time": "Thu Sep 30 11:46:44 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Oct 07 14:41:40 2010 -0700" }, "message": "dma: add support for scatterlist to scatterlist copy\n\nThis adds support for scatterlist to scatterlist DMA transfers. A\nsimilar interface is exposed by the fsldma driver (through the DMA_SLAVE\nAPI) and by the ste_dma40 driver (through an exported function).\n\nThis patch paves the way for making this type of copy operation a part\nof the generic DMAEngine API. Futher patches will add support in\nindividual drivers.\n\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "782bc950d84e404422ba21008fd51ee894c8d231", "tree": "c8a10b80bcc571c6de8a19c39b0f447ca61039d6", "parents": [ "b30a3f6257ed2105259b404d419b4964e363928c" ], "author": { "name": "Sascha Hauer", "email": "s.hauer@pengutronix.de", "time": "Thu Sep 30 13:56:32 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Oct 05 15:49:26 2010 -0700" }, "message": "dmaengine: add possibility for cyclic transfers\n\nCyclic transfers are useful for audio where a single buffer divided\nin periods has to be transfered endlessly until stopped. After being\nprepared the transfer is started using the dma_async_descriptor-\u003etx_submit\nfunction. dma_async_descriptor-\u003ecallback is called after each period.\nThe transfer is stopped using the DMA_TERMINATE_ALL callback.\nWhile being used for cyclic transfers the channel cannot be used\nfor other transfer types.\n\nSigned-off-by: Sascha Hauer \u003cs.hauer@pengutronix.de\u003e\nCc: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "0b28330e39bbe0ffee4c56b09fc415fcec595ea3", "tree": "fcf504879883763557e696eff81427b1ab78f76b", "parents": [ "058276303dbc4ed089c1f7dad0871810b1f5ddf1", "caa20d974c86af496b419eef70010e63b7fab7ac" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon May 17 16:30:58 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon May 17 16:30:58 2010 -0700" }, "message": "Merge branch \u0027ioat\u0027 into dmaengine\n" }, { "commit": "caa20d974c86af496b419eef70010e63b7fab7ac", "tree": "a38165bd839a398528a4ef4c7fa8481fb0fefed3", "parents": [ "c86e1401c9f2ba8d989fa1c4b33d0f0ec3ba8aaf" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon May 17 16:24:16 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon May 17 16:24:16 2010 -0700" }, "message": "async_tx: trim dma_async_tx_descriptor in \u0027no channel switch\u0027 case\n\nSaves 24 bytes per descriptor (64-bit) when the channel-switching\ncapabilities of async_tx are not required.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "cc05ea0cd63437da2033b3ce6e033b1f1aaaf640", "tree": "78b2786870053f56d3ba077c628d2cc975a4c737", "parents": [ "8d318a50b3d72e3daf94131f91e1ab799a8d5ad4" ], "author": { "name": "Jassi Brar", "email": "jassi.brar@samsung.com", "time": "Tue May 04 18:22:15 2010 +0900" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon May 17 01:33:56 2010 -0700" }, "message": "DMA ENGINE: Do not reset \u0027private\u0027 of channel\n\nThe member \u0027private\u0027 of \u0027struct dma_chan\u0027 is meant for passing\ndata between client and the controller driver.\n\nThe DMA client driver may point it to platform specific stuff after\nacquiring the channel. So, it is the responsiblity of the same code\nto reset it, if it must.\n\nThe DMA engine doesn\u0027t set it and hence, shouldn\u0027t reset it either.\n\nThis reseting of private by DMA Engine comes in the way of implementing\ndefault channel settings during DMAC probe. That capability is useful\nfor not having the clients to always provide platform specific data,\nlike Rx/Tx FIFO addresses, which usually doesn\u0027t change across channel\nrequests.\n\nSigned-off-by: Jassi Brar \u003cjassi.brar@samsung.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "5a0e3ad6af8660be21ca98a971cd00f331318c05", "tree": "5bfb7be11a03176a87296a43ac6647975c00a1d1", "parents": [ "ed391f4ebf8f701d3566423ce8f17e614cde9806" ], "author": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Wed Mar 24 17:04:11 2010 +0900" }, "committer": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Tue Mar 30 22:02:32 2010 +0900" }, "message": "include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h\n\npercpu.h is included by sched.h and module.h and thus ends up being\nincluded when building most .c files. percpu.h includes slab.h which\nin turn includes gfp.h making everything defined by the two files\nuniversally available and complicating inclusion dependencies.\n\npercpu.h -\u003e slab.h dependency is about to be removed. Prepare for\nthis change by updating users of gfp and slab facilities include those\nheaders directly instead of assuming availability. As this conversion\nneeds to touch large number of source files, the following script is\nused as the basis of conversion.\n\n http://userweb.kernel.org/~tj/misc/slabh-sweep.py\n\nThe script does the followings.\n\n* Scan files for gfp and slab usages and update includes such that\n only the necessary includes are there. ie. if only gfp is used,\n gfp.h, if slab is used, slab.h.\n\n* When the script inserts a new include, it looks at the include\n blocks and try to put the new include such that its order conforms\n to its surrounding. It\u0027s put in the include block which contains\n core kernel includes, in the same order that the rest are ordered -\n alphabetical, Christmas tree, rev-Xmas-tree or at the end if there\n doesn\u0027t seem to be any matching order.\n\n* If the script can\u0027t find a place to put a new include (mostly\n because the file doesn\u0027t have fitting include block), it prints out\n an error message indicating which .h file needs to be added to the\n file.\n\nThe conversion was done in the following steps.\n\n1. The initial automatic conversion of all .c files updated slightly\n over 4000 files, deleting around 700 includes and adding ~480 gfp.h\n and ~3000 slab.h inclusions. The script emitted errors for ~400\n files.\n\n2. Each error was manually checked. Some didn\u0027t need the inclusion,\n some needed manual addition while adding it to implementation .h or\n embedding .c file was more appropriate for others. This step added\n inclusions to around 150 files.\n\n3. The script was run again and the output was compared to the edits\n from #2 to make sure no file was left behind.\n\n4. Several build tests were done and a couple of problems were fixed.\n e.g. lib/decompress_*.c used malloc/free() wrappers around slab\n APIs requiring slab.h to be added manually.\n\n5. The script was run on all .h files but without automatically\n editing them as sprinkling gfp.h and slab.h inclusions around .h\n files could easily lead to inclusion dependency hell. Most gfp.h\n inclusion directives were ignored as stuff from gfp.h was usually\n wildly available and often used in preprocessor macros. Each\n slab.h inclusion directive was examined and added manually as\n necessary.\n\n6. percpu.h was updated not to include slab.h.\n\n7. Build test were done on the following configurations and failures\n were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my\n distributed build env didn\u0027t work with gcov compiles) and a few\n more options had to be turned off depending on archs to make things\n build (like ipr on powerpc/64 which failed due to missing writeq).\n\n * x86 and x86_64 UP and SMP allmodconfig and a custom test config.\n * powerpc and powerpc64 SMP allmodconfig\n * sparc and sparc64 SMP allmodconfig\n * ia64 SMP allmodconfig\n * s390 SMP allmodconfig\n * alpha SMP allmodconfig\n * um on x86_64 SMP allmodconfig\n\n8. percpu.h modifications were reverted so that it could be applied as\n a separate patch and serve as bisection point.\n\nGiven the fact that I had only a couple of failures from tests on step\n6, I\u0027m fairly confident about the coverage of this conversion patch.\nIf there is a breakage, it\u0027s likely to be something in one of the arch\nheaders which should be easily discoverable easily on most builds of\nthe specific arch.\n\nSigned-off-by: Tejun Heo \u003ctj@kernel.org\u003e\nGuess-its-ok-by: Christoph Lameter \u003ccl@linux-foundation.org\u003e\nCc: Ingo Molnar \u003cmingo@redhat.com\u003e\nCc: Lee Schermerhorn \u003cLee.Schermerhorn@hp.com\u003e\n" }, { "commit": "0793448187643b50af89d36b08470baf45a3cab4", "tree": "b3313ff58d47e26a8cf707d196177effa1aadfbe", "parents": [ "c3635c78e500a52c9fcd55de381a72928d9e054d" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@stericsson.com", "time": "Fri Mar 26 16:50:49 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Mar 26 16:50:49 2010 -0700" }, "message": "DMAENGINE: generic channel status v2\n\nConvert the device_is_tx_complete() operation on the\nDMA engine to a generic device_tx_status()operation which\ncan return three states, DMA_TX_RUNNING, DMA_TX_COMPLETE,\nDMA_TX_PAUSED.\n\n[dan.j.williams@intel.com: update for timberdale]\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nAcked-by: Mark Brown \u003cbroonie@opensource.wolfsonmicro.com\u003e\nCc: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nCc: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nCc: Pavel Machek \u003cpavel@ucw.cz\u003e\nCc: Li Yang \u003cleoli@freescale.com\u003e\nCc: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nCc: Paul Mundt \u003clethal@linux-sh.org\u003e\nCc: Ralf Baechle \u003cralf@linux-mips.org\u003e\nCc: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nCc: Magnus Damm \u003cdamm@opensource.se\u003e\nCc: Liam Girdwood \u003clrg@slimlogic.co.uk\u003e\nCc: Joe Perches \u003cjoe@perches.com\u003e\nCc: Roland Dreier \u003crdreier@cisco.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "c3635c78e500a52c9fcd55de381a72928d9e054d", "tree": "87403f402227cd8b5572550e70facf81c9eaa0d9", "parents": [ "0f65169b1bf44220308e1ce1f6666ad03ddc27af" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@stericsson.com", "time": "Fri Mar 26 16:44:01 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Mar 26 16:44:01 2010 -0700" }, "message": "DMAENGINE: generic slave control v2\n\nConvert the device_terminate_all() operation on the\nDMA engine to a generic device_control() operation\nwhich can now optionally support also pausing and\nresuming DMA on a certain channel. Implemented for the\nCOH 901 318 DMAC as an example.\n\n[dan.j.williams@intel.com: update for timberdale]\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nAcked-by: Mark Brown \u003cbroonie@opensource.wolfsonmicro.com\u003e\nCc: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nCc: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nCc: Pavel Machek \u003cpavel@ucw.cz\u003e\nCc: Li Yang \u003cleoli@freescale.com\u003e\nCc: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nCc: Paul Mundt \u003clethal@linux-sh.org\u003e\nCc: Ralf Baechle \u003cralf@linux-mips.org\u003e\nCc: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nCc: Magnus Damm \u003cdamm@opensource.se\u003e\nCc: Liam Girdwood \u003clrg@slimlogic.co.uk\u003e\nCc: Joe Perches \u003cjoe@perches.com\u003e\nCc: Roland Dreier \u003crdreier@cisco.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "0a135ba14d71fb84c691a5386aff5049691fe6d7", "tree": "adb1de887dd6839d69d2fc16ffa2a10ff63298fa", "parents": [ "4850f524b2c4c8a4e9f8ef4dd9c7c4afde2f2b2c", "a29d8b8e2d811a24bbe49215a0f0c536b72ebc18" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Mar 03 07:34:18 2010 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Mar 03 07:34:18 2010 -0800" }, "message": "Merge branch \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tj/percpu\n\n* \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tj/percpu:\n percpu: add __percpu sparse annotations to what\u0027s left\n percpu: add __percpu sparse annotations to fs\n percpu: add __percpu sparse annotations to core kernel subsystems\n local_t: Remove leftover local.h\n this_cpu: Remove pageset_notifier\n this_cpu: Page allocator conversion\n percpu, x86: Generic inc / dec percpu instructions\n local_t: Move local.h include to ringbuffer.c and ring_buffer_benchmark.c\n module: Use this_cpu_xx to dynamically allocate counters\n local_t: Remove cpu_local_xx macros\n percpu: refactor the code in pcpu_[de]populate_chunk()\n percpu: remove compile warnings caused by __verify_pcpu_ptr()\n percpu: make accessors check for percpu pointer in sparse\n percpu: add __percpu for sparse.\n percpu: make access macros universal\n percpu: remove per_cpu__ prefix.\n" }, { "commit": "a29d8b8e2d811a24bbe49215a0f0c536b72ebc18", "tree": "5a714679aeebd5f7af5d1fc521f0db8639324f6c", "parents": [ "003cb608a2533d0927a83bc4e07e46d7a622eda9" ], "author": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Tue Feb 02 14:39:15 2010 +0900" }, "committer": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Wed Feb 17 11:17:38 2010 +0900" }, "message": "percpu: add __percpu sparse annotations to what\u0027s left\n\nAdd __percpu sparse annotations to places which didn\u0027t make it in one\nof the previous patches. All converions are trivial.\n\nThese annotations are to make sparse consider percpu variables to be\nin a different address space and warn if accessed without going\nthrough percpu accessors. This patch doesn\u0027t affect normal builds.\n\nSigned-off-by: Tejun Heo \u003ctj@kernel.org\u003e\nAcked-by: Borislav Petkov \u003cborislav.petkov@amd.com\u003e\nCc: Dan Williams \u003cdan.j.williams@intel.com\u003e\nCc: Huang Ying \u003cying.huang@intel.com\u003e\nCc: Len Brown \u003clenb@kernel.org\u003e\nCc: Neil Brown \u003cneilb@suse.de\u003e\n" }, { "commit": "adef477268ff5ddd0195611dc7e26d7a879fefe1", "tree": "ad7b36a817f5f045719b28ade67914a2ce775d5c", "parents": [ "abe94c756c08d50566c09a65b9c7fe72f83071c5" ], "author": { "name": "Anatolij Gustschin", "email": "agust@denx.de", "time": "Tue Jan 26 10:26:06 2010 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Feb 02 14:58:37 2010 -0700" }, "message": "dmaengine: fix memleak in dma_async_device_unregister\n\nWhile debugging a dma driver I noticed a memleak after\nunloading the driver module.\n\nCaught by kmemleak.\n\nSigned-off-by: Anatolij Gustschin \u003cagust@denx.de\u003e\nCc: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "d0316554d3586cbea60592a41391b5def2553d6f", "tree": "5e7418f0bacbc68cec5dfd1541e03eb56870aa02", "parents": [ "fb0bbb92d42d5bd0ab224605444efdfed06d6934", "51e99be00ce2713cbb841cedc997cafa6e26c7f4" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Dec 14 09:58:24 2009 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Dec 14 09:58:24 2009 -0800" }, "message": "Merge branch \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tj/percpu\n\n* \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tj/percpu: (34 commits)\n m68k: rename global variable vmalloc_end to m68k_vmalloc_end\n percpu: add missing per_cpu_ptr_to_phys() definition for UP\n percpu: Fix kdump failure if booted with percpu_alloc\u003dpage\n percpu: make misc percpu symbols unique\n percpu: make percpu symbols in ia64 unique\n percpu: make percpu symbols in powerpc unique\n percpu: make percpu symbols in x86 unique\n percpu: make percpu symbols in xen unique\n percpu: make percpu symbols in cpufreq unique\n percpu: make percpu symbols in oprofile unique\n percpu: make percpu symbols in tracer unique\n percpu: make percpu symbols under kernel/ and mm/ unique\n percpu: remove some sparse warnings\n percpu: make alloc_percpu() handle array types\n vmalloc: fix use of non-existent percpu variable in put_cpu_var()\n this_cpu: Use this_cpu_xx in trace_functions_graph.c\n this_cpu: Use this_cpu_xx for ftrace\n this_cpu: Use this_cpu_xx in nmi handling\n this_cpu: Use this_cpu operations in RCU\n this_cpu: Use this_cpu ops for VM statistics\n ...\n\nFix up trivial (famous last words) global per-cpu naming conflicts in\n\tarch/x86/kvm/svm.c\n\tmm/slab.c\n" }, { "commit": "7b3cc2b1fc2066391e498f3387204908c4eced21", "tree": "8a2bc28955710c580201046d04843773cb7d87a1", "parents": [ "4499a24dec00e037da7d09caccad45e7594a9c19" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 17:10:37 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 23:21:03 2009 -0700" }, "message": "async_tx: build-time toggling of async_{syndrome,xor}_val dma support\n\nioat3.2 does not support asynchronous error notifications which makes\nthe driver experience latencies when non-zero pq validate results are\nexpected. Provide a mechanism for turning off async_xor_val and\nasync_syndrome_val via Kconfig. This approach is generally useful for\nany driver that specifies ASYNC_TX_DISABLE_CHANNEL_SWITCH and would like\nto force the async_tx api to fall back to the synchronous path for\ncertain operations.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "4499a24dec00e037da7d09caccad45e7594a9c19", "tree": "d336eb5f67a2873bcd7e43ef64d5d149283e7e0f", "parents": [ "b57014def9afc2bd8a62299d2f51b77dad5ae0c7" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 17:10:25 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 23:21:03 2009 -0700" }, "message": "dmaengine: include xor/pq validate in device_has_all_tx_types()\n\nA channel must include these capabilities to satisfy\nASYNC_TX_DISABLE_CHANNEL_SWITCH.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "e7dcaa4755e35d7540bf19f316f8798357c53fa0", "tree": "69c41151378213382199b577f2bc7b0d8bd1cc22", "parents": [ "ca0c9584b1f16bd5911893647cb7f1be82e60554" ], "author": { "name": "Christoph Lameter", "email": "cl@linux-foundation.org", "time": "Sat Oct 03 19:48:23 2009 +0900" }, "committer": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Sat Oct 03 19:48:23 2009 +0900" }, "message": "this_cpu: Eliminate get/put_cpu\n\nThere are cases where we can use this_cpu_ptr and as the result\nof using this_cpu_ptr() we no longer need to determine the\ncurrently executing cpu.\n\nIn those places no get/put_cpu combination is needed anymore.\nThe local cpu variable can be eliminated.\n\nPreemption still needs to be disabled and enabled since the\nmodifications of the per cpu variables is not atomic. There may\nbe multiple per cpu variables modified and those must all\nbe from the same processor.\n\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nAcked-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nAcked-by: Tejun Heo \u003ctj@kernel.org\u003e\ncc: Eric Biederman \u003cebiederm@aristanetworks.com\u003e\ncc: Stephen Hemminger \u003cshemminger@vyatta.com\u003e\ncc: David L Stevens \u003cdlstevens@us.ibm.com\u003e\nSigned-off-by: Christoph Lameter \u003ccl@linux-foundation.org\u003e\nSigned-off-by: Tejun Heo \u003ctj@kernel.org\u003e\n" }, { "commit": "bbb20089a3275a19e475dbc21320c3742e3ca423", "tree": "216fdc1cbef450ca688135c5b8969169482d9a48", "parents": [ "3e48e656903e9fd8bc805c6a2c4264d7808d315b", "657a77fa7284d8ae28dfa48f1dc5d919bf5b2843" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:55:21 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:55:21 2009 -0700" }, "message": "Merge branch \u0027dmaengine\u0027 into async-tx-next\n\nConflicts:\n\tcrypto/async_tx/async_xor.c\n\tdrivers/dma/ioat/dma_v2.h\n\tdrivers/dma/ioat/pci.c\n\tdrivers/md/raid5.c\n" }, { "commit": "0803172778901e24a75ab074798d98c2b7411559", "tree": "a3e1d0cf4228d65dc1fac2ad56f3beb6b6f3474b", "parents": [ "1979b186b80449ac6574d97c254b694c8a99b703" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "message": "dmaengine: kill tx_list\n\nThe tx_list attribute of struct dma_async_tx_descriptor is common to\nmost, but not all dma driver implementations. None of the upper level\ncode (dmaengine/async_tx) uses it, so allow drivers to implement it\nlocally if they need it. This saves sizeof(struct list_head) bytes for\ndrivers that do not manage descriptors with a linked list (e.g.: ioatdma\nv2,3).\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "138f4c359d23d2ec38d18bd70dd9613ae515fe93", "tree": "ad7fafba6eac74d9d92ade839a65171466d67a70", "parents": [ "0403e3827788d878163f9ef0541b748b0f88ca5d" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:51 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:51 2009 -0700" }, "message": "dmaengine, async_tx: add a \"no channel switch\" allocator\n\nChannel switching is problematic for some dmaengine drivers as the\narchitecture precludes separating the -\u003eprep from -\u003esubmit. In these\ncases the driver can select ASYNC_TX_DISABLE_CHANNEL_SWITCH to modify\nthe async_tx allocator to only return channels that support all of the\nrequired asynchronous operations.\n\nFor example MD_RAID456\u003dy selects support for asynchronous xor, xor\nvalidate, pq, pq validate, and memcpy. When\nASYNC_TX_DISABLE_CHANNEL_SWITCH\u003dy any channel with all these\ncapabilities is marked DMA_ASYNC_TX allowing async_tx_find_channel() to\nquickly locate compatible channels with the guarantee that dependency\nchains will remain on one channel. When\nASYNC_TX_DISABLE_CHANNEL_SWITCH\u003dn async_tx_find_channel() may select\nchannels that lead to operation chains that need to cross channel\nboundaries using the async_tx channel switch capability.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "f9dd2134374c8de6b911e2b8652c6c9622eaa658", "tree": "c1b8f8d622941606b9e7247ab31d811ba4295011", "parents": [ "4b652f0db3be891c7b76b109c3b55003b920fc96", "07a3b417dc3d00802bd7b4874c3e811f0b015a7d" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:29 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:29 2009 -0700" }, "message": "Merge branch \u0027md-raid6-accel\u0027 into ioat3.2\n\nConflicts:\n\tinclude/linux/dmaengine.h\n" }, { "commit": "b2f46fd8ef3dff2ab30f31126833f78b7480283a", "tree": "9f111e3e313b4d142c12d2d8156a2704a36904f8", "parents": [ "95475e57113c66aac7583925736ed2e2d58c990d" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 14 12:20:36 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:09:27 2009 -0700" }, "message": "async_tx: add support for asynchronous GF multiplication\n\n[ Based on an original patch by Yuri Tikhonov ]\n\nThis adds support for doing asynchronous GF multiplication by adding\ntwo additional functions to the async_tx API:\n\n async_gen_syndrome() does simultaneous XOR and Galois field\n multiplication of sources.\n\n async_syndrome_val() validates the given source buffers against known P\n and Q values.\n\nWhen a request is made to run async_pq against more than the hardware\nmaximum number of supported sources we need to reuse the previous\ngenerated P and Q values as sources into the next operation. Care must\nbe taken to remove Q from P\u0027 and P from Q\u0027. For example to perform a 5\nsource pq op with hardware that only supports 4 sources at a time the\nfollowing approach is taken:\n\np, q \u003d PQ(src0, src1, src2, src3, COEF({01}, {02}, {04}, {08}))\np\u0027, q\u0027 \u003d PQ(p, q, q, src4, COEF({00}, {01}, {00}, {10}))\n\np\u0027 \u003d p + q + q + src4 \u003d p + src4\nq\u0027 \u003d {00}*p + {01}*q + {00}*q + {10}*src4 \u003d q + {10}*src4\n\nNote: 4 is the minimum acceptable maxpq otherwise we punt to\nsynchronous-software path.\n\nThe DMA_PREP_CONTINUE flag indicates to the driver to reuse p and q as\nsources (in the above manner) and fill the remaining slots up to maxpq\nwith the new sources/coefficients.\n\nNote1: Some devices have native support for P+Q continuation and can skip\nthis extra work. Devices with this capability can advertise it with\ndma_set_maxpq. It is up to each driver how to handle the\nDMA_PREP_CONTINUE flag.\n\nNote2: The api supports disabling the generation of P when generating Q,\nthis is ignored by the synchronous path but is implemented by some dma\ndevices to save unnecessary writes. In this case the continuation\nalgorithm is simplified to only reuse Q as a source.\n\nCc: H. Peter Anvin \u003chpa@zytor.com\u003e\nCc: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\nSigned-off-by: Yuri Tikhonov \u003cyur@emcraft.com\u003e\nSigned-off-by: Ilya Yanok \u003cyanok@emcraft.com\u003e\nReviewed-by: Andre Noll \u003cmaan@systemlinux.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "95475e57113c66aac7583925736ed2e2d58c990d", "tree": "933aa0ca3bffef5b1457c516fbe3e8690b4c4cb1", "parents": [ "af1f951eb6ef27b01cbfb3f6c21b770af4368a6d" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 14 12:19:02 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:09:27 2009 -0700" }, "message": "async_tx: remove walk of tx-\u003eparent chain in dma_wait_for_async_tx\n\nWe currently walk the parent chain when waiting for a given tx to\ncomplete however this walk may race with the driver cleanup routine.\nThe routines in async_raid6_recov.c may fall back to the synchronous\npath at any point so we need to be prepared to call async_tx_quiesce()\n(which calls dma_wait_for_async_tx). To remove the -\u003eparent walk we\nguarantee that every time a dependency is attached -\u003eissue_pending() is\ninvoked, then we can simply poll the initial descriptor until\ncompletion.\n\nThis also allows for a lighter weight \u0027issue pending\u0027 implementation as\nthere is no longer a requirement to iterate through all the channels\u0027\n-\u003eissue_pending() routines as long as operations have been submitted in\nan ordered chain. async_tx_issue_pending() is added for this case.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "4f005dbe5584fe54c9f6d6d4f0acd3fb29be84da", "tree": "d9a4add9553af6c50fae59a79e9ab217945a7090", "parents": [ "ca50a51e890b0a62b44b5642c1ba5049909e5a8b" ], "author": { "name": "Maciej Sosnowski", "email": "maciej.sosnowski@intel.com", "time": "Thu Apr 23 12:31:51 2009 +0200" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue May 12 14:41:47 2009 -0700" }, "message": "ioatdma: fix \"ioatdma frees DMA memory with wrong function\"\n\nas reported by Alexander Beregalov \u003ca.beregalov@gmail.com\u003e\n\nioatdma 0000:00:08.0: DMA-API: device driver frees DMA memory with\nwrong function [device address\u003d0x000000007f76f800] [size\u003d2000 bytes]\n[map\nped as single] [unmapped as page]\n\nThe ioatdma driver was unmapping all regions\n(either allocated as page or single) using unmap_page.\nThis patch lets dma driver recognize if unmap_single or unmap_page should be used.\nIt introduces two new dma control flags:\nDMA_COMPL_SRC_UNMAP_SINGLE and DMA_COMPL_DEST_UNMAP_SINGLE.\nThey should be set to indicate dma driver to do dma-unmapping as single\n(first one for the source, tha latter for the destination).\nIf respective flag is not set, the driver assumes dma-unmapping as page.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nReported-by: Alexander Beregalov \u003ca.beregalov@gmail.com\u003e\nTested-by: Alexander Beregalov \u003ca.beregalov@gmail.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "099f53cb50e45ef617a9f1d63ceec799e489418b", "tree": "fd57f259f58bcf615fe2b17734ed0cbec612782d", "parents": [ "fd74ea65883c7e6903e9b652795f72b723a2be69" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Apr 08 14:28:37 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Apr 08 14:28:37 2009 -0700" }, "message": "async_tx: rename zero_sum to val\n\n\u0027zero_sum\u0027 does not properly describe the operation of generating parity\nand checking that it validates against an existing buffer. Change the\nname of the operation to \u0027val\u0027 (for \u0027validate\u0027). This is in\nanticipation of the p+q case where it is a requirement to identify the\ntarget parity buffers separately from the source buffers, because the\ntarget parity buffers will not have corresponding pq coefficients.\n\nReviewed-by: Andre Noll \u003cmaan@systemlinux.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "0f571515c332e00b3515dbe0859ceaa30ab66e00", "tree": "6d67c555714264dda749e387cee6738f770abc5d", "parents": [ "e44e0aa3cfa97cddff01704751a4b25151830c72" ], "author": { "name": "Atsushi Nemoto", "email": "anemo@mba.ocn.ne.jp", "time": "Fri Mar 06 20:07:14 2009 +0900" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Mar 26 09:48:09 2009 -0700" }, "message": "dmaengine: Add privatecnt to revert DMA_PRIVATE property\n\nCurrently dma_request_channel() set DMA_PRIVATE capability but never\nclear it. So if a public channel was once grabbed by\ndma_request_channel(), the device stay PRIVATE forever. Add\nprivatecnt member to dma_device to correctly revert it.\n\n[lg@denx.de: fix bad usage of \u0027chan\u0027 in dma_async_device_register]\nSigned-off-by: Atsushi Nemoto \u003canemo@mba.ocn.ne.jp\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "ccccce229c633a92c42cd1a40c0738d7b0d12644", "tree": "a954537ae73f2e03c4431b244796cdc255af7a10", "parents": [ "8d47bae004f062630f69f7f83d098424252e232d" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 25 09:13:24 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 25 09:13:24 2009 -0700" }, "message": "dmaengine: initialize tx_list in dma_async_tx_descriptor_init\n\nCentralize this common initialization (and one case where ipu_idmac is\nduplicating -\u003echan initialization).\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "257b17ca030387cb17314cd1851507bdd1b4ddd5", "tree": "74f88050ecfb70e6370399bc8b34843b22472f85", "parents": [ "041b62374c7fedc11a8a1eeda2868612d3d1436c" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 25 09:13:23 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 25 09:13:23 2009 -0700" }, "message": "dmaengine: fail device registration if channel registration fails\n\nAtsushi points out:\n\"If alloc_percpu or kzalloc failed, chan_id does not match with its\nposition in device-\u003echannels list.\n\nAnd above \"continue\" looks buggy anyway. Keeping incomplete channels\nin device-\u003echannels list looks very dangerous...\"\n\nAlso, fix up leakage of idr_ref in the idr_pre_get() and channel init\nfail cases.\n\nReported-by: Atsushi Nemoto \u003canemo@mba.ocn.ne.jp\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "287d859222e0adbc67666a6154aaf42d7d5bbb54", "tree": "a3e00f7b42f91c0d00f9d5a8d79414939b3c566f", "parents": [ "9ccf3b5e8409927835c4d38cb2f380c9e4349e76" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Feb 18 14:48:26 2009 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Feb 18 15:37:55 2009 -0800" }, "message": "atmel-mci: fix initialization of dma slave data\n\nThe conversion of atmel-mci to dma_request_channel missed the\ninitialization of the channel dma_slave information. The filter_fn passed\nto dma_request_channel is responsible for initializing the channel\u0027s\nprivate data. This implementation has the additional benefit of enabling\na generic client-channel data passing mechanism.\n\nReviewed-by: Atsushi Nemoto \u003canemo@mba.ocn.ne.jp\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nAcked-by: Haavard Skinnemoen \u003chskinnemoen@atmel.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "83436a0560e9ef8af2f0796264dde4bed1415359", "tree": "ec195673813725fbfc49c6e56689682b162f42d4", "parents": [ "169d5f663759ec494aa74a552ce99486235e6e50" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Jan 19 14:39:10 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Jan 19 14:39:10 2009 -0700" }, "message": "dmaengine: kill some dubious WARN_ONCEs\n\ndma_find_channel and dma_issue_pending_all are good places to warn about\nimproper api usage. However, warning correctly means synchronizing with\ndma_list_mutex, i.e. too much overhead for these fast-path calls.\n\nReported-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "dd59b8537f6cb53ab863fafad86a5828f1e889a2", "tree": "a1236a8042583813fc7b9e32688b9bc6e7858ea0", "parents": [ "c59765042f53a79a7a65585042ff463b69cb248c" ], "author": { "name": "Yuri Tikhonov", "email": "yur@emcraft.com", "time": "Mon Jan 12 15:17:20 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Jan 12 15:19:29 2009 -0700" }, "message": "dmaengine: fix dependency chaining\n\nIn dmaengine we track the dependencies between the descriptors\nusing the \u0027next\u0027 pointers of the structure. These pointers are\nset to NULL as soon as the corresponding descriptor has been\nsubmitted to the channel (in dma_run_dependencies()).\n\nBut, the first \u0027next\u0027 in chain is still remaining set, regardless\nthe fact, that tx-\u003enext has been already submitted. This may lead to\nmultiple submissions of the same descriptor. This patch fixes this.\n\nActually, some previous implementation of the xxx_run_dependencies()\nfunction already had this fix in place. The fdb..0eaf3 commit, beside the\ncorrect things, broke this.\n\nCc: \u003cstable@kernel.org\u003e\nSigned-off-by: Yuri Tikhonov \u003cyur@emcraft.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "652afc27b26859a0ea5f6db681d80b83d2c43cf8", "tree": "fc314e981f67470ebca307548d4cd420da717298", "parents": [ "e2346677af86150c6083974585c131e8a2c3ddcc" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:22 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:22 2009 -0700" }, "message": "dmaengine: bump initcall level to arch_initcall\n\nThere are dmaengine users that would like to register dma devices at\nsubsys_initcall time to ensure channels are available by device_initcall\ntime.\n\nCc: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nCc: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nCc: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n\n" }, { "commit": "e2346677af86150c6083974585c131e8a2c3ddcc", "tree": "2205b224c4e961ad59dc684fb4db835aaf9515a0", "parents": [ "864498aaa9fef69ee166da023d12413a7776342d" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:21 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:21 2009 -0700" }, "message": "dmaengine: advertise all channels on a device to dma_filter_fn\n\nAllow dma_filter_fn routines to disambiguate multiple channels on a device\nrather than assuming that all channels on a device are equal.\n\nCc: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nReported-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n\n" }, { "commit": "864498aaa9fef69ee166da023d12413a7776342d", "tree": "023d6bfc15ba192c1a92caab3ff7525a84e409fc", "parents": [ "41d5e59c1299f27983977bcfe3b360600996051c" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:21 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:21 2009 -0700" }, "message": "dmaengine: use idr for registering dma device numbers\n\nThis brings some predictability to dma device numbers, i.e. an rmmod/insmod\ncycle may now result in /sys/class/dma/dma0chan0 being restored rather than\n/sys/class/dma/dma1chan0 appearing.\n\nCc: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n\n" }, { "commit": "41d5e59c1299f27983977bcfe3b360600996051c", "tree": "f0e80b6fea3af04f266843af97f433198ad535c7", "parents": [ "4fac7fa57cf8001be259688468c825f836daf739" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:21 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:21 2009 -0700" }, "message": "dmaengine: add a release for dma class devices and dependent infrastructure\n\nResolves:\nWARNING: at drivers/base/core.c:122 device_release+0x4d/0x52()\nDevice \u0027dma0chan0\u0027 does not have a release() function, it is broken and must be fixed.\n\nThe dma_chan_dev object is introduced to gear-match sysfs kobject and\ndmaengine channel lifetimes. When a channel is removed access to the\nsysfs entries return -ENODEV until the kobject can be released.\n\nThe bulk of the change is updates to existing code to handle the extra\nlayer of indirection between a dma_chan and its struct device.\n\nReported-by: Alexander Beregalov \u003ca.beregalov@gmail.com\u003e\nAcked-by: Stephen Hemminger \u003cshemminger@vyatta.com\u003e\nCc: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n\n" }, { "commit": "7dd602510128d7a64b11ff3b7d4f30ac8e3946ce", "tree": "6a87f942c72b0b02d24db7144cad435211178fcc", "parents": [ "f27c580c3628d79b17f38976d842a6d7f3616e2e" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:19 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:19 2009 -0700" }, "message": "dmaengine: kill enum dma_state_client\n\nDMA_NAK is now useless. We can just use a bool instead.\n\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "f27c580c3628d79b17f38976d842a6d7f3616e2e", "tree": "f1a1a96c1130e7e1c88f75cb5f5aab4c53fe0297", "parents": [ "aa1e6f1a385eb2b04171ec841f3b760091e4a8ee" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:18 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:18 2009 -0700" }, "message": "dmaengine: remove \u0027bigref\u0027 infrastructure\n\nReference counting is done at the module level so clients need not worry\nthat a channel will leave while they are actively using dmaengine.\n\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "aa1e6f1a385eb2b04171ec841f3b760091e4a8ee", "tree": "1401e7f1e867e5d4a769b648605e0317d25d5ccb", "parents": [ "209b84a88fe81341b4d8d465acc4a67cb7c3feb3" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:17 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:17 2009 -0700" }, "message": "dmaengine: kill struct dma_client and supporting infrastructure\n\nAll users have been converted to either the general-purpose allocator,\ndma_find_channel, or dma_request_channel.\n\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n\n" }, { "commit": "209b84a88fe81341b4d8d465acc4a67cb7c3feb3", "tree": "134632ed8c914f0ee497e7a22bc616d84e068119", "parents": [ "74465b4ff9ac1da503025c0a0042e023bfa6505c" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:17 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:17 2009 -0700" }, "message": "dmaengine: replace dma_async_client_register with dmaengine_get\n\nNow that clients no longer need to be notified of channel arrival\ndma_async_client_register can simply increment the dmaengine_ref_count.\n\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "74465b4ff9ac1da503025c0a0042e023bfa6505c", "tree": "ce63f4a4b055b65cae1edaddd334931bf512c76e", "parents": [ "33df8ca068123457db56c316946a3c0e4ef787d6" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:16 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:16 2009 -0700" }, "message": "atmel-mci: convert to dma_request_channel and down-level dma_slave\n\ndma_request_channel provides an exclusive channel, so we no longer need to\npass slave data through dmaengine.\n\nCc: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "59b5ec21446b9239d706ab237fb261d525b75e81", "tree": "a437a354e84d311104829ca0e8b00b0ec8cb05c4", "parents": [ "f67b45999205164958de4ec0658d51fa4bee066d" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:15 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:15 2009 -0700" }, "message": "dmaengine: introduce dma_request_channel and private channels\n\nThis interface is primarily for device-to-memory clients which need to\nsearch for dma channels with platform-specific characteristics. The\nprototype is:\n\nstruct dma_chan *dma_request_channel(dma_cap_mask_t mask,\n dma_filter_fn filter_fn,\n void *filter_param);\n\nWhen the optional \u0027filter_fn\u0027 parameter is set to NULL\ndma_request_channel simply returns the first channel that satisfies the\ncapability mask. Otherwise, when the mask parameter is insufficient for\nspecifying the necessary channel, the filter_fn routine can be used to\ndisposition the available channels in the system. The filter_fn routine\nis called once for each free channel in the system. Upon seeing a\nsuitable channel filter_fn returns DMA_ACK which flags that channel to\nbe the return value from dma_request_channel. A channel allocated via\nthis interface is exclusive to the caller, until dma_release_channel()\nis called.\n\nTo ensure that all channels are not consumed by the general-purpose\nallocator the DMA_PRIVATE capability is provided to exclude a dma_device\nfrom general-purpose (memory-to-memory) consideration.\n\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n\n" }, { "commit": "2ba05622b8b143b0c95968ba59bddfbd6d2f2559", "tree": "b7b72d02a993ff2ba731d6608f4ab8ce87482bcb", "parents": [ "bec085134e446577a983f17f57d642a88d1af53b" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:14 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:14 2009 -0700" }, "message": "dmaengine: provide a common \u0027issue_pending_all\u0027 implementation\n\nasync_tx and net_dma each have open-coded versions of issue_pending_all,\nso provide a common routine in dmaengine.\n\nThe implementation needs to walk the global device list, so implement\nrcu to allow dma_issue_pending_all to run lockless. Clients protect\nthemselves from channel removal events by holding a dmaengine reference.\n\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n" }, { "commit": "bec085134e446577a983f17f57d642a88d1af53b", "tree": "7d29afc53fedc72349ee78112fb71f68ff48ce24", "parents": [ "6f49a57aa5a0c6d4e4e27c85f7af6c83325a12d1" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:14 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:14 2009 -0700" }, "message": "dmaengine: centralize channel allocation, introduce dma_find_channel\n\nAllowing multiple clients to each define their own channel allocation\nscheme quickly leads to a pathological situation. For memory-to-memory\noffload all clients can share a central allocator.\n\nThis simply moves the existing async_tx allocator to dmaengine with\nminimal fixups:\n* async_tx.c:get_chan_ref_by_cap --\u003e dmaengine.c:nth_chan\n* async_tx.c:async_tx_rebalance --\u003e dmaengine.c:dma_channel_rebalance\n* split out common code from async_tx.c:__async_tx_find_channel --\u003e\n dma_find_channel\n\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n" }, { "commit": "6f49a57aa5a0c6d4e4e27c85f7af6c83325a12d1", "tree": "afba24357d1f4ff69ccb2b39a19542546590a50b", "parents": [ "07f2211e4fbce6990722d78c4f04225da9c0e9cf" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:14 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:14 2009 -0700" }, "message": "dmaengine: up-level reference counting to the module level\n\nSimply, if a client wants any dmaengine channel then prevent all dmaengine\nmodules from being removed. Once the clients are done re-enable module\nremoval.\n\nWhy?, beyond reducing complication:\n1/ Tracking reference counts per-transaction in an efficient manner, as\n is currently done, requires a complicated scheme to avoid cache-line\n bouncing effects.\n2/ Per-transaction ref-counting gives the false impression that a\n dma-driver can be gracefully removed ahead of its user (net, md, or\n dma-slave)\n3/ None of the in-tree dma-drivers talk to hot pluggable hardware, but\n if such an engine were built one day we still would not need to notify\n clients of remove events. The driver can simply return NULL to a\n -\u003eprep() request, something that is much easier for a client to handle.\n\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n" }, { "commit": "07f2211e4fbce6990722d78c4f04225da9c0e9cf", "tree": "51934e20a334e93c8c399d2e6375f264551e9bc3", "parents": [ "28405d8d9ce05f5bd869ef8b48da5086f9527d73" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Jan 05 17:14:31 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Jan 05 18:10:19 2009 -0700" }, "message": "dmaengine: remove dependency on async_tx\n\nasync_tx.ko is a consumer of dma channels. A circular dependency arises\nif modules in drivers/dma rely on common code in async_tx.ko. It\nprevents either module from being unloaded.\n\nMove dma_wait_for_async_tx and async_tx_run_dependencies to dmaeninge.o\nwhere they should have been from the beginning.\n\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "b0b42b16ff2b90f17bc1a4308366c9beba4b276e", "tree": "d9025b46fe5360300ae4e430df3246c67602adad", "parents": [ "532d3b1f86f41834a25373e3ded981d68e4ce17f" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Dec 03 17:17:07 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Dec 03 17:25:36 2008 -0700" }, "message": "dmaengine: protect \u0027id\u0027 from concurrent registrations\n\nThere is a possibility to have two devices registered with the same id.\n\nCc: \u003cstable@kernel.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "06190d8415219d9eef7d8f04b52a109e34575a76", "tree": "f7ac0ca156f5a2341c08417020ebbfc544b0c59b", "parents": [ "65e503814dec83c7b2ac955e75919d009109c919" ], "author": { "name": "Kay Sievers", "email": "kay.sievers@vrfy.org", "time": "Tue Nov 11 13:12:33 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Nov 11 13:12:33 2008 -0700" }, "message": "dmaengine: struct device - replace bus_id with dev_name(), dev_set_name()\n\nAcked-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Kay Sievers \u003ckay.sievers@vrfy.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "dc0ee6435cb92ccc81b14ff28d163fecc5a7f120", "tree": "0a494946593f36516a997f64cb299d898cdf463f", "parents": [ "e1d181efb14a93cf263d6c588a5395518edf3294" ], "author": { "name": "Haavard Skinnemoen", "email": "haavard.skinnemoen@atmel.com", "time": "Tue Jul 08 11:59:35 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 08 11:59:35 2008 -0700" }, "message": "dmaengine: Add slave DMA interface\n\nThis patch adds the necessary interfaces to the DMA Engine framework\nto use functionality found on most embedded DMA controllers: DMA from\nand to I/O registers with hardware handshaking.\n\nIn this context, hardware hanshaking means that the peripheral that\nowns the I/O registers in question is able to tell the DMA controller\nwhen more data is available for reading, or when there is room for\nmore data to be written. This usually happens internally on the chip,\nbut these signals may also be exported outside the chip for things\nlike IDE DMA, etc.\n\nA new struct dma_slave is introduced. This contains information that\nthe DMA engine driver needs to set up slave transfers to and from a\nslave device. Most engines supporting DMA slave transfers will want to\nextend this structure with controller-specific parameters. This\nadditional information is usually passed from the platform/board code\nthrough the client driver.\n\nA \"slave\" pointer is added to the dma_client struct. This must point\nto a valid dma_slave structure iff the DMA_SLAVE capability is\nrequested. The DMA engine driver may use this information in its\ndevice_alloc_chan_resources hook to configure the DMA controller for\nslave transfers from and to the given slave device.\n\nA new operation for preparing slave DMA transfers is added to struct\ndma_device. This takes a scatterlist and returns a single descriptor\nrepresenting the whole transfer.\n\nAnother new operation for terminating all pending transfers is added as\nwell. The latter is needed because there may be errors outside the scope\nof the DMA Engine framework that may require DMA operations to be\nterminated prematurely.\n\nDMA Engine drivers may extend the dma_device, dma_chan and/or\ndma_slave_descriptor structures to allow controller-specific\noperations. The client driver can detect such extensions by looking at\nthe DMA Engine\u0027s struct device, or it can request a specific DMA\nEngine device by setting the dma_dev field in struct dma_slave.\n\ndmaslave interface changes since v4:\n * Fix checkpatch errors\n * Fix changelog (there are no slave descriptors anymore)\n\ndmaslave interface changes since v3:\n * Use dma_data_direction instead of a new enum\n * Submit slave transfers as scatterlists\n * Remove the DMA slave descriptor struct\n\ndmaslave interface changes since v2:\n * Add a dma_dev field to struct dma_slave. If set, the client can\n only be bound to the DMA controller that corresponds to this\n device. This allows controller-specific extensions of the\n dma_slave structure; if the device matches, the controller may\n safely assume its extensions are present.\n * Move reg_width into struct dma_slave as there are currently no\n users that need to be able to set the width on a per-transfer\n basis.\n\ndmaslave interface changes since v1:\n * Drop the set_direction and set_width descriptor hooks. Pass the\n direction and width to the prep function instead.\n * Declare a dma_slave struct with fixed information about a slave,\n i.e. register addresses, handshake interfaces and such.\n * Add pointer to a dma_slave struct to dma_client. Can be NULL if\n the DMA_SLAVE capability isn\u0027t requested.\n * Drop the set_slave device hook since the alloc_chan_resources hook\n now has enough information to set up the channel for slave\n transfers.\n\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "848c536a37b8db4e461f14ca15fe29850151c822", "tree": "f4a88e92e31de28511e3a3de99200a77d2613dae", "parents": [ "4a776f0aa922a552460192c07b56f4fe9cd82632" ], "author": { "name": "Haavard Skinnemoen", "email": "haavard.skinnemoen@atmel.com", "time": "Tue Jul 08 11:58:58 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 08 11:58:58 2008 -0700" }, "message": "dmaengine: Add dma_client parameter to device_alloc_chan_resources\n\nA DMA controller capable of doing slave transfers may need to know a\nfew things about the slave when preparing the channel. We don\u0027t want\nto add this information to struct dma_channel since the channel hasn\u0027t\nyet been bound to a client at this point.\n\nInstead, pass a reference to the client requesting the channel to the\ndriver\u0027s device_alloc_chan_resources hook so that it can pick the\nnecessary information from the dma_client struct by itself.\n\n[dan.j.williams@intel.com: fixed up fsldma and mv_xor]\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "7cc5bf9a3a84e5a02e23e5739fb894790b37c101", "tree": "b526b348ed1b64884bf672924540bb5dc29cb211", "parents": [ "9c402f4e196290692d998b188f9094deb1619e57" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 08 11:58:21 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 08 11:58:21 2008 -0700" }, "message": "dmaengine: track the number of clients using a channel\n\nHaavard\u0027s dma-slave interface would like to test for exclusive access to a\nchannel. The standard channel refcounting is not sufficient in that it\ntracks more than just client references, it is also inaccurate as reference\ncounts are percpu until the channel is removed.\n\nThis change also enables a future fix to deallocate resources when a client\ndeclines to use a capable channel.\n\nAcked-by: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "1099dc79245719c046e632212ec09d6ec1154ef5", "tree": "e80912e5d819d131d51b6845d8aff03bd7f2b9f6", "parents": [ "65bc3ffe8c067e387fe5557bc3ea5071071f6af9" ], "author": { "name": "Haavard Skinnemoen", "email": "hskinnemoen@atmel.com", "time": "Tue Jul 08 11:58:05 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 08 11:58:05 2008 -0700" }, "message": "dmaengine: Couple DMA channels to their physical DMA device\n\nSet the \u0027parent\u0027 field of channel class devices to point to the\nphysical DMA device initialized by the DMA engine driver.\n\nThis allows drivers to use chan-\u003edev.parent for syncing DMA buffers\nand adds a \u0027device\u0027 symlink to the real device in\n/sys/class/dma/dmaXchanY.\n\nSigned-off-by: Haavard Skinnemoen \u003chskinnemoen@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "8a5703f846e2363fc466aff3f53608340a1ae33f", "tree": "b229bba81473078275ff811254bf23f640f85e09", "parents": [ "218ff137bc67252694420563d23d051ab9227f17" ], "author": { "name": "Sebastian Siewior", "email": "bigeasy@tglx.de", "time": "Mon Apr 21 22:38:45 2008 +0000" }, "committer": { "name": "Jesper Juhl", "email": "juhl@hera.kernel.org", "time": "Mon Apr 21 22:38:45 2008 +0000" }, "message": "DMA engine: typo fixes\n\nSpelling fixes for dmaengine.[ch]\n\nSigned-off-by: Sebastian Siewior \u003cbigeasy@linutronix.de\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Jesper Juhl \u003cjesper.juhl@gmail.com\u003e\n" }, { "commit": "636bdeaa1243327501edfd2a597ed7443eb4239a", "tree": "59b894f124e3664ea4a537d7c07c527abdb9c8da", "parents": [ "c4fe15541d0ef5cc8cc1ce43057663851f8fc387" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Apr 17 20:17:26 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Apr 17 13:25:54 2008 -0700" }, "message": "dmaengine: ack to flags: make use of the unused bits in the \u0027ack\u0027 field\n\n\u0027ack\u0027 is currently a simple integer that flags whether or not a client is done\ntouching fields in the given descriptor. It is effectively just a single bit\nof information. Converting this to a flags parameter allows the other bits to\nbe put to use to control completion actions, like dma-unmap, and capture\nresults, like xor-zero-sum \u003d\u003d 0.\n\nChanges are one of:\n1/ convert all open-coded -\u003eack manipulations to use async_tx_ack\n and async_tx_test_ack.\n2/ set the ack bit at prep time where possible\n3/ make drivers store the flags at prep time\n4/ add flags to the device_prep_dma_interrupt prototype\n\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "ce4d65a5db77e1568c82d5151a746f627c4f6ed5", "tree": "1f3936d2984fc03125bde025796465f9cada9075", "parents": [ "19242d7233df7d658405d4b7ee1758d21414cfaa" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Apr 17 20:17:26 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Apr 17 13:25:54 2008 -0700" }, "message": "async_tx: kill -\u003edevice_dependency_added\n\nDMA drivers no longer need to be notified of dependency submission\nevents as async_tx_run_dependencies and async_tx_channel_switch will\nhandle the scheduling and execution of dependent operations.\n\n[sfr@canb.auug.org.au: extend this for fsldma]\nAcked-by: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "19242d7233df7d658405d4b7ee1758d21414cfaa", "tree": "4bffa2700c30fdb454dfa150115a0607c6cf3d2a", "parents": [ "1c62979ed29a8e2bf9fbe1db101c81a0089676f8" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Apr 17 20:17:25 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Apr 17 13:25:05 2008 -0700" }, "message": "async_tx: fix multiple dependency submission\n\nShrink struct dma_async_tx_descriptor and introduce\nasync_tx_channel_switch to properly inject a channel switch interrupt in\nthe descriptor stream. This simplifies the locking model as drivers no\nlonger need to handle dma_async_tx_descriptor.lock.\n\nAcked-by: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "9b941c6660bae673e27c207f1d20d98ef8ecd450", "tree": "e34aa803ae33e745e0c013dc35ebafb8d9bcca55", "parents": [ "56822843ff99c88c778a614851328fcbb1503d10" ], "author": { "name": "Zhang Wei", "email": "wei.zhang@freescale.com", "time": "Thu Mar 13 17:45:28 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Mar 13 10:57:07 2008 -0700" }, "message": "dmaengine: Fix a bug about BUG_ON() on DMA engine capability DMA_INTERRUPT.\n\nThe device-\u003edevice_prep_dma_interrupt function is used by\nDMA_INTERRUPT capability, not DMA_ZERO_SUM.\n\nSigned-off-by: Zhang Wei \u003cwei.zhang@freescale.com\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "0036731c88fdb5bf4f04a796a30b5e445fc57f54", "tree": "66982e4a9fdb92fedadca35c0ccaa0b9a75e9d2e", "parents": [ "d909b347591a23c5a2c324fbccd4c9c966f31c67" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Feb 02 19:49:57 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Feb 06 10:12:17 2008 -0700" }, "message": "async_tx: kill tx_set_src and tx_set_dest methods\n\nThe tx_set_src and tx_set_dest methods were originally implemented to allow\nan array of addresses to be passed down from async_xor to the dmaengine\ndriver while minimizing stack overhead. Removing these methods allows\ndrivers to have all transaction parameters available at \u0027prep\u0027 time, saves\ntwo function pointers in struct dma_async_tx_descriptor, and reduces the\nnumber of indirect branches..\n\nA consequence of moving this data to the \u0027prep\u0027 routine is that\nmulti-source routines like async_xor need temporary storage to convert an\narray of linear addresses into an array of dma addresses. In order to keep\nthe same stack footprint of the previous implementation the input array is\nreused as storage for the dma addresses. This requires that\nsizeof(dma_addr_t) be less than or equal to sizeof(void *). As a\nconsequence CONFIG_DMADEVICES now depends on !CONFIG_HIGHMEM64G. It also\nrequires that drivers be able to make descriptor resources available when\nthe \u0027prep\u0027 routine is polled.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nAcked-by: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\n" }, { "commit": "891f78ea833edd4a1e524e15bfe297a7a84d81a0", "tree": "533f12df743c4adc6d2b40d048ffb7d16c93e591", "parents": [ "62ca8792560e5bd7dc09f54ed3523a7864f416c7" ], "author": { "name": "Tony Jones", "email": "tonyj@suse.de", "time": "Tue Sep 25 02:03:03 2007 +0200" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Thu Jan 24 20:40:05 2008 -0800" }, "message": "DMA: Convert from class_device to device for DMA engine\n\nSigned-off-by: Tony Jones \u003ctonyj@suse.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nCc: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\nCc: Kay Sievers \u003ckay.sievers@vrfy.org\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n" }, { "commit": "348badf1e825323c419dd118f65783db0f7d2ec8", "tree": "126cddb26c14233eaff8ddd6a240fe4ac69204ee", "parents": [ "90d8dabf74179e6615bd4688a118e12ec29ab7aa" ], "author": { "name": "Haavard Skinnemoen", "email": "hskinnemoen@atmel.com", "time": "Wed Nov 14 16:59:27 2007 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Wed Nov 14 18:45:39 2007 -0800" }, "message": "dmaengine: fix broken device refcounting\n\nWhen a DMA device is unregistered, its reference count is decremented twice\nfor each channel: Once dma_class_dev_release() and once in\ndma_chan_cleanup(). This may result in the DMA device driver\u0027s remove()\nfunction completing before all channels have been cleaned up, causing lots\nof use-after-free fun.\n\nFix it by incrementing the device\u0027s reference count twice for each\nchannel during registration.\n\n[dan.j.williams@intel.com: kill unnecessary client refcounting]\nSigned-off-by: Haavard Skinnemoen \u003chskinnemoen@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nSigned-off-by: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\nCc: \u003cstable@kernel.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "d379b01e9087a582d58f4b678208a4f8d8376fe7", "tree": "155920bca93c18afba66b9d5acfecd359d5bec65", "parents": [ "7405f74badf46b5d023c5d2b670b4471525f6c91" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Jul 09 11:56:42 2007 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Jul 13 08:06:13 2007 -0700" }, "message": "dmaengine: make clients responsible for managing channels\n\nThe current implementation assumes that a channel will only be used by one\nclient at a time. In order to enable channel sharing the dmaengine core is\nchanged to a model where clients subscribe to channel-available-events.\nInstead of tracking how many channels a client wants and how many it has\nreceived the core just broadcasts the available channels and lets the\nclients optionally take a reference. The core learns about the clients\u0027\nneeds at dma_event_callback time.\n\nIn support of multiple operation types, clients can specify a capability\nmask to only be notified of channels that satisfy a certain set of\ncapabilities.\n\nChangelog:\n* removed DMA_TX_ARRAY_INIT, no longer needed\n* dma_client_chan_free -\u003e dma_chan_release: switch to global reference\n counting only at device unregistration time, before it was also happening\n at client unregistration time\n* clients now return dma_state_client to dmaengine (ack, dup, nak)\n* checkpatch.pl fixes\n* fixup merge with git-ioat\n\nCc: Chris Leech \u003cchristopher.leech@intel.com\u003e\nSigned-off-by: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nAcked-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "7405f74badf46b5d023c5d2b670b4471525f6c91", "tree": "20dd20571637dba1c2b04c7b13ac208c33b5706b", "parents": [ "428ed6024fa74a271142f3257966e9b5e1cb37a1" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 02 11:10:43 2007 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Jul 13 08:06:11 2007 -0700" }, "message": "dmaengine: refactor dmaengine around dma_async_tx_descriptor\n\nThe current dmaengine interface defines mutliple routines per operation,\ni.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding\nmore operation types (xor, crc, etc) to this model would result in an\nunmanageable number of method permutations.\n\n\tAre we really going to add a set of hooks for each DMA engine\n\twhizbang feature?\n\t\t- Jeff Garzik\n\nThe descriptor creation process is refactored using the new common\ndma_async_tx_descriptor structure. Instead of per driver\ndo_\u003coperation\u003e_\u003cdest\u003e_to_\u003csrc\u003e methods, drivers integrate\ndma_async_tx_descriptor into their private software descriptor and then\ndefine a \u0027prep\u0027 routine per operation. The prep routine allocates a\ndescriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines\nare valid. Descriptor creation and submission becomes:\n\nstruct dma_device *dev;\nstruct dma_chan *chan;\nstruct dma_async_tx_descriptor *tx;\n\ntx \u003d dev-\u003edevice_prep_dma_\u003coperation\u003e(chan, len, int_flag)\ntx-\u003etx_set_src(dma_addr_t, tx, index /* for multi-source ops */)\ntx-\u003etx_set_dest(dma_addr_t, tx, index)\ntx-\u003etx_submit(tx)\n\nIn addition to the refactoring, dma_async_tx_descriptor also lays the\ngroundwork for definining cross-channel-operation dependencies, and a\ncallback facility for asynchronous notification of operation completion.\n\nChangelog:\n* drop dma mapping methods, suggested by Chris Leech\n* fix ioat_dma_dependency_added, also caught by Andrew Morton\n* fix dma_sync_wait, change from Andrew Morton\n* uninline large functions, change from Andrew Morton\n* add tx-\u003ecallback \u003d NULL to dmaengine calls to interoperate with async_tx\n calls\n* hookup ioat_tx_submit\n* convert channel capabilities to a \u0027cpumask_t like\u0027 bitmap\n* removed DMA_TX_ARRAY_INIT, no longer needed\n* checkpatch.pl fixes\n* make set_src, set_dest, and tx_submit descriptor specific methods\n* fixup git-ioat merge\n* move group_list and phys to dma_async_tx_descriptor\n\nCc: Jeff Garzik \u003cjeff@garzik.org\u003e\nCc: Chris Leech \u003cchristopher.leech@intel.com\u003e\nSigned-off-by: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nAcked-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "ff487fb773749124550a5ad2b7fbfe0376af6f0d", "tree": "4162ef179d0496b8c5fa066a51cf97606e22c1be", "parents": [ "000725d56a196e72dc22328324c5ec5506265736" ], "author": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Thu Mar 08 09:57:34 2007 -0800" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Jul 11 15:39:03 2007 -0700" }, "message": "drivers/dma: handle sysfs errors\n\nFrom: Jeff Garzik \u003cjeff@garzik.org\u003e\n\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\nSigned-off-by: Chris Leech \u003cchristopher.leech@intel.com\u003e\n" }, { "commit": "765e3d8a71bbc1f3400667d5cfcfd7b03382d587", "tree": "0cf7dd6f707b10510d0c7343b5d4c198f093f725", "parents": [ "bed31ed9e1cd71d98ff0bc9212100adee523a10a" ], "author": { "name": "David Brownell", "email": "david-b@pacbell.net", "time": "Fri Mar 16 13:38:05 2007 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Fri Mar 16 19:25:03 2007 -0700" }, "message": "[PATCH] rm pointless dmaengine exports\n\nThis removes several pointless exports from drivers/dma/dmaengine.c; the\ndma_async_memcpy_*() functions are inlined by \u003clinux/dmaengine.h\u003e so those\nexports are inappropriate.\n\nIt also moves the existing EXPORT_SYMBOL declarations next to their functions,\nso it\u0027s now trivial to confirm one-to-one correspondence between exports and\nnonstatic symbols.\n\nSigned-off-by: David Brownell \u003cdbrownell@users.sourceforge.net\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nAcked-by: Chris Leech \u003cchristopher.leech@intel.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "6508871eddbbd3e62799f3b6182a6a4fd3ef31d5", "tree": "f8d5275b81e827326d8638b0286abd6bf19cd95c", "parents": [ "fe4ada2d6f0b746246e9b5bf0f4f2e4d3a07d26e" ], "author": { "name": "Randy Dunlap", "email": "rdunlap@xenotime.net", "time": "Mon Jul 03 19:45:31 2006 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Mon Jul 03 19:45:31 2006 -0700" }, "message": "[IOAT]: fix kernel-doc in source files\n\nFix kernel-doc warnings in drivers/dma/:\n- use correct function \u0026 parameter names\n- add descriptions where omitted\n\nSigned-off-by: Randy Dunlap \u003crdunlap@xenotime.net\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "17f3ae08b6e7fd778371f2cafbd1c988a67ee343", "tree": "9e33f603469628d9bbe679bede945d61e7417dbf", "parents": [ "1a2449a87bb7606113b1aa1a9d3c3e78ef189a1c" ], "author": { "name": "Andrew Morton", "email": "akpm@osdl.org", "time": "Thu May 25 13:26:53 2006 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sat Jun 17 21:25:58 2006 -0700" }, "message": "[I/OAT]: Do not use for_each_cpu().\n\nfor_each_cpu() is going away (and is gone in -mm).\n\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Chris Leech \u003cchristopher.leech@intel.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "c13c8260da3155f2cefb63b0d1b7dcdcb405c644", "tree": "ecfe02fa44a423a948f5fb5ad76497da2bb7a402", "parents": [ "427abfa28afedffadfca9dd8b067eb6d36bac53f" ], "author": { "name": "Chris Leech", "email": "christopher.leech@intel.com", "time": "Tue May 23 17:18:44 2006 -0700" }, "committer": { "name": "David S. Miller", "email": "davem@sunset.davemloft.net", "time": "Sat Jun 17 21:18:43 2006 -0700" }, "message": "[I/OAT]: DMA memcpy subsystem\n\nProvides an API for offloading memory copies to DMA devices\n\nSigned-off-by: Chris Leech \u003cchristopher.leech@intel.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" } ] }