)]}' { "log": [ { "commit": "6f68fbaafbaa033205cd131d3e1f3c4b914e9b78", "tree": "56b434496064ed170f94381e3ec4c6c340b71376", "parents": [ "6e4513972a5ad28517477d21f301a02ac7a0df76", "0b28330e39bbe0ffee4c56b09fc415fcec595ea3" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri May 21 17:05:46 2010 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri May 21 17:05:46 2010 -0700" }, "message": "Merge branch \u0027next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx\n\n* \u0027next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx:\n DMAENGINE: extend the control command to include an arg\n async_tx: trim dma_async_tx_descriptor in \u0027no channel switch\u0027 case\n DMAENGINE: DMA40 fix for allocation of logical channel 0\n DMAENGINE: DMA40 support paused channel status\n dmaengine: mpc512x: Use resource_size\n DMA ENGINE: Do not reset \u0027private\u0027 of channel\n ioat: Remove duplicated devm_kzalloc() calls for ioatdma_device\n ioat3: disable cacheline-unaligned transfers for raid operations\n ioat2,3: convert to producer/consumer locking\n ioat: convert to circ_buf\n DMAENGINE: Support for ST-Ericssons DMA40 block v3\n async_tx: use of kzalloc/kfree requires the include of slab.h\n dmaengine: provide helper for setting txstate\n DMAENGINE: generic channel status v2\n DMAENGINE: generic slave control v2\n dma: timb-dma: Update comment and fix compiler warning\n dma: Add timb-dma\n DMAENGINE: COH 901 318 fix bytesleft\n DMAENGINE: COH 901 318 rename confusing vars\n" }, { "commit": "caa20d974c86af496b419eef70010e63b7fab7ac", "tree": "a38165bd839a398528a4ef4c7fa8481fb0fefed3", "parents": [ "c86e1401c9f2ba8d989fa1c4b33d0f0ec3ba8aaf" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon May 17 16:24:16 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon May 17 16:24:16 2010 -0700" }, "message": "async_tx: trim dma_async_tx_descriptor in \u0027no channel switch\u0027 case\n\nSaves 24 bytes per descriptor (64-bit) when the channel-switching\ncapabilities of async_tx are not required.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "5157b4aa5b7de8787b6318e61bcc285031bb9088", "tree": "cf47d7739d646895a151bf3fd71e56e64dc9d260", "parents": [ "7ebd467551ed6ae200d7835a84bbda0dcadaa511" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue May 04 20:41:56 2010 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed May 05 07:52:56 2010 -0700" }, "message": "raid6: fix recovery performance regression\n\nThe raid6 recovery code should immediately drop back to the optimized\nsynchronous path when a p+q dma resource is not available. Otherwise we\nrun the non-optimized/multi-pass async code in sync mode.\n\nVerified with raid6test (NDISKS\u003d255)\n\nApplies to kernels \u003e\u003d 2.6.32.\n\nCc: \u003cstable@kernel.org\u003e\nAcked-by: NeilBrown \u003cneilb@suse.de\u003e\nReported-by: H. Peter Anvin \u003chpa@zytor.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "5a0e3ad6af8660be21ca98a971cd00f331318c05", "tree": "5bfb7be11a03176a87296a43ac6647975c00a1d1", "parents": [ "ed391f4ebf8f701d3566423ce8f17e614cde9806" ], "author": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Wed Mar 24 17:04:11 2010 +0900" }, "committer": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Tue Mar 30 22:02:32 2010 +0900" }, "message": "include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h\n\npercpu.h is included by sched.h and module.h and thus ends up being\nincluded when building most .c files. percpu.h includes slab.h which\nin turn includes gfp.h making everything defined by the two files\nuniversally available and complicating inclusion dependencies.\n\npercpu.h -\u003e slab.h dependency is about to be removed. Prepare for\nthis change by updating users of gfp and slab facilities include those\nheaders directly instead of assuming availability. As this conversion\nneeds to touch large number of source files, the following script is\nused as the basis of conversion.\n\n http://userweb.kernel.org/~tj/misc/slabh-sweep.py\n\nThe script does the followings.\n\n* Scan files for gfp and slab usages and update includes such that\n only the necessary includes are there. ie. if only gfp is used,\n gfp.h, if slab is used, slab.h.\n\n* When the script inserts a new include, it looks at the include\n blocks and try to put the new include such that its order conforms\n to its surrounding. It\u0027s put in the include block which contains\n core kernel includes, in the same order that the rest are ordered -\n alphabetical, Christmas tree, rev-Xmas-tree or at the end if there\n doesn\u0027t seem to be any matching order.\n\n* If the script can\u0027t find a place to put a new include (mostly\n because the file doesn\u0027t have fitting include block), it prints out\n an error message indicating which .h file needs to be added to the\n file.\n\nThe conversion was done in the following steps.\n\n1. The initial automatic conversion of all .c files updated slightly\n over 4000 files, deleting around 700 includes and adding ~480 gfp.h\n and ~3000 slab.h inclusions. The script emitted errors for ~400\n files.\n\n2. Each error was manually checked. Some didn\u0027t need the inclusion,\n some needed manual addition while adding it to implementation .h or\n embedding .c file was more appropriate for others. This step added\n inclusions to around 150 files.\n\n3. The script was run again and the output was compared to the edits\n from #2 to make sure no file was left behind.\n\n4. Several build tests were done and a couple of problems were fixed.\n e.g. lib/decompress_*.c used malloc/free() wrappers around slab\n APIs requiring slab.h to be added manually.\n\n5. The script was run on all .h files but without automatically\n editing them as sprinkling gfp.h and slab.h inclusions around .h\n files could easily lead to inclusion dependency hell. Most gfp.h\n inclusion directives were ignored as stuff from gfp.h was usually\n wildly available and often used in preprocessor macros. Each\n slab.h inclusion directive was examined and added manually as\n necessary.\n\n6. percpu.h was updated not to include slab.h.\n\n7. Build test were done on the following configurations and failures\n were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my\n distributed build env didn\u0027t work with gcov compiles) and a few\n more options had to be turned off depending on archs to make things\n build (like ipr on powerpc/64 which failed due to missing writeq).\n\n * x86 and x86_64 UP and SMP allmodconfig and a custom test config.\n * powerpc and powerpc64 SMP allmodconfig\n * sparc and sparc64 SMP allmodconfig\n * ia64 SMP allmodconfig\n * s390 SMP allmodconfig\n * alpha SMP allmodconfig\n * um on x86_64 SMP allmodconfig\n\n8. percpu.h modifications were reverted so that it could be applied as\n a separate patch and serve as bisection point.\n\nGiven the fact that I had only a couple of failures from tests on step\n6, I\u0027m fairly confident about the coverage of this conversion patch.\nIf there is a breakage, it\u0027s likely to be something in one of the arch\nheaders which should be easily discoverable easily on most builds of\nthe specific arch.\n\nSigned-off-by: Tejun Heo \u003ctj@kernel.org\u003e\nGuess-its-ok-by: Christoph Lameter \u003ccl@linux-foundation.org\u003e\nCc: Ingo Molnar \u003cmingo@redhat.com\u003e\nCc: Lee Schermerhorn \u003cLee.Schermerhorn@hp.com\u003e\n" }, { "commit": "e02a0e47a3f061c1a53fc4376332a988ec047e8a", "tree": "9663568d687abfc4c75a39c42fdc2d05dd68e04a", "parents": [ "cd78809f6191485a90ea6c92c2b58900ab5c156f" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Dec 17 13:55:38 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Dec 17 13:55:38 2009 -0700" }, "message": "async_tx: expand async raid6 test to cover ioatdma corner case\n\nAdd explicit 11 and 12 disks cases to exercise the 0 \u003c src_cnt % 8 \u003c 3\ncorner case in the ioatdma driver.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "7b3cc2b1fc2066391e498f3387204908c4eced21", "tree": "8a2bc28955710c580201046d04843773cb7d87a1", "parents": [ "4499a24dec00e037da7d09caccad45e7594a9c19" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 17:10:37 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 23:21:03 2009 -0700" }, "message": "async_tx: build-time toggling of async_{syndrome,xor}_val dma support\n\nioat3.2 does not support asynchronous error notifications which makes\nthe driver experience latencies when non-zero pq validate results are\nexpected. Provide a mechanism for turning off async_xor_val and\nasync_syndrome_val via Kconfig. This approach is generally useful for\nany driver that specifies ASYNC_TX_DISABLE_CHANNEL_SWITCH and would like\nto force the async_tx api to fall back to the synchronous path for\ncertain operations.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "da17bf4306fd3a52e938b121df82a7baa10eb282", "tree": "c5e5056287547e6674b63c690c911367e76f8d09", "parents": [ "030b07720be0f3bfada12ff6bfa3c61a91212f32" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Oct 19 14:05:12 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Oct 19 23:34:46 2009 -0700" }, "message": "async_tx: fix asynchronous raid6 recovery for ddf layouts\n\nThe raid6 recovery code currently requires special handling of the\n4-disk and 5-disk recovery scenarios for the native layout. Quoting\nfrom commit 0a82a623:\n\n In these situations the default N-disk algorithm will present\n 0-source or 1-source operations to dma devices. To cover for\n dma devices where the minimum source count is 2 we implement\n 4-disk and 5-disk handling in the recovery code.\n\nThe ddf layout presents disks\u003d6 and disks\u003d7 to the recovery code in\nthese situations. Instead of looking at the number of disks count the\nnumber of non-zero sources in the list and call the special case code\nwhen the number of non-failed sources is 0 or 1.\n\n[neilb@suse.de: replace \u0027ddf\u0027 flag with counting good sources]\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "030b07720be0f3bfada12ff6bfa3c61a91212f32", "tree": "591325a099403876dc808e5a38dbfe3d10957b6d", "parents": [ "5676470f06f783aebf545c8f17ca772911022068" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Oct 19 18:09:32 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Oct 19 23:34:46 2009 -0700" }, "message": "async_pq: rename scribble page\n\nThe global scribble page is used as a temporary destination buffer when\ndisabling the P or Q result is requested. The local scribble buffer\ncontains memory for performing address conversions. Rename the global\nvariable to avoid confusion.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n" }, { "commit": "5676470f06f783aebf545c8f17ca772911022068", "tree": "58a33d5fc031fc0a6090299dd8535c24182b7897", "parents": [ "6629542e79255e0dbef8ec82eaf644e1b2546c3c" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Oct 19 18:09:32 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Oct 19 18:20:20 2009 -0700" }, "message": "async_pq: kill a stray dma_map() call and other cleanups\n\n- update the kernel doc for async_syndrome to indicate what NULL in the\n source list means\n- whitespace fixups\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "b2141e6951ad56c8f65e70547baeabd5698e390a", "tree": "cc0a000cb6bc1eee887a6e3de5d8073f471bf9b5", "parents": [ "5dd33c9a4c29015f6d87568d33521c98931a387e" ], "author": { "name": "NeilBrown", "email": "neilb@suse.de", "time": "Fri Oct 16 16:40:34 2009 +1100" }, "committer": { "name": "NeilBrown", "email": "neilb@suse.de", "time": "Fri Oct 16 16:40:34 2009 +1100" }, "message": "raid6/async_tx: handle holes in block list in async_syndrome_val\n\nasync_syndrome_val check the P and Q blocks used for RAID6\ncalculations.\nWith DDF raid6, some of the data blocks might be NULL, so\nthis needs to be handled in the same way that async_gen_syndrome\nhandles it.\n\nAs async_syndrome_val calls async_xor, also enhance async_xor\nto detect and skip NULL blocks in the list.\n\nSigned-off-by: NeilBrown \u003cneilb@suse.de\u003e\n" }, { "commit": "5dd33c9a4c29015f6d87568d33521c98931a387e", "tree": "a79ac38e1957580743b708410b54694f2b1cbf77", "parents": [ "5e5e3e78ed9038b8f7112835d07084eefb9daa47" ], "author": { "name": "NeilBrown", "email": "neilb@suse.de", "time": "Fri Oct 16 16:40:25 2009 +1100" }, "committer": { "name": "NeilBrown", "email": "neilb@suse.de", "time": "Fri Oct 16 16:40:25 2009 +1100" }, "message": "md/async: don\u0027t pass a memory pointer as a page pointer.\n\nmd/raid6 passes a list of \u0027struct page *\u0027 to the async_tx routines,\nwhich then either DMA map them for offload, or take the page_address\nfor CPU based calculations.\n\nFor RAID6 we sometime leave \u0027blanks\u0027 in the list of pages.\nFor CPU based calcs, we want to treat theses as a page of zeros.\nFor offloaded calculations, we simply don\u0027t pass a page to the\nhardware.\n\nCurrently the \u0027blanks\u0027 are encoded as a pointer to\nraid6_empty_zero_page. This is a 4096 byte memory region, not a\n\u0027struct page\u0027. This is mostly handled correctly but is rather ugly.\n\nSo change the code to pass and expect a NULL pointer for the blanks.\nWhen taking page_address of a page, we need to check for a NULL and\nin that case use raid6_empty_zero_page.\n\nSigned-off-by: NeilBrown \u003cneilb@suse.de\u003e\n" }, { "commit": "1f6672d44c1ae7408b43c06170ec34eb0a0e9b9f", "tree": "b8c2be522cf71512a5f9587448967d78ae31bfbf", "parents": [ "cdef57dbb618608bfffda2fc32c8d0a4012a1d3a" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Sep 21 10:47:40 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Sep 21 10:47:40 2009 -0700" }, "message": "async_tx/raid6: add missing dma_unmap calls to the async fail case\n\nIf we are unable to offload async_mult() or async_sum_product(), then\nunmap the buffers before falling through to the synchronous path.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "1b6df6930994d5d027375b07ac9da63644eb5758", "tree": "1cf584491f4f1f5407a49ad531ec0b60205f6e38", "parents": [ "376ec37667b510453f5a62fcd95d762786e6a0a9" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Sep 16 21:03:29 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Sep 16 21:03:29 2009 -0700" }, "message": "raid6test: fix stack overflow\n\nTesting on x86_64 with NDISKS\u003d255 yields:\n\n do_IRQ: modprobe near stack overflow (cur:ffff88007d19c000,sp:ffff88007d19c128)\n\n...and eventually\n\n general protection fault: 0000 [#1]\n\nMoving the scribble buffers off the stack allows the test to complete\nsuccessfully.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "83544ae9f3991bfc7d5e0fe9a3008cd05a8d57b7", "tree": "bc4b28c2e5bdae01a2c8a250176fcdac6ae7a8ce", "parents": [ "9308add6ea4fedeba37b0d7c4630a542bd34f214" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:53 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:53 2009 -0700" }, "message": "dmaengine, async_tx: support alignment checks\n\nSome engines have transfer size and address alignment restrictions. Add\na per-operation alignment property to struct dma_device that the async\nroutines and dmatest can use to check alignment capabilities.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "138f4c359d23d2ec38d18bd70dd9613ae515fe93", "tree": "ad7fafba6eac74d9d92ade839a65171466d67a70", "parents": [ "0403e3827788d878163f9ef0541b748b0f88ca5d" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:51 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:51 2009 -0700" }, "message": "dmaengine, async_tx: add a \"no channel switch\" allocator\n\nChannel switching is problematic for some dmaengine drivers as the\narchitecture precludes separating the -\u003eprep from -\u003esubmit. In these\ncases the driver can select ASYNC_TX_DISABLE_CHANNEL_SWITCH to modify\nthe async_tx allocator to only return channels that support all of the\nrequired asynchronous operations.\n\nFor example MD_RAID456\u003dy selects support for asynchronous xor, xor\nvalidate, pq, pq validate, and memcpy. When\nASYNC_TX_DISABLE_CHANNEL_SWITCH\u003dy any channel with all these\ncapabilities is marked DMA_ASYNC_TX allowing async_tx_find_channel() to\nquickly locate compatible channels with the guarantee that dependency\nchains will remain on one channel. When\nASYNC_TX_DISABLE_CHANNEL_SWITCH\u003dn async_tx_find_channel() may select\nchannels that lead to operation chains that need to cross channel\nboundaries using the async_tx channel switch capability.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "0403e3827788d878163f9ef0541b748b0f88ca5d", "tree": "2dc73744bd92c268a1310f24668167f130877278", "parents": [ "f9dd2134374c8de6b911e2b8652c6c9622eaa658" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:50 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:50 2009 -0700" }, "message": "dmaengine: add fence support\n\nSome engines optimize operation by reading ahead in the descriptor chain\nsuch that descriptor2 may start execution before descriptor1 completes.\nIf descriptor2 depends on the result from descriptor1 then a fence is\nrequired (on descriptor2) to disable this optimization. The async_tx\napi could implicitly identify dependencies via the \u0027depend_tx\u0027\nparameter, but that would constrain cases where the dependency chain\nonly specifies a completion order rather than a data dependency. So,\nprovide an ASYNC_TX_FENCE to explicitly identify data dependencies.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "cb3c82992f62f838e6476a0bff12909158007fc6", "tree": "d6ced15a81340b9b8343c369fea22940f31f06eb", "parents": [ "58691d64c44ae41ddf098ecb31e9a994026e3cff" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 14 12:20:37 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:09:28 2009 -0700" }, "message": "async_tx: raid6 recovery self test\n\nPort drivers/md/raid6test/test.c to use the async raid6 recovery\nroutines. This is meant as a unit test for raid6 acceleration drivers. In\naddition to the 16-drive test case this implements tests for the 4-disk and\n5-disk special cases (dma devices can not generically handle less than 2\nsources), and adds a test for the D+Q case.\n\nReviewed-by: Andre Noll \u003cmaan@systemlinux.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "0a82a6239beecc95db6e05fe43ee62d16b381d38", "tree": "524f6417ae8128f5b1da322872e860bd4af5840d", "parents": [ "b2f46fd8ef3dff2ab30f31126833f78b7480283a" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 14 12:20:37 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:09:27 2009 -0700" }, "message": "async_tx: add support for asynchronous RAID6 recovery operations\n\n async_raid6_2data_recov() recovers two data disk failures\n\n async_raid6_datap_recov() recovers a data disk and the P disk\n\nThese routines are a port of the synchronous versions found in\ndrivers/md/raid6recov.c. The primary difference is breaking out the xor\noperations into separate calls to async_xor. Two helper routines are\nintroduced to perform scalar multiplication where needed.\nasync_sum_product() multiplies two sources by scalar coefficients and\nthen sums (xor) the result. async_mult() simply multiplies a single\nsource by a scalar.\n\nThis implemention also includes, in contrast to the original\nsynchronous-only code, special case handling for the 4-disk and 5-disk\narray cases. In these situations the default N-disk algorithm will\npresent 0-source or 1-source operations to dma devices. To cover for\ndma devices where the minimum source count is 2 we implement 4-disk and\n5-disk handling in the recovery code.\n\n[ Impact: asynchronous raid6 recovery routines for 2data and datap cases ]\n\nCc: Yuri Tikhonov \u003cyur@emcraft.com\u003e\nCc: Ilya Yanok \u003cyanok@emcraft.com\u003e\nCc: H. Peter Anvin \u003chpa@zytor.com\u003e\nCc: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\nReviewed-by: Andre Noll \u003cmaan@systemlinux.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "b2f46fd8ef3dff2ab30f31126833f78b7480283a", "tree": "9f111e3e313b4d142c12d2d8156a2704a36904f8", "parents": [ "95475e57113c66aac7583925736ed2e2d58c990d" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 14 12:20:36 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:09:27 2009 -0700" }, "message": "async_tx: add support for asynchronous GF multiplication\n\n[ Based on an original patch by Yuri Tikhonov ]\n\nThis adds support for doing asynchronous GF multiplication by adding\ntwo additional functions to the async_tx API:\n\n async_gen_syndrome() does simultaneous XOR and Galois field\n multiplication of sources.\n\n async_syndrome_val() validates the given source buffers against known P\n and Q values.\n\nWhen a request is made to run async_pq against more than the hardware\nmaximum number of supported sources we need to reuse the previous\ngenerated P and Q values as sources into the next operation. Care must\nbe taken to remove Q from P\u0027 and P from Q\u0027. For example to perform a 5\nsource pq op with hardware that only supports 4 sources at a time the\nfollowing approach is taken:\n\np, q \u003d PQ(src0, src1, src2, src3, COEF({01}, {02}, {04}, {08}))\np\u0027, q\u0027 \u003d PQ(p, q, q, src4, COEF({00}, {01}, {00}, {10}))\n\np\u0027 \u003d p + q + q + src4 \u003d p + src4\nq\u0027 \u003d {00}*p + {01}*q + {00}*q + {10}*src4 \u003d q + {10}*src4\n\nNote: 4 is the minimum acceptable maxpq otherwise we punt to\nsynchronous-software path.\n\nThe DMA_PREP_CONTINUE flag indicates to the driver to reuse p and q as\nsources (in the above manner) and fill the remaining slots up to maxpq\nwith the new sources/coefficients.\n\nNote1: Some devices have native support for P+Q continuation and can skip\nthis extra work. Devices with this capability can advertise it with\ndma_set_maxpq. It is up to each driver how to handle the\nDMA_PREP_CONTINUE flag.\n\nNote2: The api supports disabling the generation of P when generating Q,\nthis is ignored by the synchronous path but is implemented by some dma\ndevices to save unnecessary writes. In this case the continuation\nalgorithm is simplified to only reuse Q as a source.\n\nCc: H. Peter Anvin \u003chpa@zytor.com\u003e\nCc: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\nSigned-off-by: Yuri Tikhonov \u003cyur@emcraft.com\u003e\nSigned-off-by: Ilya Yanok \u003cyanok@emcraft.com\u003e\nReviewed-by: Andre Noll \u003cmaan@systemlinux.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "95475e57113c66aac7583925736ed2e2d58c990d", "tree": "933aa0ca3bffef5b1457c516fbe3e8690b4c4cb1", "parents": [ "af1f951eb6ef27b01cbfb3f6c21b770af4368a6d" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 14 12:19:02 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:09:27 2009 -0700" }, "message": "async_tx: remove walk of tx-\u003eparent chain in dma_wait_for_async_tx\n\nWe currently walk the parent chain when waiting for a given tx to\ncomplete however this walk may race with the driver cleanup routine.\nThe routines in async_raid6_recov.c may fall back to the synchronous\npath at any point so we need to be prepared to call async_tx_quiesce()\n(which calls dma_wait_for_async_tx). To remove the -\u003eparent walk we\nguarantee that every time a dependency is attached -\u003eissue_pending() is\ninvoked, then we can simply poll the initial descriptor until\ncompletion.\n\nThis also allows for a lighter weight \u0027issue pending\u0027 implementation as\nthere is no longer a requirement to iterate through all the channels\u0027\n-\u003eissue_pending() routines as long as operations have been submitted in\nan ordered chain. async_tx_issue_pending() is added for this case.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "af1f951eb6ef27b01cbfb3f6c21b770af4368a6d", "tree": "2009d83f93be62856eebbe9a41310d8ead4a6a13", "parents": [ "ad283ea4a3ce82cda2efe33163748a397b31b1eb" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:09:26 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:09:26 2009 -0700" }, "message": "async_tx: kill needless module_{init|exit}\n\nIf module_init and module_exit are nops then neither need to be defined.\n\n[ Impact: pure cleanup ]\n\nReviewed-by: Andre Noll \u003cmaan@systemlinux.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "ad283ea4a3ce82cda2efe33163748a397b31b1eb", "tree": "11cd739195f336895abe9e4a62d824e49a41c24f", "parents": [ "d6f38f31f3ad4b0dd33fe970988f14e7c65ef702" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:09:26 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Aug 29 19:09:26 2009 -0700" }, "message": "async_tx: add sum check flags\n\nReplace the flat zero_sum_result with a collection of flags to contain\nthe P (xor) zero-sum result, and the soon to be utilized Q (raid6 reed\nsolomon syndrome) zero-sum result. Use the SUM_CHECK_ namespace instead\nof DMA_ since these flags will be used on non-dma-zero-sum enabled\nplatforms.\n\nReviewed-by: Andre Noll \u003cmaan@systemlinux.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "04ce9ab385dc97eb55299d533cd3af79b8fc7529", "tree": "9b8d0b9c1eba820a8a107d05abc2e2f8d4d20a59", "parents": [ "a08abd8ca890a377521d65d493d174bebcaf694b" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Jun 03 14:22:28 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Jun 03 14:22:28 2009 -0700" }, "message": "async_xor: permit callers to pass in a \u0027dma/page scribble\u0027 region\n\nasync_xor() needs space to perform dma and page address conversions. In\nmost cases the code can simply reuse the struct page * array because the\nsize of the native pointer matches the size of a dma/page address. In\norder to support archs where sizeof(dma_addr_t) is larger than\nsizeof(struct page *), or to preserve the input parameters, we utilize a\nmemory region passed in by the caller.\n\nSince the code is now prepared to handle the case where it cannot\nperform address conversions on the stack, we no longer need the\n!HIGHMEM64G dependency in drivers/dma/Kconfig.\n\n[ Impact: don\u0027t clobber input buffers for address conversions ]\n\nReviewed-by: Andre Noll \u003cmaan@systemlinux.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "a08abd8ca890a377521d65d493d174bebcaf694b", "tree": "987c149a2d7d6ab345f426ac28191627b4a02a3e", "parents": [ "88ba2aa586c874681c072101287e15d40de7e6e2" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Jun 03 11:43:59 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Jun 03 14:07:35 2009 -0700" }, "message": "async_tx: structify submission arguments, add scribble\n\nPrepare the api for the arrival of a new parameter, \u0027scribble\u0027. This\nwill allow callers to identify scratchpad memory for dma address or page\naddress conversions. As this adds yet another parameter, take this\nopportunity to convert the common submission parameters (flags,\ndependency, callback, and callback argument) into an object that is\npassed by reference.\n\nAlso, take this opportunity to fix up the kerneldoc and add notes about\nthe relevant ASYNC_TX_* flags for each routine.\n\n[ Impact: moves api pass-by-value parameters to a pass-by-reference struct ]\n\nSigned-off-by: Andre Noll \u003cmaan@systemlinux.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "88ba2aa586c874681c072101287e15d40de7e6e2", "tree": "69a124fcd0a8a75ef9aae0cc4081bad83c770374", "parents": [ "099f53cb50e45ef617a9f1d63ceec799e489418b" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Apr 09 16:16:18 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Jun 03 14:07:34 2009 -0700" }, "message": "async_tx: kill ASYNC_TX_DEP_ACK flag\n\nIn support of inter-channel chaining async_tx utilizes an ack flag to\ngate whether a dependent operation can be chained to another. While the\nflag is not set the chain can be considered open for appending. Setting\nthe ack flag closes the chain and flags the descriptor for garbage\ncollection. The ASYNC_TX_DEP_ACK flag essentially means \"close the\nchain after adding this dependency\". Since each operation can only have\none child the api now implicitly sets the ack flag at dependency\nsubmission time. This removes an unnecessary management burden from\nclients of the api.\n\n[ Impact: clean up and enforce one dependency per operation ]\n\nReviewed-by: Andre Noll \u003cmaan@systemlinux.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "099f53cb50e45ef617a9f1d63ceec799e489418b", "tree": "fd57f259f58bcf615fe2b17734ed0cbec612782d", "parents": [ "fd74ea65883c7e6903e9b652795f72b723a2be69" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Apr 08 14:28:37 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Apr 08 14:28:37 2009 -0700" }, "message": "async_tx: rename zero_sum to val\n\n\u0027zero_sum\u0027 does not properly describe the operation of generating parity\nand checking that it validates against an existing buffer. Change the\nname of the operation to \u0027val\u0027 (for \u0027validate\u0027). This is in\nanticipation of the p+q case where it is a requirement to identify the\ntarget parity buffers separately from the source buffers, because the\ntarget parity buffers will not have corresponding pq coefficients.\n\nReviewed-by: Andre Noll \u003cmaan@systemlinux.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "729b5d1b8ec72c28e99840b3f300ba67726e3ab9", "tree": "8eac6444ea80bf05f461eb77243f56b008ee5083", "parents": [ "06164f3194e01ea4c76941ac60f541d656c8975f" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 25 09:13:25 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 25 09:13:25 2009 -0700" }, "message": "dmaengine: allow dma support for async_tx to be toggled\n\nProvide a config option for blocking the allocation of dma channels to\nthe async_tx api.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "06164f3194e01ea4c76941ac60f541d656c8975f", "tree": "0a5edc96e053ce0cf90139b48bc2ca7c7c130186", "parents": [ "54aee6a5f560d0e1bf3f39987c6ebe06daeb0ce1" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 25 09:13:25 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Mar 25 09:13:25 2009 -0700" }, "message": "async_tx: provide __async_inline for HAS_DMA\u003dn archs\n\nTo allow an async_tx routine to be compiled away on HAS_DMA\u003dn arch it\nneeds to be declared __always_inline otherwise the compiler may emit\ncode and cause a link error.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "209b84a88fe81341b4d8d465acc4a67cb7c3feb3", "tree": "134632ed8c914f0ee497e7a22bc616d84e068119", "parents": [ "74465b4ff9ac1da503025c0a0042e023bfa6505c" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:17 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:17 2009 -0700" }, "message": "dmaengine: replace dma_async_client_register with dmaengine_get\n\nNow that clients no longer need to be notified of channel arrival\ndma_async_client_register can simply increment the dmaengine_ref_count.\n\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "2ba05622b8b143b0c95968ba59bddfbd6d2f2559", "tree": "b7b72d02a993ff2ba731d6608f4ab8ce87482bcb", "parents": [ "bec085134e446577a983f17f57d642a88d1af53b" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:14 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:14 2009 -0700" }, "message": "dmaengine: provide a common \u0027issue_pending_all\u0027 implementation\n\nasync_tx and net_dma each have open-coded versions of issue_pending_all,\nso provide a common routine in dmaengine.\n\nThe implementation needs to walk the global device list, so implement\nrcu to allow dma_issue_pending_all to run lockless. Clients protect\nthemselves from channel removal events by holding a dmaengine reference.\n\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n" }, { "commit": "bec085134e446577a983f17f57d642a88d1af53b", "tree": "7d29afc53fedc72349ee78112fb71f68ff48ce24", "parents": [ "6f49a57aa5a0c6d4e4e27c85f7af6c83325a12d1" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:14 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:14 2009 -0700" }, "message": "dmaengine: centralize channel allocation, introduce dma_find_channel\n\nAllowing multiple clients to each define their own channel allocation\nscheme quickly leads to a pathological situation. For memory-to-memory\noffload all clients can share a central allocator.\n\nThis simply moves the existing async_tx allocator to dmaengine with\nminimal fixups:\n* async_tx.c:get_chan_ref_by_cap --\u003e dmaengine.c:nth_chan\n* async_tx.c:async_tx_rebalance --\u003e dmaengine.c:dma_channel_rebalance\n* split out common code from async_tx.c:__async_tx_find_channel --\u003e\n dma_find_channel\n\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n" }, { "commit": "6f49a57aa5a0c6d4e4e27c85f7af6c83325a12d1", "tree": "afba24357d1f4ff69ccb2b39a19542546590a50b", "parents": [ "07f2211e4fbce6990722d78c4f04225da9c0e9cf" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:14 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 06 11:38:14 2009 -0700" }, "message": "dmaengine: up-level reference counting to the module level\n\nSimply, if a client wants any dmaengine channel then prevent all dmaengine\nmodules from being removed. Once the clients are done re-enable module\nremoval.\n\nWhy?, beyond reducing complication:\n1/ Tracking reference counts per-transaction in an efficient manner, as\n is currently done, requires a complicated scheme to avoid cache-line\n bouncing effects.\n2/ Per-transaction ref-counting gives the false impression that a\n dma-driver can be gracefully removed ahead of its user (net, md, or\n dma-slave)\n3/ None of the in-tree dma-drivers talk to hot pluggable hardware, but\n if such an engine were built one day we still would not need to notify\n clients of remove events. The driver can simply return NULL to a\n -\u003eprep() request, something that is much easier for a client to handle.\n\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n" }, { "commit": "07f2211e4fbce6990722d78c4f04225da9c0e9cf", "tree": "51934e20a334e93c8c399d2e6375f264551e9bc3", "parents": [ "28405d8d9ce05f5bd869ef8b48da5086f9527d73" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Jan 05 17:14:31 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Jan 05 18:10:19 2009 -0700" }, "message": "dmaengine: remove dependency on async_tx\n\nasync_tx.ko is a consumer of dma channels. A circular dependency arises\nif modules in drivers/dma rely on common code in async_tx.ko. It\nprevents either module from being unloaded.\n\nMove dma_wait_for_async_tx and async_tx_run_dependencies to dmaeninge.o\nwhere they should have been from the beginning.\n\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "a06d568f7c5e40e34ea64881842deb8f4382babf", "tree": "15b38b4652705b7c58bd89052c81ab91ca94cc4a", "parents": [ "b0b42b16ff2b90f17bc1a4308366c9beba4b276e" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Dec 08 13:46:00 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Dec 08 13:46:00 2008 -0700" }, "message": "async_xor: dma_map destination DMA_BIDIRECTIONAL\n\nMapping the destination multiple times is a misuse of the dma-api.\nSince the destination may be reused as a source, ensure that it is only\nmapped once and that it is mapped bidirectionally. This appears to add\nugliness on the unmap side in that it always reads back the destination\naddress from the descriptor, but gcc can determine that dma_unmap is a\nnop and not emit the code that calculates its arguments.\n\nCc: \u003cstable@kernel.org\u003e\nCc: Saeed Bishara \u003csaeed@marvell.com\u003e\nAcked-by: Yuri Tikhonov \u003cyur@emcraft.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "fdb0ac80618729e6b12121c66449b8532990eaf3", "tree": "7572761bb23e6cc87ef2ffb061d9998f4e4dfd57", "parents": [ "6bfb09a1005193be5c81ebac9f3ef85210142650" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Sep 13 19:57:04 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Sep 13 19:57:04 2008 -0700" }, "message": "async_tx: make async_tx_run_dependencies() easier to read\n\n* Rename \u0027next\u0027 to \u0027dep\u0027\n* Move the channel switch check inside the loop to simplify\n termination\n\nAcked-by: Ilya Yanok \u003cyanok@emcraft.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "de24125dd0a452bfd4502fc448e3534c5d2e87aa", "tree": "30b86411bdbbe6ebea4598bd82856a399f66bd88", "parents": [ "b380b0d4f7dffcc235c0facefa537d4655619101" ], "author": { "name": "Yuri Tikhonov", "email": "yur@emcraft.com", "time": "Fri Sep 05 08:15:47 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Sep 05 08:15:47 2008 -0700" }, "message": "async_tx: fix the bug in async_tx_run_dependencies\n\nShould clear the next pointer of the TX if we are sure that the\nnext TX (say NXT) will be submitted to the channel too. Overwise,\nwe break the chain of descriptors, because we lose the information\nabout the next descriptor to run. So next time, when invoke\nasync_tx_run_dependencies() with TX, it\u0027s TX-\u003enext will be NULL, and\nNXT will be never submitted.\n\nCc: \u003cstable@kernel.org\u003e\t\t[2.6.26]\nSigned-off-by: Yuri Tikhonov \u003cyur@emcraft.com\u003e\nSigned-off-by: Ilya Yanok \u003cyanok@emcraft.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "e34a8ae79056e6cea4a1ac21119ee3c91f378f99", "tree": "8ff15ee52e38b2e0031e71313a01668589e6dccc", "parents": [ "ca5de404ff036a29b25e9a83f6919c9f606c5841" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Aug 05 10:22:05 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Aug 05 10:25:20 2008 -0700" }, "message": "async_tx: fix missing braces in async_xor_zero_sum\n\nFound-by: Yuri Tikhonov \u003cyur@emcraft.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "5554b35933245e95710d709175e14c02cbc956a4", "tree": "2eeb2f05a7061da3c9a3bc9ea69a344b990c6b49", "parents": [ "0f6e38a6381446eff5175b77d1094834a633a90f", "7f1b358a236ee9c19657a619ac6f2dcabcaa0924" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Jul 23 12:03:18 2008 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Jul 23 12:03:18 2008 -0700" }, "message": "Merge branch \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx\n\n* \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: (24 commits)\n I/OAT: I/OAT version 3.0 support\n I/OAT: tcp_dma_copybreak default value dependent on I/OAT version\n I/OAT: Add watchdog/reset functionality to ioatdma\n iop_adma: cleanup iop_chan_xor_slot_count\n iop_adma: document how to calculate the minimum descriptor pool size\n iop_adma: directly reclaim descriptors on allocation failure\n async_tx: make async_tx_test_ack a boolean routine\n async_tx: remove depend_tx from async_tx_sync_epilog\n async_tx: export async_tx_quiesce\n async_tx: fix handling of the \"out of descriptor\" condition in async_xor\n async_tx: ensure the xor destination buffer remains dma-mapped\n async_tx: list_for_each_entry_rcu() cleanup\n dmaengine: Driver for the Synopsys DesignWare DMA controller\n dmaengine: Add slave DMA interface\n dmaengine: add DMA_COMPL_SKIP_{SRC,DEST}_UNMAP flags to control dma unmap\n dmaengine: Add dma_client parameter to device_alloc_chan_resources\n dmatest: Simple DMA memcpy test client\n dmaengine: DMA engine driver for Marvell XOR engine\n iop-adma: fix platform driver hotplug/coldplug\n dmaengine: track the number of clients using a channel\n ...\n\nFixed up conflict in drivers/dca/dca-sysfs.c manually\n" }, { "commit": "3dce01713723bbcc92562bd4488e8b840a4f786c", "tree": "7e0720179ad4240b993f86f558a3efa8861f1033", "parents": [ "d2c52b7983b95bb3fc2a784e479f832f142d4523" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Jul 17 17:59:55 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Jul 17 17:59:55 2008 -0700" }, "message": "async_tx: remove depend_tx from async_tx_sync_epilog\n\nAll callers of async_tx_sync_epilog have called async_tx_quiesce on the\ndepend_tx, so async_tx_sync_epilog need only call the callback to\ncomplete the operation.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "d2c52b7983b95bb3fc2a784e479f832f142d4523", "tree": "7bc37e7438cee523496674adcd97034df764af47", "parents": [ "669ab0b210f9bd15d94d4d6a49ae13366a85e4da" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Jul 17 17:59:55 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Jul 17 17:59:55 2008 -0700" }, "message": "async_tx: export async_tx_quiesce\n\nReplace open coded \"wait and acknowledge\" instances with async_tx_quiesce.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "669ab0b210f9bd15d94d4d6a49ae13366a85e4da", "tree": "ead561418e94def95c4d4b4512ae3c9a7888febe", "parents": [ "1e55db2d6bdef92abc981b68673564e63c80da4d" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Jul 17 17:59:55 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Jul 17 17:59:55 2008 -0700" }, "message": "async_tx: fix handling of the \"out of descriptor\" condition in async_xor\n\nEnsure forward progress is made when a dmaengine driver is unable to\nallocate an xor descriptor by breaking the dependency chain with\nasync_tx_quisce() and issue any pending descriptors.\n\nTested with iop-adma by setting device-\u003emax_xor \u003d 2 to force multiple\ncalls to device_prep_dma_xor for each call to async_xor and limiting the\ndescriptor slot pool to 5. Discovered that the minimum descriptor pool\nsize for iop-adma is 2 * iop_chan_xor_slot_cnt(device-\u003emax_xor) + 1.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "1e55db2d6bdef92abc981b68673564e63c80da4d", "tree": "ac3cd7c249735772df8c08b1d803563bad854527", "parents": [ "20fc190b0ef58bf8b3b0bff9de122083956f82ec" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Jul 16 19:44:56 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Jul 17 17:59:55 2008 -0700" }, "message": "async_tx: ensure the xor destination buffer remains dma-mapped\n\nWhen the number of source buffers for an xor operation exceeds the hardware\nchannel maximum async_xor creates a chain of dependent operations. The result\nof one operation is reused as an input to the next to continue the xor\ncalculation. The destination buffer should remain mapped for the duration of\nthe entire chain. To provide this guarantee the code must no longer be allowed\nto fallback to the synchronous path as this will preclude the buffer from being\nunmapped, i.e. the dma-driver will potentially miss the descriptor with\n!DMA_COMPL_SKIP_DEST_UNMAP.\n\nCc: Neil Brown \u003cneilb@suse.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "20fc190b0ef58bf8b3b0bff9de122083956f82ec", "tree": "81512548e0f7b74b2f96b664e389fda5d9fad29a", "parents": [ "3bfb1d20b547a5071d01344581eac5846ea84491" ], "author": { "name": "Li Zefan", "email": "lizf@cn.fujitsu.com", "time": "Thu Jul 17 17:59:47 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Jul 17 17:59:47 2008 -0700" }, "message": "async_tx: list_for_each_entry_rcu() cleanup\n\nIn the rcu update side, don\u0027t use list_for_each_entry_rcu().\n\nSigned-off-by: Li Zefan \u003clizf@cn.fujitsu.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "65bc3ffe8c067e387fe5557bc3ea5071071f6af9", "tree": "71d7eb925b020a6e45d8d1a4047b961df34cff97", "parents": [ "51ee87f27a1d2c0e08492924f2fb0223c4c704d9" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Jun 05 23:26:11 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 08 11:57:55 2008 -0700" }, "message": "async_tx: fix async_memset compile error\n\ncommit 636bdeaa \u0027dmaengine: ack to flags: make use of the unused bits in\nthe \u0027ack\u0027 field\u0027 missed an -\u003eack conversion in\ncrypto/async_tx/async_memset.c\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "82524746c27fa418c250a56dd7606b9d3fc79826", "tree": "1801230b8fc2e436e722ac6f54fc53f1c112c310", "parents": [ "32300751b4079cb5688453baa94711579d4285d5" ], "author": { "name": "Franck Bui-Huu", "email": "fbuihuu@gmail.com", "time": "Mon May 12 21:21:05 2008 +0200" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Mon May 19 10:01:37 2008 +0200" }, "message": "rcu: split list.h and move rcu-protected lists into rculist.h\n\nMove rcu-protected lists from list.h into a new header file rculist.h.\n\nThis is done because list are a very used primitive structure all over the\nkernel and it\u0027s currently impossible to include other header files in this\nlist.h without creating some circular dependencies.\n\nFor example, list.h implements rcu-protected list and uses rcu_dereference()\nwithout including rcupdate.h. It actually compiles because users of\nrcu_dereference() are macros. Others RCU functions could be used too but\naren\u0027t probably because of this.\n\nTherefore this patch creates rculist.h which includes rcupdates without to\nmany changes/troubles.\n\nSigned-off-by: Franck Bui-Huu \u003cfbuihuu@gmail.com\u003e\nAcked-by: Paul E. McKenney \u003cpaulmck@linux.vnet.ibm.com\u003e\nAcked-by: Josh Triplett \u003cjosh@kernel.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "636bdeaa1243327501edfd2a597ed7443eb4239a", "tree": "59b894f124e3664ea4a537d7c07c527abdb9c8da", "parents": [ "c4fe15541d0ef5cc8cc1ce43057663851f8fc387" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Apr 17 20:17:26 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Apr 17 13:25:54 2008 -0700" }, "message": "dmaengine: ack to flags: make use of the unused bits in the \u0027ack\u0027 field\n\n\u0027ack\u0027 is currently a simple integer that flags whether or not a client is done\ntouching fields in the given descriptor. It is effectively just a single bit\nof information. Converting this to a flags parameter allows the other bits to\nbe put to use to control completion actions, like dma-unmap, and capture\nresults, like xor-zero-sum \u003d\u003d 0.\n\nChanges are one of:\n1/ convert all open-coded -\u003eack manipulations to use async_tx_ack\n and async_tx_test_ack.\n2/ set the ack bit at prep time where possible\n3/ make drivers store the flags at prep time\n4/ add flags to the device_prep_dma_interrupt prototype\n\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "19242d7233df7d658405d4b7ee1758d21414cfaa", "tree": "4bffa2700c30fdb454dfa150115a0607c6cf3d2a", "parents": [ "1c62979ed29a8e2bf9fbe1db101c81a0089676f8" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Apr 17 20:17:25 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Apr 17 13:25:05 2008 -0700" }, "message": "async_tx: fix multiple dependency submission\n\nShrink struct dma_async_tx_descriptor and introduce\nasync_tx_channel_switch to properly inject a channel switch interrupt in\nthe descriptor stream. This simplifies the locking model as drivers no\nlonger need to handle dma_async_tx_descriptor.lock.\n\nAcked-by: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "8d8002f642886ae256a3c5d70fe8aff4faf3631a", "tree": "81a3df533e7a0ad2d268b28fba1507e770df0f55", "parents": [ "f79abb627f033c85a6088231f20c85bc4a9bd757" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Mar 18 21:23:59 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Mar 18 17:01:00 2008 -0700" }, "message": "async_tx: avoid the async xor_zero_sum path when src_cnt \u003e device-\u003emax_xor\n\nIf the channel cannot perform the operation in one call to\n-\u003edevice_prep_dma_zero_sum, then fallback to the xor+page_is_zero path.\nThis only affects users with arrays larger than 16 devices on iop13xx or\n32 devices on iop3xx.\n\nCc: \u003cstable@kernel.org\u003e\nCc: Neil Brown \u003cneilb@suse.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "3280ab3e8815d60cea483d49b21261972e2785d6", "tree": "6f74b532ce482fc8bcdb0fdbca3a823053b6cc37", "parents": [ "3d9b525b69bc3302d8355e5f5cf081a856c211e0" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Mar 13 17:45:28 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Mar 13 10:57:10 2008 -0700" }, "message": "async_tx: checkpatch says s/__FUNCTION__/__func__/g\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "47437b2c9a64315efeb3d84e97ffefd6c3c67ef1", "tree": "e0dec7b29bebb0a2113f143576d940c571869aa0", "parents": [ "d4c56f97ff21df405d0cebe11f49e3c3c79662b5" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Feb 02 19:49:59 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Feb 06 10:12:18 2008 -0700" }, "message": "async_tx: allow architecture specific async_tx_find_channel implementations\n\nThe source and destination addresses are included to allow channel\nselection based on address alignment.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nReviewed-by: Haavard Skinnemoen \u003chskinnemoen@atmel.com\u003e\n" }, { "commit": "d4c56f97ff21df405d0cebe11f49e3c3c79662b5", "tree": "e6b0de433d7c985982ac12815998242a786d87b2", "parents": [ "0036731c88fdb5bf4f04a796a30b5e445fc57f54" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Feb 02 19:49:58 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Feb 06 10:12:18 2008 -0700" }, "message": "async_tx: replace \u0027int_en\u0027 with operation preparation flags\n\nPass a full set of flags to drivers\u0027 per-operation \u0027prep\u0027 routines.\nCurrently the only flag passed is DMA_PREP_INTERRUPT. The expectation is\nthat arch-specific async_tx_find_channel() implementations can exploit this\ncapability to find the best channel for an operation.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nAcked-by: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\nReviewed-by: Haavard Skinnemoen \u003chskinnemoen@atmel.com\u003e\n" }, { "commit": "0036731c88fdb5bf4f04a796a30b5e445fc57f54", "tree": "66982e4a9fdb92fedadca35c0ccaa0b9a75e9d2e", "parents": [ "d909b347591a23c5a2c324fbccd4c9c966f31c67" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Feb 02 19:49:57 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Feb 06 10:12:17 2008 -0700" }, "message": "async_tx: kill tx_set_src and tx_set_dest methods\n\nThe tx_set_src and tx_set_dest methods were originally implemented to allow\nan array of addresses to be passed down from async_xor to the dmaengine\ndriver while minimizing stack overhead. Removing these methods allows\ndrivers to have all transaction parameters available at \u0027prep\u0027 time, saves\ntwo function pointers in struct dma_async_tx_descriptor, and reduces the\nnumber of indirect branches..\n\nA consequence of moving this data to the \u0027prep\u0027 routine is that\nmulti-source routines like async_xor need temporary storage to convert an\narray of linear addresses into an array of dma addresses. In order to keep\nthe same stack footprint of the previous implementation the input array is\nreused as storage for the dma addresses. This requires that\nsizeof(dma_addr_t) be less than or equal to sizeof(void *). As a\nconsequence CONFIG_DMADEVICES now depends on !CONFIG_HIGHMEM64G. It also\nrequires that drivers be able to make descriptor resources available when\nthe \u0027prep\u0027 routine is polled.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nAcked-by: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\n" }, { "commit": "d909b347591a23c5a2c324fbccd4c9c966f31c67", "tree": "1092bfdc2722eed041a29752a62836366855c30a", "parents": [ "e73ef9acfd30f36bf7c60237ecffe7bbca8068d6" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Feb 02 19:30:14 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Feb 06 10:12:17 2008 -0700" }, "message": "async_tx: kill ASYNC_TX_ASSUME_COHERENT\n\nRemove the unused ASYNC_TX_ASSUME_COHERENT flag. Async_tx is\nmeant to hide the difference between asynchronous hardware and synchronous\nsoftware operations, this flag requires clients to understand cache\ncoherency consequences of the async path.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nReviewed-by: Haavard Skinnemoen \u003chskinnemoen@atmel.com\u003e\n" }, { "commit": "cf8f68aa76e8e12f9dcbba3ffe61fb9f2a3a0c2b", "tree": "f53fa3040cfd8fcc47eb8aaed60a0a79181cd9b2", "parents": [ "1367a3d310afc1ce758c8b94a0dc77834b4494a0" ], "author": { "name": "Denis Cheng", "email": "crquan@gmail.com", "time": "Sat Feb 02 19:29:58 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Feb 06 10:12:17 2008 -0700" }, "message": "async_tx: use LIST_HEAD instead of LIST_HEAD_INIT\n\nsingle list_head variable initialized with LIST_HEAD_INIT could almost\nalways can be replaced with LIST_HEAD declaration, this shrinks the code\nand looks better.\n\nSigned-off-by: Denis Cheng \u003ccrquan@gmail.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "1367a3d310afc1ce758c8b94a0dc77834b4494a0", "tree": "cf6938c1662074f26ee16ff02d3c38332bc010ef", "parents": [ "551e4fb2465b87de9d4aa1669b27d624435443bb" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Feb 02 18:46:43 2008 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Feb 06 10:12:17 2008 -0700" }, "message": "async_tx: fix compile breakage, mark do_async_xor __always_inline\n\ndo_async_xor must be compiled away on !HAS_DMA archs.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nAcked-by: Cornelia Huck \u003ccornelia.huck@de.ibm.com\u003e\n" }, { "commit": "6247cdc2cd334dad0ea5428245a7d8f4b075f21e", "tree": "275bfcdb142a92ea347d264b6b37b17c98d41733", "parents": [ "c5d2b9f444b8d9f5ad7c5e583686c119ba3a9ba7" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Sep 21 13:27:04 2007 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Sep 24 10:26:26 2007 -0700" }, "message": "async_tx: fix dma_wait_for_async_tx\n\nFix dma_wait_for_async_tx to not loop forever in the case where a\ndependency chain is longer than two entries. This condition will not\nhappen with current in-kernel drivers, but fix it for future drivers.\n\nFound-by: Saeed Bishara \u003csaeed.bishara@gmail.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "eb0645a8b1f14da300f40bb9f424640cd1181fbf", "tree": "462789626fcd1775bec80d74d19bcd68797589c8", "parents": [ "7c6129c68fe90a61166800b40217a850b8faee98" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Jul 20 00:31:46 2007 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Fri Jul 20 08:44:19 2007 -0700" }, "message": "async_tx: fix kmap_atomic usage in async_memcpy\n\nAndrew Morton:\n\t[async_memcpy] is very wrong if both ASYNC_TX_KMAP_DST and\n\tASYNC_TX_KMAP_SRC can ever be set. We\u0027ll end up using the same kmap\n\tslot for both src add dest and we get either corrupted data or a BUG.\n\nEvgeniy Polyakov:\n\tBtw, shouldn\u0027t it always be kmap_atomic() even if flag is not set.\n\tThat pages are usual one returned by alloc_page().\n\nSo fix the usage of kmap_atomic and kill the ASYNC_TX_KMAP_DST and\nASYNC_TX_KMAP_SRC flags.\n\nCc: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nCc: Evgeniy Polyakov \u003cjohnpol@2ka.mipt.ru\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "9bc89cd82d6f88fb0ca39b30445c329a430fd66b", "tree": "7bd0e856abd359f84edea1bacfd1dd32edd93fbb", "parents": [ "685784aaf3cd0e3ff5e36c7ecf6f441cdbf57f73" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jan 02 11:10:44 2007 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Jul 13 08:06:14 2007 -0700" }, "message": "async_tx: add the async_tx api\n\nThe async_tx api provides methods for describing a chain of asynchronous\nbulk memory transfers/transforms with support for inter-transactional\ndependencies. It is implemented as a dmaengine client that smooths over\nthe details of different hardware offload engine implementations. Code\nthat is written to the api can optimize for asynchronous operation and the\napi will fit the chain of operations to the available offload resources. \n \n\tI imagine that any piece of ADMA hardware would register with the\n\t\u0027async_*\u0027 subsystem, and a call to async_X would be routed as\n\tappropriate, or be run in-line. - Neil Brown\n\nasync_tx exploits the capabilities of struct dma_async_tx_descriptor to\nprovide an api of the following general format:\n\nstruct dma_async_tx_descriptor *\nasync_\u003coperation\u003e(..., struct dma_async_tx_descriptor *depend_tx,\n\t\t\tdma_async_tx_callback cb_fn, void *cb_param)\n{\n\tstruct dma_chan *chan \u003d async_tx_find_channel(depend_tx, \u003coperation\u003e);\n\tstruct dma_device *device \u003d chan ? chan-\u003edevice : NULL;\n\tint int_en \u003d cb_fn ? 1 : 0;\n\tstruct dma_async_tx_descriptor *tx \u003d device ?\n\t\tdevice-\u003edevice_prep_dma_\u003coperation\u003e(chan, len, int_en) : NULL;\n\n\tif (tx) { /* run \u003coperation\u003e asynchronously */\n\t\t...\n\t\ttx-\u003etx_set_dest(addr, tx, index);\n\t\t...\n\t\ttx-\u003etx_set_src(addr, tx, index);\n\t\t...\n\t\tasync_tx_submit(chan, tx, flags, depend_tx, cb_fn, cb_param);\n\t} else { /* run \u003coperation\u003e synchronously */\n\t\t...\n\t\t\u003coperation\u003e\n\t\t...\n\t\tasync_tx_sync_epilog(flags, depend_tx, cb_fn, cb_param);\n\t}\n\n\treturn tx;\n}\n\nasync_tx_find_channel() returns a capable channel from its pool. The\nchannel pool is organized as a per-cpu array of channel pointers. The\nasync_tx_rebalance() routine is tasked with managing these arrays. In the\nuniprocessor case async_tx_rebalance() tries to spread responsibility\nevenly over channels of similar capabilities. For example if there are two\ncopy+xor channels, one will handle copy operations and the other will\nhandle xor. In the SMP case async_tx_rebalance() attempts to spread the\noperations evenly over the cpus, e.g. cpu0 gets copy channel0 and xor\nchannel0 while cpu1 gets copy channel 1 and xor channel 1. When a\ndependency is specified async_tx_find_channel defaults to keeping the\noperation on the same channel. A xor-\u003ecopy-\u003exor chain will stay on one\nchannel if it supports both operation types, otherwise the transaction will\ntransition between a copy and a xor resource.\n\nCurrently the raid5 implementation in the MD raid456 driver has been\nconverted to the async_tx api. A driver for the offload engines on the\nIntel Xscale series of I/O processors, iop-adma, is provided in a later\ncommit. With the iop-adma driver and async_tx, raid456 is able to offload\ncopy, xor, and xor-zero-sum operations to hardware engines.\n \nOn iop342 tiobench showed higher throughput for sequential writes (20 - 30%\nimprovement) and sequential reads to a degraded array (40 - 55%\nimprovement). For the other cases performance was roughly equal, +/- a few\npercentage points. On a x86-smp platform the performance of the async_tx\nimplementation (in synchronous mode) was also +/- a few percentage points\nof the original implementation. According to \u0027top\u0027 on iop342 CPU\nutilization drops from ~50% to ~15% during a \u0027resync\u0027 while the speed\naccording to /proc/mdstat doubles from ~25 MB/s to ~50 MB/s.\n \nThe tiobench command line used for testing was: tiobench --size 2048\n--block 4096 --block 131072 --dir /mnt/raid --numruns 5\n* iop342 had 1GB of memory available\n\nDetails:\n* if CONFIG_DMA_ENGINE\u003dn the asynchronous path is compiled away by making\n async_tx_find_channel a static inline routine that always returns NULL\n* when a callback is specified for a given transaction an interrupt will\n fire at operation completion time and the callback will occur in a\n tasklet. if the the channel does not support interrupts then a live\n polling wait will be performed\n* the api is written as a dmaengine client that requests all available\n channels\n* In support of dependencies the api implicitly schedules channel-switch\n interrupts. The interrupt triggers the cleanup tasklet which causes\n pending operations to be scheduled on the next channel\n* Xor engines treat an xor destination address differently than a software\n xor routine. To the software routine the destination address is an implied\n source, whereas engines treat it as a write-only destination. This patch\n modifies the xor_blocks routine to take a an explicit destination address\n to mirror the hardware.\n\nChangelog:\n* fixed a leftover debug print\n* don\u0027t allow callbacks in async_interrupt_cond\n* fixed xor_block changes\n* fixed usage of ASYNC_TX_XOR_DROP_DEST\n* drop dma mapping methods, suggested by Chris Leech\n* printk warning fixups from Andrew Morton\n* don\u0027t use inline in C files, Adrian Bunk\n* select the API when MD is enabled\n* BUG_ON xor source counts \u003c\u003d 1\n* implicitly handle hardware concerns like channel switching and\n interrupts, Neil Brown\n* remove the per operation type list, and distribute operation capabilities\n evenly amongst the available channels\n* simplify async_tx_find_channel to optimize the fast path\n* introduce the channel_table_initialized flag to prevent early calls to\n the api\n* reorganize the code to mimic crypto\n* include mm.h as not all archs include it in dma-mapping.h\n* make the Kconfig options non-user visible, Adrian Bunk\n* move async_tx under crypto since it is meant as \u0027core\u0027 functionality, and\n the two may share algorithms in the future\n* move large inline functions into c files\n* checkpatch.pl fixes\n* gpl v2 only correction\n\nCc: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nAcked-By: NeilBrown \u003cneilb@suse.de\u003e\n" } ] }