)]}' { "log": [ { "commit": "622a9edd919de98ef59571ae6c40c7458244e3f2", "tree": "c25684f90ed52c459c39d97d6ab641fe3bb6b09d", "parents": [ "bc154b1efb7f8430ea9faabd5953ebc411f8ead5" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Oct 16 23:29:42 2007 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Wed Oct 17 08:42:57 2007 -0700" }, "message": "Remove dma_cache_(wback|inv|wback_inv) functions\n\ndma_cache_(wback|inv|wback_inv) were the earliest attempt on a generalized\ncache managment API for I/O purposes. Originally it was basically the raw\nMIPS low level cache API exported to the entire world. The API has\nsuffered from a lack of documentation, was not very widely used unlike it\u0027s\nmore modern brothers and can easily be replaced by dma_cache_sync. So\nremove it rsp. turn the surviving bits back into an arch private API, as\ndiscussed on linux-arch.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\nAcked-by: Paul Mundt \u003clethal@linux-sh.org\u003e\nAcked-by: Paul Mackerras \u003cpaulus@samba.org\u003e\nAcked-by: David S. Miller \u003cdavem@davemloft.net\u003e\nAcked-by: Kyle McMartin \u003ckyle@parisc-linux.org\u003e\nAcked-by: Haavard Skinnemoen \u003chskinnemoen@atmel.com\u003e\nCc: \u003clinux-arch@vger.kernel.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "cca67164bbdb083df9adb6480822518b0f4b358f", "tree": "a4b951950a6f9dfb880d25d57a932760aa2032f1", "parents": [ "6f834197a79d34d65ca44e9c77f2571edbcfb64b" ], "author": { "name": "Haavard Skinnemoen", "email": "hskinnemoen@atmel.com", "time": "Mon Aug 13 16:24:01 2007 +0200" }, "committer": { "name": "Haavard Skinnemoen", "email": "hskinnemoen@atmel.com", "time": "Wed Aug 15 16:36:56 2007 +0200" }, "message": "[AVR32] Define mmiowb()\n\nAdd empty definition of mmiowb() since some drivers need it. Uncached\nwrites are strongly ordered on AVR32. They may be delayed if the\ndcache is busy doing a writeback, but AFAICT that\u0027s not what this\nmacro is supposed to deal with, at least on UP systems.\n\nWe might have to revisit this definition when a SMP-capable AVR32 CPU\ncomes along, depending on how the busses and cache coherency stuff\nend up being implemented.\n\nSigned-off-by: Haavard Skinnemoen \u003chskinnemoen@atmel.com\u003e\n" }, { "commit": "2c1a2a3441a754a9b5a8e7184071154f8a9bd61b", "tree": "a11527d9a32495d800c949e9616b82c5c25aba5f", "parents": [ "d80e2bb12606906fd0b5b5592f519852de8b0113" ], "author": { "name": "Haavard Skinnemoen", "email": "hskinnemoen@atmel.com", "time": "Wed Mar 07 10:40:44 2007 +0100" }, "committer": { "name": "Haavard Skinnemoen", "email": "hskinnemoen@atmel.com", "time": "Fri Apr 27 13:44:15 2007 +0200" }, "message": "[AVR32] Use memcpy/memset in memcpy_{from,to}_io and memset_io\n\nUsing readb/writeb to implement these breaks NOR flash support. I\ncan\u0027t see any reason why regular memcpy and memset shouldn\u0027t work.\n\nSigned-off-by: Haavard Skinnemoen \u003chskinnemoen@atmel.com\u003e\n" }, { "commit": "e3e7d8d4ea37b8372ee417452d03171c5dc55125", "tree": "247a899f472e5cf1a3f7467dda88a017bee134a6", "parents": [ "92b728c147adb8c690b520304f4c9ee3eee43c21" ], "author": { "name": "Haavard Skinnemoen", "email": "hskinnemoen@atmel.com", "time": "Mon Feb 12 16:28:56 2007 +0100" }, "committer": { "name": "Haavard Skinnemoen", "email": "hskinnemoen@atmel.com", "time": "Fri Apr 27 13:44:14 2007 +0200" }, "message": "[AVR32] Make I/O access macros work with external devices\n\nFix the I/O access macros so that they work with externally connected\ndevices accessed in little-endian mode over any bus width:\n\n* Use a set of macros to define I/O port- and memory operations\n borrowed from MIPS.\n* Allow subarchitecture to specify address- and data-mangling\n* Implement at32ap-specific port mangling (with build-time\n configurable bus width. Only one bus width at a time supported\n for now.)\n* Rewrite iowriteN and friends to use write[bwl] and friends\n (not the __raw counterparts.)\n\nThis has been tested using pata_pcmcia to access a CompactFlash card\nconnected to the EBI (16-bit bus width.)\n\nSigned-off-by: Haavard Skinnemoen \u003chskinnemoen@atmel.com\u003e\n" }, { "commit": "2201ec2b10910c869befb012ae75696a02091e7d", "tree": "c885f996671bc6ca72933acf6d75a7700e5cb676", "parents": [ "b60f16eb56ff872a86c55c11bcfd430ce8cec340" ], "author": { "name": "Haavard Skinnemoen", "email": "hskinnemoen@atmel.com", "time": "Fri Feb 16 12:53:57 2007 +0100" }, "committer": { "name": "Haavard Skinnemoen", "email": "hskinnemoen@atmel.com", "time": "Fri Feb 16 12:53:57 2007 +0100" }, "message": "[AVR32] Define ioremap_nocache, ioport_map and ioport_unmap\n\nThese are all defined in terms of ioremap/iounmap since port I/O\nisn\u0027t really different from memory-mapped I/O on AVR32.\n\nSigned-off-by: Haavard Skinnemoen \u003chskinnemoen@atmel.com\u003e\n" }, { "commit": "b60f16eb56ff872a86c55c11bcfd430ce8cec340", "tree": "315e4a24916e9c3a932d3c2ee518c958ca69519d", "parents": [ "7de970e11fb832a56c897276967fb0e49f59b313" ], "author": { "name": "Haavard Skinnemoen", "email": "hskinnemoen@atmel.com", "time": "Fri Feb 16 12:47:40 2007 +0100" }, "committer": { "name": "Haavard Skinnemoen", "email": "hskinnemoen@atmel.com", "time": "Fri Feb 16 12:47:40 2007 +0100" }, "message": "[AVR32] Fix prototypes for __raw_writesb and friends\n\nThe first parameter to __raw_writes[bwl] and __raw_reads[bwl] should\nbe a void __iomem *, not unsigned long.\n\nSigned-off-by: Haavard Skinnemoen \u003chskinnemoen@atmel.com\u003e\n" }, { "commit": "065834ab3988fece5608088e83724891c8190a2f", "tree": "53f4f4abf61ea228c2a78ca7de9e44642ab3c124", "parents": [ "fa3522407f01ead1ec14bdd6b785ea08d17d500d" ], "author": { "name": "Ben Nizette", "email": "ben@mallochdigital.com", "time": "Tue Oct 24 10:12:43 2006 +0200" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Wed Oct 25 20:26:33 2006 -0700" }, "message": "[PATCH] AVR32: add io{read,write}{8,16,32}{be,} support\n\nA number of new drivers require io{read,write}{8,16,32}{be,} family of io\noperations. These are provided for the AVR32 by this patch in the form of\na series of macros.\n\nAccess to the (memory mapped) io space through these macros is defined to\nbe little endian only as little endian devices (such as PCI) are the main\nconsumer of IO access. If high speed access is required,\nio{read,write}{16,32}be macros are supplied to perform native big endian\naccess to this io space.\n\nSigned-off-by: Ben Nizette \u003cben@mallochdigital.com\u003e\nSigned-off-by: Haavard Skinnemoen \u003chskinnemoen@atmel.com\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" }, { "commit": "5f97f7f9400de47ae837170bb274e90ad3934386", "tree": "514451e6dc6b46253293a00035d375e77b1c65ed", "parents": [ "53e62d3aaa60590d4a69b4e07c29f448b5151047" ], "author": { "name": "Haavard Skinnemoen", "email": "hskinnemoen@atmel.com", "time": "Mon Sep 25 23:32:13 2006 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@g5.osdl.org", "time": "Tue Sep 26 08:48:54 2006 -0700" }, "message": "[PATCH] avr32 architecture\n\nThis adds support for the Atmel AVR32 architecture as well as the AT32AP7000\nCPU and the AT32STK1000 development board.\n\nAVR32 is a new high-performance 32-bit RISC microprocessor core, designed for\ncost-sensitive embedded applications, with particular emphasis on low power\nconsumption and high code density. The AVR32 architecture is not binary\ncompatible with earlier 8-bit AVR architectures.\n\nThe AVR32 architecture, including the instruction set, is described by the\nAVR32 Architecture Manual, available from\n\nhttp://www.atmel.com/dyn/resources/prod_documents/doc32000.pdf\n\nThe Atmel AT32AP7000 is the first CPU implementing the AVR32 architecture. It\nfeatures a 7-stage pipeline, 16KB instruction and data caches and a full\nMemory Management Unit. It also comes with a large set of integrated\nperipherals, many of which are shared with the AT91 ARM-based controllers from\nAtmel.\n\nFull data sheet is available from\n\nhttp://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf\n\nwhile the CPU core implementation including caches and MMU is documented by\nthe AVR32 AP Technical Reference, available from\n\nhttp://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf\n\nInformation about the AT32STK1000 development board can be found at\n\nhttp://www.atmel.com/dyn/products/tools_card.asp?tool_id\u003d3918\n\nincluding a BSP CD image with an earlier version of this patch, development\ntools (binaries and source/patches) and a root filesystem image suitable for\nbooting from SD card.\n\nAlternatively, there\u0027s a preliminary \"getting started\" guide available at\nhttp://avr32linux.org/twiki/bin/view/Main/GettingStarted which provides links\nto the sources and patches you will need in order to set up a cross-compiling\nenvironment for avr32-linux.\n\nThis patch, as well as the other patches included with the BSP and the\ntoolchain patches, is actively supported by Atmel Corporation.\n\n[dmccr@us.ibm.com: Fix more pxx_page macro locations]\n[bunk@stusta.de: fix `make defconfig\u0027]\nSigned-off-by: Haavard Skinnemoen \u003chskinnemoen@atmel.com\u003e\nSigned-off-by: Adrian Bunk \u003cbunk@stusta.de\u003e\nSigned-off-by: Dave McCracken \u003cdmccr@us.ibm.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n" } ] }