)]}'
{
  "log": [
    {
      "commit": "9e83b98a79d25136282a1757f879c40ee929a28b",
      "tree": "1ec7588320b7e95f05eab8b2f9a06c07f48034bc",
      "parents": [
        "b5f87aa41db4d5cd64ca77f10b33fdfba61a47d7"
      ],
      "author": {
        "name": "Mike Frysinger",
        "email": "michael.frysinger@analog.com",
        "time": "Wed Nov 21 16:08:58 2007 +0800"
      },
      "committer": {
        "name": "Bryan Wu",
        "email": "bryan.wu@analog.com",
        "time": "Wed Nov 21 16:08:58 2007 +0800"
      },
      "message": "Blackfin arch: add support for working around anomaly 05000312\n\nAnomaly 05000312 - Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted:\n\nDESCRIPTION:\nWhen instruction cache is enabled, erroneous behavior may occur when any of the following instructions are interrupted:\n\n. CSYNC\n• SSYNC\n• LCx \u003d\n• LTx \u003d (only when LCx is non-zero)\n• LBx \u003d (only when LCx is non-zero)\n\nWhen this problem occurs, a variety of incorrect things could happen, including an illegal instruction exception. Additional errors could\nshow up as an exception, a hardware error, or an instruction that is valid but different than the one that was expected.\n\nWORKAROUND:\nPlace a cli before all SSYNC, CSYNC, \"LCx \u003d\", \"LTx \u003d\", and \"LBx \u003d\" instructions to disable interrupts, and place an sti after each of these\ninstructions to re-enable interrupts. When these instructions are executed in code that is already non-interruptible, the problem will not\noccur.\n\nSigned-off-by: Mike Frysinger \u003cmichael.frysinger@analog.com\u003e\nSigned-off-by: Bryan Wu \u003cbryan.wu@analog.com\u003e\n\n"
    },
    {
      "commit": "1394f03221790a988afc3e4b3cb79f2e477246a9",
      "tree": "2c1963c9a4f2d84a5e021307fde240c5d567cf70",
      "parents": [
        "73243284463a761e04d69d22c7516b2be7de096c"
      ],
      "author": {
        "name": "Bryan Wu",
        "email": "bryan.wu@analog.com",
        "time": "Sun May 06 14:50:22 2007 -0700"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@woody.linux-foundation.org",
        "time": "Mon May 07 12:12:58 2007 -0700"
      },
      "message": "blackfin architecture\n\nThis adds support for the Analog Devices Blackfin processor architecture, and\ncurrently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561\n(Dual Core) devices, with a variety of development platforms including those\navaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,\nBF561-EZKIT), and Bluetechnix!  Tinyboards.\n\nThe Blackfin architecture was jointly developed by Intel and Analog Devices\nInc.  (ADI) as the Micro Signal Architecture (MSA) core and introduced it in\nDecember of 2000.  Since then ADI has put this core into its Blackfin\nprocessor family of devices.  The Blackfin core has the advantages of a clean,\northogonal,RISC-like microprocessor instruction set.  It combines a dual-MAC\n(Multiply/Accumulate), state-of-the-art signal processing engine and\nsingle-instruction, multiple-data (SIMD) multimedia capabilities into a single\ninstruction-set architecture.\n\nThe Blackfin architecture, including the instruction set, is described by the\nADSP-BF53x/BF56x Blackfin Processor Programming Reference\nhttp://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf\n\nThe Blackfin processor is already supported by major releases of gcc, and\nthere are binary and source rpms/tarballs for many architectures at:\nhttp://blackfin.uclinux.org/gf/project/toolchain/frs There is complete\ndocumentation, including \"getting started\" guides available at:\nhttp://docs.blackfin.uclinux.org/ which provides links to the sources and\npatches you will need in order to set up a cross-compiling environment for\nbfin-linux-uclibc\n\nThis patch, as well as the other patches (toolchain, distribution,\nuClibc) are actively supported by Analog Devices Inc, at:\nhttp://blackfin.uclinux.org/\n\nWe have tested this on LTP, and our test plan (including pass/fails) can\nbe found at:\nhttp://docs.blackfin.uclinux.org/doku.php?id\u003dtesting_the_linux_kernel\n\n[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]\nSigned-off-by: Bryan Wu \u003cbryan.wu@analog.com\u003e\nSigned-off-by: Mariusz Kozlowski \u003cm.kozlowski@tuxland.pl\u003e\nSigned-off-by: Aubrey Li \u003caubrey.li@analog.com\u003e\nSigned-off-by: Jie Zhang \u003cjie.zhang@analog.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n"
    }
  ]
}