)]}' { "log": [ { "commit": "734c2992828c66cee3feb21ecd30a6ac44aecc51", "tree": "c732007f463393046dc83cc3d6b5953cb076aa32", "parents": [ "8f98781e0f15207b6ab33bee1fae05428be0475b" ], "author": { "name": "Julia Lawall", "email": "julia@diku.dk", "time": "Sat Feb 06 09:43:41 2010 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Feb 10 12:07:28 2010 -0700" }, "message": "drivers/dma: Correct NULL test\n\ncohd_fin has already been verified not to be NULL, so the argument to\nBUG_ON cannot be true.\n\nA simplified version of the semantic match that finds this problem is as\nfollows: (http://coccinelle.lip6.fr/)\n\n// \u003csmpl\u003e\n@r@\nexpression *x;\nexpression e;\nidentifier l;\n@@\n\nif (x \u003d\u003d NULL || ...) {\n ... when forall\n return ...; }\n... when !\u003d goto l;\n when !\u003d x \u003d e\n when !\u003d \u0026x\n*x \u003d\u003d NULL\n// \u003c/smpl\u003e\n\nSigned-off-by: Julia Lawall \u003cjulia@diku.dk\u003e\nAcked-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "8f98781e0f15207b6ab33bee1fae05428be0475b", "tree": "31830720fd57bd11191e85bbdc98eaefe061f127", "parents": [ "b953df7c70740cd7593072ebec77a8f658505630" ], "author": { "name": "Guennadi Liakhovetski", "email": "g.liakhovetski@gmx.de", "time": "Wed Feb 10 17:32:38 2010 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Feb 10 12:01:06 2010 -0700" }, "message": "async-tx: fix buffer submission error handling in ipu_idma.c\n\nIf submitting new buffer failed, a wrong descriptor gets completed and it\ndoesn\u0027t check, if a callback is at all defined, which can lead to an Oops. Fix\nthese bugs and make ipu_update_channel_buffer() void, because it never fails.\n\nSigned-off-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "b953df7c70740cd7593072ebec77a8f658505630", "tree": "3f831c33f2b1a0173e7142226869dababcd16422", "parents": [ "7e55a70c5b9a57c12f49c44b0847c9343d4f54e4" ], "author": { "name": "Yong Zhang", "email": "yong.zhang0@gmail.com", "time": "Fri Feb 05 21:52:37 2010 +0800" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Feb 05 15:35:53 2010 -0700" }, "message": "dmaengine: correct onstack wait_queue_head declaration\n\nUse DECLARE_WAIT_QUEUE_HEAD_ONSTACK to make lockdep happy\n\nSigned-off-by: Yong Zhang \u003cyong.zhang0@gmail.com\u003e\nCc: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nCc: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nCc: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "7e55a70c5b9a57c12f49c44b0847c9343d4f54e4", "tree": "e9ba9f5896d8e97e76894f23641afd3abce5aac4", "parents": [ "adef477268ff5ddd0195611dc7e26d7a879fefe1" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Jan 13 13:33:12 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Feb 02 22:57:34 2010 -0700" }, "message": "ioat: fix infinite timeout checking in ioat2_quiesce\n\nFix typo in ioat2_quiesce. check \u0027tmo\u0027 is zero, not \u0027end\u0027. Also applies\nto 2.6.32.3\n\nCc: \u003cstable@kernel.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "adef477268ff5ddd0195611dc7e26d7a879fefe1", "tree": "ad7b36a817f5f045719b28ade67914a2ce775d5c", "parents": [ "abe94c756c08d50566c09a65b9c7fe72f83071c5" ], "author": { "name": "Anatolij Gustschin", "email": "agust@denx.de", "time": "Tue Jan 26 10:26:06 2010 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Feb 02 14:58:37 2010 -0700" }, "message": "dmaengine: fix memleak in dma_async_device_unregister\n\nWhile debugging a dma driver I noticed a memleak after\nunloading the driver module.\n\nCaught by kmemleak.\n\nSigned-off-by: Anatolij Gustschin \u003cagust@denx.de\u003e\nCc: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "05a625486efc3209ae4d98e253dafa6ce0124385", "tree": "b78b4a854639fecc91598ecb05900c929a6ab85e", "parents": [ "1f11abc966b82b9fd0c834707486ef301b2f398d", "f80ca163d65903276bec7045a484a79c0897eb2d" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Dec 30 13:46:29 2009 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Dec 30 13:46:29 2009 -0800" }, "message": "Merge branch \u0027fixes\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx\n\n* \u0027fixes\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx:\n drivers/dma: Correct use after free\n drivers/dma: drop unnecesary memset\n ioat2,3: put channel hardware in known state at init\n async_tx: expand async raid6 test to cover ioatdma corner case\n ioat3: fix p-disabled q-continuation\n sh: fix DMA driver\u0027s descriptor chaining and cookie assignment\n dma: at_hdmac: correct incompatible type for argument 1 of \u0027spin_lock_bh\u0027\n" }, { "commit": "f80ca163d65903276bec7045a484a79c0897eb2d", "tree": "97c7d61d43248b9db0757a76af80ff58b98b5599", "parents": [ "0794ec8ce327ec74416b569b8fb1951274693700", "a6d52d70677e99bdb89b6921c265d0a58c22e597" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Dec 22 17:21:47 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Dec 22 17:21:47 2009 -0700" }, "message": "Merge branch \u0027ioat\u0027 into fixes\n" }, { "commit": "0794ec8ce327ec74416b569b8fb1951274693700", "tree": "4e6a59cdf0c13005d22165932b82acf1213bc937", "parents": [ "1e9d1b13efae7e0a2705611d47ae5f07e27015f0" ], "author": { "name": "Julia Lawall", "email": "julia@diku.dk", "time": "Tue Dec 22 21:30:59 2009 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Dec 22 15:30:08 2009 -0700" }, "message": "drivers/dma: Correct use after free\n\nMove the kfree after the iounmap that refers to the same structure.\n\nA simplified version of the semantic match that finds this problem is as\nfollows: (http://coccinelle.lip6.fr/)\n\n// \u003csmpl\u003e\n@@\nexpression x,e;\nidentifier f;\niterator I;\nstatement S;\n@@\n\n*kfree(x);\n... when !\u003d \u0026x\n when !\u003d x \u003d e\n when !\u003d I(x,...) S\n*x-\u003ef\n// \u003c/smpl\u003e\n\nSigned-off-by: Julia Lawall \u003cjulia@diku.dk\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "1e9d1b13efae7e0a2705611d47ae5f07e27015f0", "tree": "bb5f9eed3636080b2dc8a4791d03b812e65a6786", "parents": [ "3542a113ab2f5880f1b62e5909d754250fb57d6b" ], "author": { "name": "Julia Lawall", "email": "julia@diku.dk", "time": "Sat Dec 19 08:30:30 2009 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Dec 22 15:29:05 2009 -0700" }, "message": "drivers/dma: drop unnecesary memset\n\nmemset of 0 is not needed after kzalloc\n\nThe semantic patch that makes this change is as follows:\n(http://coccinelle.lip6.fr/)\n\n// \u003csmpl\u003e\n@@\nexpression x;\nstatement S;\n@@\n\nx \u003d kzalloc(...);\nif (x \u003d\u003d NULL) S\n... when !\u003d x\n-memset(x,0,...);// \u003c/smpl\u003e\n\nSigned-off-by: Julia Lawall \u003cjulia@diku.dk\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "a6d52d70677e99bdb89b6921c265d0a58c22e597", "tree": "9310005efbfa5d3141c1bf9d9ed5464377419f1e", "parents": [ "e02a0e47a3f061c1a53fc4376332a988ec047e8a" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Dec 19 15:36:02 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Dec 19 15:36:02 2009 -0700" }, "message": "ioat2,3: put channel hardware in known state at init\n\nPut the ioat2 and ioat3 state machines in the halted state with all\nerrors cleared.\n\nThe ioat1 init path is not disturbed for stability, there are no\nreported ioat1 initiaization issues.\n\nCc: \u003cstable@kernel.org\u003e\nReported-by: Roland Dreier \u003crdreier@cisco.com\u003e\nTested-by: Roland Dreier \u003crdreier@cisco.com\u003e\nAcked-by: Simon Horman \u003chorms@verge.net.au\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "cd78809f6191485a90ea6c92c2b58900ab5c156f", "tree": "d17a0e30178ec8ae78e04df69ca3d7b280054361", "parents": [ "22763c5cf3690a681551162c15d34d935308c8d7" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Dec 17 13:52:39 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Dec 17 13:52:39 2009 -0700" }, "message": "ioat3: fix p-disabled q-continuation\n\nWhen continuing a pq calculation the driver needs 3 extra sources. The\ndriver can perform a 3 source calculation with a single descriptor, but\nneeds an extended descriptor to process up to 8 sources in one\noperation. However, in the p-disabled case only one extra source is\nneeded. When continuing a p-disabled operation there are occasions\n(i.e. 0 \u003c src_cnt % 8 \u003c 3) where the tail operation does not need an\nextended descriptor. Properly account for this fact otherwise invalid\n\u0027dmacount\u0027 values will be written to hardware usually causing the\nchannel to halt with \u0027invalid descriptor\u0027 errors.\n\nCc: \u003cstable@kernel.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "3542a113ab2f5880f1b62e5909d754250fb57d6b", "tree": "30359d2425678ccc84b62c055c19e943a300ecf6", "parents": [ "4297a462f455e38f08976df7b16c849614a287da" ], "author": { "name": "Guennadi Liakhovetski", "email": "g.liakhovetski@gmx.de", "time": "Thu Dec 17 09:41:39 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Dec 17 09:41:39 2009 -0700" }, "message": "sh: fix DMA driver\u0027s descriptor chaining and cookie assignment\n\nThe SH DMA driver wrongly assigns negative cookies to transfer descriptors,\nalso, its chaining of partial descriptors is broken. The latter problem is\nusually invisible, because maximum transfer size per chunk is 16M, but if you\nartificially set this limit lower, the driver fails. Since cookies are also\nused in chunk management, both these problems are fixed in one patch. As side\neffects a possible memory leak, when descriptors are prepared, but not\nsubmitted, and multiple races have also been fixed.\n\nSigned-off-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nAcked-by: Paul Mundt \u003clethal@linux-sh.org\u003e\nAcked-by: Nobuhiro Iwamatsu \u003ciwamatsu@nigauri.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "7949456b1b96924c2d9ae5aea5fa7d4c81c946ed", "tree": "819e64dcd686c8b53c698c164aea96a002e8b5f8", "parents": [ "60d9aa758c00f20ade0cb1951f6a934f628dd2d7", "12458ea06efd7b44281e68fe59c950ec7d59c649" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Dec 16 10:28:56 2009 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Dec 16 10:28:56 2009 -0800" }, "message": "Merge branch \u0027next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx\n\n* \u0027next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx:\n ppc440spe-adma: adds updated ppc440spe adma driver\n iop-adma.c: use resource_size()\n dmaengine: clarify the meaning of the DMA_CTRL_ACK flag\n sh: stylistic improvements for the DMA driver\n dmaengine: fix dmatest to verify minimum transfer length and test buffer size\n sh: DMA driver has to specify its alignment requirements\n Add COH 901 318 DMA block driver v5\n" }, { "commit": "4297a462f455e38f08976df7b16c849614a287da", "tree": "0c488ff750a68ad4058fdc77561a5392f71877d0", "parents": [ "12458ea06efd7b44281e68fe59c950ec7d59c649" ], "author": { "name": "Nicolas Ferre", "email": "nicolas.ferre@atmel.com", "time": "Wed Dec 16 16:28:03 2009 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Dec 16 11:21:48 2009 -0700" }, "message": "dma: at_hdmac: correct incompatible type for argument 1 of \u0027spin_lock_bh\u0027\n\nCorrect a typo error in locking calls.\n\nCc: \u003cstable@kernel.org\u003e\nSigned-off-by: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "471452104b8520337ae2fb48c4e61cd4896e025d", "tree": "8594ae4a8362014e3cccf72a4e8834cdbb610bdd", "parents": [ "0ead0f84e81a41c3e98aeceab04af8ab1bb08d1f" ], "author": { "name": "Alexey Dobriyan", "email": "adobriyan@gmail.com", "time": "Mon Dec 14 18:00:08 2009 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Dec 15 08:53:25 2009 -0800" }, "message": "const: constify remaining dev_pm_ops\n\nSigned-off-by: Alexey Dobriyan \u003cadobriyan@gmail.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "d0316554d3586cbea60592a41391b5def2553d6f", "tree": "5e7418f0bacbc68cec5dfd1541e03eb56870aa02", "parents": [ "fb0bbb92d42d5bd0ab224605444efdfed06d6934", "51e99be00ce2713cbb841cedc997cafa6e26c7f4" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Dec 14 09:58:24 2009 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Dec 14 09:58:24 2009 -0800" }, "message": "Merge branch \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tj/percpu\n\n* \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tj/percpu: (34 commits)\n m68k: rename global variable vmalloc_end to m68k_vmalloc_end\n percpu: add missing per_cpu_ptr_to_phys() definition for UP\n percpu: Fix kdump failure if booted with percpu_alloc\u003dpage\n percpu: make misc percpu symbols unique\n percpu: make percpu symbols in ia64 unique\n percpu: make percpu symbols in powerpc unique\n percpu: make percpu symbols in x86 unique\n percpu: make percpu symbols in xen unique\n percpu: make percpu symbols in cpufreq unique\n percpu: make percpu symbols in oprofile unique\n percpu: make percpu symbols in tracer unique\n percpu: make percpu symbols under kernel/ and mm/ unique\n percpu: remove some sparse warnings\n percpu: make alloc_percpu() handle array types\n vmalloc: fix use of non-existent percpu variable in put_cpu_var()\n this_cpu: Use this_cpu_xx in trace_functions_graph.c\n this_cpu: Use this_cpu_xx for ftrace\n this_cpu: Use this_cpu_xx in nmi handling\n this_cpu: Use this_cpu operations in RCU\n this_cpu: Use this_cpu ops for VM statistics\n ...\n\nFix up trivial (famous last words) global per-cpu naming conflicts in\n\tarch/x86/kvm/svm.c\n\tmm/slab.c\n" }, { "commit": "12458ea06efd7b44281e68fe59c950ec7d59c649", "tree": "264df3c6fa054b7b866bb2eccca5f83e41044632", "parents": [ "2e032b62c4c8560d6416ad3cc925cfc2a5eafb07" ], "author": { "name": "Anatolij Gustschin", "email": "agust@denx.de", "time": "Fri Dec 11 21:24:44 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Dec 11 21:24:44 2009 -0700" }, "message": "ppc440spe-adma: adds updated ppc440spe adma driver\n\nThis patch adds new version of the PPC440SPe ADMA driver.\n\nSigned-off-by: Yuri Tikhonov \u003cyur@emcraft.com\u003e\nSigned-off-by: Anatolij Gustschin \u003cagust@denx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "2e032b62c4c8560d6416ad3cc925cfc2a5eafb07", "tree": "8700a84d68eebf61def8dde6cf4bd5d76a13c5fb", "parents": [ "a88f6667078412e5eff37ead68a043ee0ec9f1da" ], "author": { "name": "H Hartley Sweeten", "email": "hartleys@visionengravers.com", "time": "Fri Dec 11 21:24:33 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Dec 11 21:24:33 2009 -0700" }, "message": "iop-adma.c: use resource_size()\n\nThe size of the requested and ioremaped memory is off by 1.\nUse resource_size() to get the correct value.\n\nSigned-off-by: H Hartley Sweeten \u003chsweeten@visionengravers.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "86d61b33e48f1da5a6b310d3de93187db62ab72a", "tree": "9d82b881df70b3832111c9f79da69fcb60aa079b", "parents": [ "cfe4f2751ef1a5390b56c5d263f90b6ff138ba31" ], "author": { "name": "Guennadi Liakhovetski", "email": "g.liakhovetski@gmx.de", "time": "Thu Dec 10 18:35:07 2009 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Dec 10 23:32:09 2009 -0700" }, "message": "sh: stylistic improvements for the DMA driver\n\nSigned-off-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "cfe4f2751ef1a5390b56c5d263f90b6ff138ba31", "tree": "05eb71e6046cde60a728b792b9b44918e9b1c210", "parents": [ "ddb4f0f0e05871c7ac540cc778993c06ff53b765" ], "author": { "name": "Guennadi Liakhovetski", "email": "g.liakhovetski@gmx.de", "time": "Fri Dec 04 19:44:48 2009 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Dec 10 23:27:51 2009 -0700" }, "message": "dmaengine: fix dmatest to verify minimum transfer length and test buffer size\n\nTransfers and the test buffer have to be at least align bytes long.\n\nSigned-off-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "ddb4f0f0e05871c7ac540cc778993c06ff53b765", "tree": "6880d9690d296bd2cade679e46ccca8986deab83", "parents": [ "61f135b92f4758bc4d4767cd0a5d2da954e27f14" ], "author": { "name": "Guennadi Liakhovetski", "email": "g.liakhovetski@gmx.de", "time": "Fri Dec 04 19:44:41 2009 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Dec 10 23:25:58 2009 -0700" }, "message": "sh: DMA driver has to specify its alignment requirements\n\nThe SH DMA driver by default uses 32-byte transfers, in this mode buffers and\nsizes have to be 32-byte aligned. Specifying this requirement also fixes Oopses\nwith dmatest.\n\nSigned-off-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "4ef58d4e2ad1fa2a3e5bbf41af2284671fca8cf8", "tree": "856ba96302a36014736747e8464f80eeb827bbdd", "parents": [ "f6c4c8195b5e7878823caa1181be404d9e86d369", "d014d043869cdc591f3a33243d3481fa4479c2d0" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Dec 09 19:43:33 2009 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Dec 09 19:43:33 2009 -0800" }, "message": "Merge branch \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial\n\n* \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: (42 commits)\n tree-wide: fix misspelling of \"definition\" in comments\n reiserfs: fix misspelling of \"journaled\"\n doc: Fix a typo in slub.txt.\n inotify: remove superfluous return code check\n hdlc: spelling fix in find_pvc() comment\n doc: fix regulator docs cut-and-pasteism\n mtd: Fix comment in Kconfig\n doc: Fix IRQ chip docs\n tree-wide: fix assorted typos all over the place\n drivers/ata/libata-sff.c: comment spelling fixes\n fix typos/grammos in Documentation/edac.txt\n sysctl: add missing comments\n fs/debugfs/inode.c: fix comment typos\n sgivwfb: Make use of ARRAY_SIZE.\n sky2: fix sky2_link_down copy/paste comment error\n tree-wide: fix typos \"couter\" -\u003e \"counter\"\n tree-wide: fix typos \"offest\" -\u003e \"offset\"\n fix kerneldoc for set_irq_msi()\n spidev: fix double \"of of\" in comment\n comment typo fix: sybsystem -\u003e subsystem\n ...\n" }, { "commit": "d014d043869cdc591f3a33243d3481fa4479c2d0", "tree": "63626829498e647ba058a1ce06419fe7e4d5f97d", "parents": [ "6ec22f9b037fc0c2e00ddb7023fad279c365324d", "6070d81eb5f2d4943223c96e7609a53cdc984364" ], "author": { "name": "Jiri Kosina", "email": "jkosina@suse.cz", "time": "Mon Dec 07 18:36:35 2009 +0100" }, "committer": { "name": "Jiri Kosina", "email": "jkosina@suse.cz", "time": "Mon Dec 07 18:36:35 2009 +0100" }, "message": "Merge branch \u0027for-next\u0027 into for-linus\n\nConflicts:\n\n\tkernel/irq/chip.c\n" }, { "commit": "e28edb723e64200554194da17617ee6e82de6690", "tree": "6116b7166054a17c9fbd94ade6db070d31c7c786", "parents": [ "2fc42814d8a9dd757abc7f80fbf11e9247e97d40", "01c62c9b32ec122bf5e3edeecec4d826cb8e81e5", "43234b1ef630388c2cffb34eeeaa84dd731602cc", "183bd50f4fe6cd49c1790a90163e3d1ece80f344", "50dcfa0234753c32e1c838cc0e6d7952dda73201", "045868df2c5eee2330c052f8237b428afa9394fd", "6635529987cd01f9af0c3996cf2e7b9e2bbb4aa7", "870725d9fcdecb23eab696d405fa90df46151865" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Dec 05 10:35:18 2009 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sat Dec 05 10:35:18 2009 +0000" }, "message": "Merge branches \u0027at91\u0027, \u0027ep93xx\u0027, \u0027etm\u0027, \u0027ks8695\u0027, \u0027nuc\u0027, \u0027u300\u0027 and \u0027u8500\u0027 into devel\n" }, { "commit": "af901ca181d92aac3a7dc265144a9081a86d8f39", "tree": "380054af22521144fbe1364c3bcd55ad24c9bde4", "parents": [ "972b94ffb90ea6d20c589d9a47215df103388ddd" ], "author": { "name": "André Goddard Rosa", "email": "andre.goddard@gmail.com", "time": "Sat Nov 14 13:09:05 2009 -0200" }, "committer": { "name": "Jiri Kosina", "email": "jkosina@suse.cz", "time": "Fri Dec 04 15:39:55 2009 +0100" }, "message": "tree-wide: fix assorted typos all over the place\n\nThat is \"success\", \"unknown\", \"through\", \"performance\", \"[re|un]mapping\"\n, \"access\", \"default\", \"reasonable\", \"[con]currently\", \"temperature\"\n, \"channel\", \"[un]used\", \"application\", \"example\",\"hierarchy\", \"therefore\"\n, \"[over|under]flow\", \"contiguous\", \"threshold\", \"enough\" and others.\n\nSigned-off-by: André Goddard Rosa \u003candre.goddard@gmail.com\u003e\nSigned-off-by: Jiri Kosina \u003cjkosina@suse.cz\u003e\n" }, { "commit": "56adf7e8127d601b172e180b44551ce83404348f", "tree": "eabcdad1e4b17ea8f7c20a50a44ca859360085d3", "parents": [ "49954c1567cb0d70d28bb5512d471dc5bd4e2c3f" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sun Nov 22 12:10:10 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sun Nov 22 12:10:10 2009 -0700" }, "message": "shdma: fix initialization error handling\n\n1/ Error handling code following a kzalloc should free the allocated data.\n2/ Report an error when no platform data is detected\n\nBoth problems fixed by moving the platform data check before the allocation,\nand allows a goto to be killed.\n\nReported-by: Julia Lawall \u003cjulia@diku.dk\u003e\nAcked-by: Julia Lawall \u003cjulia@diku.dk\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "61f135b92f4758bc4d4767cd0a5d2da954e27f14", "tree": "388fdc08150e2f8fcb2859f70ca67cdd86616f36", "parents": [ "b419148e567728f6af0c3b01965c1cc141e3e13a" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@stericsson.com", "time": "Thu Nov 19 19:49:17 2009 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 23:45:19 2009 -0700" }, "message": "Add COH 901 318 DMA block driver v5\n\nThis patch adds support for the ST-Ericsson COH 901 318 DMA block,\nfound in the U300 series platforms. It registers a DMA slave for\ndevice I/O and also a memcpy slave for memcpy.\n\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "49954c1567cb0d70d28bb5512d471dc5bd4e2c3f", "tree": "c64b4585518028b5c8ae749b93d9f560d536f649", "parents": [ "7b3cc2b1fc2066391e498f3387204908c4eced21" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 17:11:03 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 23:21:03 2009 -0700" }, "message": "ioat3: fix pq completion versus channel deallocation race\n\nThe completion of a pq operation is notified with a null descriptor\nappended to the end of the chain. This descriptor needs to be visible\nto dma clients otherwise the client is precluded from ensuring all\noperations are quiesced before freeing channel resources, i.e. due to\ndescriptor polling it may get the completion notification ahead of the\ninterrupt delivered by the null descriptor.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "7b3cc2b1fc2066391e498f3387204908c4eced21", "tree": "8a2bc28955710c580201046d04843773cb7d87a1", "parents": [ "4499a24dec00e037da7d09caccad45e7594a9c19" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 17:10:37 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 23:21:03 2009 -0700" }, "message": "async_tx: build-time toggling of async_{syndrome,xor}_val dma support\n\nioat3.2 does not support asynchronous error notifications which makes\nthe driver experience latencies when non-zero pq validate results are\nexpected. Provide a mechanism for turning off async_xor_val and\nasync_syndrome_val via Kconfig. This approach is generally useful for\nany driver that specifies ASYNC_TX_DISABLE_CHANNEL_SWITCH and would like\nto force the async_tx api to fall back to the synchronous path for\ncertain operations.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "4499a24dec00e037da7d09caccad45e7594a9c19", "tree": "d336eb5f67a2873bcd7e43ef64d5d149283e7e0f", "parents": [ "b57014def9afc2bd8a62299d2f51b77dad5ae0c7" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 17:10:25 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 23:21:03 2009 -0700" }, "message": "dmaengine: include xor/pq validate in device_has_all_tx_types()\n\nA channel must include these capabilities to satisfy\nASYNC_TX_DISABLE_CHANNEL_SWITCH.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "b57014def9afc2bd8a62299d2f51b77dad5ae0c7", "tree": "b196078bed3b982475bd0dd22ce0ce8aad2f517a", "parents": [ "de581b65f6fe78168affa552c3bd15b8c80ed614" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 17:10:07 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 23:21:03 2009 -0700" }, "message": "ioat2,3: report all uncorrectable errors\n\nModify is_ioat_bug() to catch all errors that are uncorrectable, or not\ncurrently handled.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "de581b65f6fe78168affa552c3bd15b8c80ed614", "tree": "b980e64cf31ad79c489838310be2e13e626dd05c", "parents": [ "6f82b83b7a56bc6e9dd6d7b93531dde6027c5309" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 17:08:45 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 17:08:45 2009 -0700" }, "message": "ioat3: specify valid address for disabled-Q or disabled-P\n\nAlthough disabled, hardware still checks address validity, so duplicate\nthe known address.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "6f82b83b7a56bc6e9dd6d7b93531dde6027c5309", "tree": "d6f9fc6064e60711e1d041a48d8ff0927ca819e7", "parents": [ "228c4f5cfbf1cda411d9aa7204a612a63c89b1e8" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 17:07:57 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 17:07:57 2009 -0700" }, "message": "ioat2,3: disable asynchronous error notifications\n\nError interrupts and error completions may cause channel hangs, so\npoll the channel status register after a timeout.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "228c4f5cfbf1cda411d9aa7204a612a63c89b1e8", "tree": "0920f900732ce598fef2cdc0c4899860534e837d", "parents": [ "e22dde9904c2d26a522f1a2b89854a8238bf0933" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 17:07:10 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Nov 19 17:07:10 2009 -0700" }, "message": "ioat3: dca and raid operations are incompatible\n\nRAID operations cause a system hang on platforms with DCA\n(Direct-Cache-Access) enabled. So turn off RAID capabilities in this\ncase.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "e22dde9904c2d26a522f1a2b89854a8238bf0933", "tree": "dbb3b1f2d1d1ddafb3c004819c25c31a73811ae8", "parents": [ "b419148e567728f6af0c3b01965c1cc141e3e13a" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Nov 17 11:34:31 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Nov 17 11:34:31 2009 -0700" }, "message": "ioat: silence \"dca disabled\" messages\n\nTurning off dca is not an \"error\", and the dca-enabled state can be\nviewed from sysfs.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "cd3abf98aeaec9b23a926159856b54a95707ee88", "tree": "c5d73254dce77c63e88ac9010322fbd1da032984", "parents": [ "f51f78c06c7fb442d304b93b68b3a1ebe3785a55" ], "author": { "name": "Yegor Yefremov", "email": "yegorslists@googlemail.com", "time": "Fri Oct 23 11:27:59 2009 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Sun Oct 25 16:00:34 2009 +0000" }, "message": "ARM: 5770/1: Add DMA Engine support to at91sam9g45\n\nAdd at91sam9g45 dependency to drivers/dma/Kconfig\n\nSigned-off-by: Yegor Yefremov \u003cyegorslists@googlemail.com\u003e\nAcked-by: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n" }, { "commit": "e7dcaa4755e35d7540bf19f316f8798357c53fa0", "tree": "69c41151378213382199b577f2bc7b0d8bd1cc22", "parents": [ "ca0c9584b1f16bd5911893647cb7f1be82e60554" ], "author": { "name": "Christoph Lameter", "email": "cl@linux-foundation.org", "time": "Sat Oct 03 19:48:23 2009 +0900" }, "committer": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Sat Oct 03 19:48:23 2009 +0900" }, "message": "this_cpu: Eliminate get/put_cpu\n\nThere are cases where we can use this_cpu_ptr and as the result\nof using this_cpu_ptr() we no longer need to determine the\ncurrently executing cpu.\n\nIn those places no get/put_cpu combination is needed anymore.\nThe local cpu variable can be eliminated.\n\nPreemption still needs to be disabled and enabled since the\nmodifications of the per cpu variables is not atomic. There may\nbe multiple per cpu variables modified and those must all\nbe from the same processor.\n\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nAcked-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nAcked-by: Tejun Heo \u003ctj@kernel.org\u003e\ncc: Eric Biederman \u003cebiederm@aristanetworks.com\u003e\ncc: Stephen Hemminger \u003cshemminger@vyatta.com\u003e\ncc: David L Stevens \u003cdlstevens@us.ibm.com\u003e\nSigned-off-by: Christoph Lameter \u003ccl@linux-foundation.org\u003e\nSigned-off-by: Tejun Heo \u003ctj@kernel.org\u003e\n" }, { "commit": "4b3df5668c8ebaebd8d66a5a94374be3e3b2ef0c", "tree": "51a231742e211143f5845edf4b09d1712dcd2771", "parents": [ "1ef04fefe2241087d9db7e9615c3f11b516e36cf", "1f6672d44c1ae7408b43c06170ec34eb0a0e9b9f" ], "author": { "name": "NeilBrown", "email": "neilb@suse.de", "time": "Wed Sep 23 18:31:11 2009 +1000" }, "committer": { "name": "NeilBrown", "email": "neilb@suse.de", "time": "Wed Sep 23 18:31:11 2009 +1000" }, "message": "Merge branch \u0027next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx into for-linus\n" }, { "commit": "cdef57dbb618608bfffda2fc32c8d0a4012a1d3a", "tree": "e58d3301ea4fb264f713c4602c25e6451d4e6707", "parents": [ "f477f5b3316f39c841aa121a219b82b3a56e7da7" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Sep 21 09:22:29 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Sep 21 09:22:29 2009 -0700" }, "message": "ioat3: fix uninitialized var warnings\n\ndrivers/dma/ioat/dma_v3.c: In function \u0027ioat3_prep_memset_lock\u0027:\ndrivers/dma/ioat/dma_v3.c:439: warning: \u0027fill\u0027 may be used uninitialized in this function\ndrivers/dma/ioat/dma_v3.c:437: warning: \u0027desc\u0027 may be used uninitialized in this function\ndrivers/dma/ioat/dma_v3.c: In function \u0027__ioat3_prep_xor_lock\u0027:\ndrivers/dma/ioat/dma_v3.c:489: warning: \u0027xor\u0027 may be used uninitialized in this function\ndrivers/dma/ioat/dma_v3.c:486: warning: \u0027desc\u0027 may be used uninitialized in this function\ndrivers/dma/ioat/dma_v3.c: In function \u0027__ioat3_prep_pq_lock\u0027:\ndrivers/dma/ioat/dma_v3.c:631: warning: \u0027pq\u0027 may be used uninitialized in this function\ndrivers/dma/ioat/dma_v3.c:628: warning: \u0027desc\u0027 may be used uninitialized in this function\n\ngcc-4.0, unlike gcc-4.3, does not see that these variables are\ninitialized before use. Convert the descriptor loops to do-while make\nthis initialization apparent.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "f477f5b3316f39c841aa121a219b82b3a56e7da7", "tree": "392476186ece4084f85b3c5227853d92ecae79a6", "parents": [ "1b6df6930994d5d027375b07ac9da63644eb5758" ], "author": { "name": "Andrew Morton", "email": "akpm@linux-foundation.org", "time": "Mon Sep 21 09:17:58 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Sep 21 09:17:58 2009 -0700" }, "message": "drivers/dma/ioat/dma_v2.c: fix warnings\n\ndrivers/dma/ioat/dma_v2.c: In function \u0027ioat2_dma_prep_memcpy_lock\u0027:\ndrivers/dma/ioat/dma_v2.c:680: warning: \u0027hw\u0027 may be used uninitialized in this function\ndrivers/dma/ioat/dma_v2.c:681: warning: \u0027desc\u0027 may be used uninitialized in this function\n\nCc: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "376ec37667b510453f5a62fcd95d762786e6a0a9", "tree": "7352166b585463ce53633e379b96196dff72014f", "parents": [ "6c910a78e495b4c1778a8b136b37fe3c05712730" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Sep 16 15:16:50 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Sep 16 15:16:50 2009 -0700" }, "message": "ioat2: clarify ring size limits\n\nWith the addition of ioat_max_alloc_order it is not clear what the\nmaximum allocation order is, so document that in the modinfo. Also take\nan opportunity to kill a stray semicolon.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "33f82d141c897f39cd8bce592d88cb3c5af58342", "tree": "7765831183d05fb635e60e8f8bf92e0bdfe06b5c", "parents": [ "3eb132c986f04f64b9c360abd67a1e0d18d6d5b4" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Sep 10 00:06:44 2009 +0200" }, "committer": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Mon Sep 14 20:27:00 2009 +0200" }, "message": "at_hdmac: Rework suspend_late()/resume_early()\n\nThis patch reworks platform driver power management code\nfor at_hdmac from legacy late/early callbacks to dev_pm_ops.\n\nThe callbacks are converted for CONFIG_SUSPEND like this:\n suspend_late() -\u003e suspend_noirq()\n resume_early() -\u003e resume_noirq()\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\n" }, { "commit": "3208ca52f3bfa36914c44db207d0a34071f9897f", "tree": "fb28779eb8ec74fd650f2df085f507353fcd79ce", "parents": [ "1a5aeeecd550ee4344cfba1791f1134739b16dc6" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Sep 10 11:27:36 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Sep 10 11:27:36 2009 -0700" }, "message": "ioat: driver version 4.0\n\nA new ring implementation and the addition of raid functionality\nconstitutes a bump in the driver major version number.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "1a5aeeecd550ee4344cfba1791f1134739b16dc6", "tree": "0b2f1f104d7dbff82130ea1d41c037a74fa6753e", "parents": [ "9a8de639f35ca3951b910d5e3a2f92f4cf3afc8f" ], "author": { "name": "Maciej Sosnowski", "email": "maciej.sosnowski@intel.com", "time": "Thu Sep 10 15:05:58 2009 +0200" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Sep 10 10:00:05 2009 -0700" }, "message": "dca: registering requesters in multiple dca domains\n\nThis patch enables DCA support on multiple-IOH/multiple-IIO architectures.\nIt modifies dca module by replacing single dca_providers list\nwith dca_domains list, each domain containing separate list of providers.\nThis approach lets dca driver manage multiple domains, i.e. sets of providers\nand requesters mapped back to the same PCI root complex device.\nThe driver takes care to register each requester to a provider\nfrom the same domain.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\n" }, { "commit": "9a8de639f35ca3951b910d5e3a2f92f4cf3afc8f", "tree": "58d799166b6facdf25e314885ee7fadd20597482", "parents": [ "d8902adcc1a9fd484c8cb5e575152e32192c1ff8" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 15:06:10 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:56:37 2009 -0700" }, "message": "async_tx: remove HIGHMEM64G restriction\n\nThis restriction prevented ASYNC_TX_DMA from being enabled on platform\nconfigurations where DMA address conversion could not be performed in\nplace on the stack. Since commit 04ce9ab3 (\"async_xor: permit callers\nto pass in a \u0027dma/page scribble\u0027 region\") the async_tx api now either\nuses a caller provided \u0027scribble\u0027 buffer, or performs the conversion in\nplace when sizeof(dma_addr_t) \u003c\u003d sizeof(struct page *).\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "d8902adcc1a9fd484c8cb5e575152e32192c1ff8", "tree": "305109ce60db5ea9710dddce9db8a23f65ff4572", "parents": [ "9134d02bc0af4a8747d448d1f811ec5f8eb96df6" ], "author": { "name": "Nobuhiro Iwamatsu", "email": "iwamatsu.nobuhiro@renesas.com", "time": "Mon Sep 07 03:26:23 2009 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:56:02 2009 -0700" }, "message": "dmaengine: sh: Add Support SuperH DMA Engine driver\n\nThis supported all DMA channels, and it was tested in SH7722,\nSH7780, SH7785 and SH7763.\nThis can not use with SH DMA API.\n\nSigned-off-by: Nobuhiro Iwamatsu \u003ciwamatsu.nobuhiro@renesas.com\u003e\nReviewed-by: Matt Fleming \u003cmatt@console-pimps.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nAcked-by: Paul Mundt \u003clethal@linux-sh.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "bbb20089a3275a19e475dbc21320c3742e3ca423", "tree": "216fdc1cbef450ca688135c5b8969169482d9a48", "parents": [ "3e48e656903e9fd8bc805c6a2c4264d7808d315b", "657a77fa7284d8ae28dfa48f1dc5d919bf5b2843" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:55:21 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:55:21 2009 -0700" }, "message": "Merge branch \u0027dmaengine\u0027 into async-tx-next\n\nConflicts:\n\tcrypto/async_tx/async_xor.c\n\tdrivers/dma/ioat/dma_v2.h\n\tdrivers/dma/ioat/pci.c\n\tdrivers/md/raid5.c\n" }, { "commit": "3e48e656903e9fd8bc805c6a2c4264d7808d315b", "tree": "dfee34eb1f317b35f33a02291e65ce6ec46e3a5a", "parents": [ "a6417dd58d6832f123f36c6f22c63ec1ab62ce1c", "f6dbf651615900646fe0ba1ef5ce1027e5b4748d" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:57 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:57 2009 -0700" }, "message": "Merge branch \u0027iop-raid6\u0027 into async-tx-next\n" }, { "commit": "657a77fa7284d8ae28dfa48f1dc5d919bf5b2843", "tree": "74fd6b5c2c35dcea18928a600ff34c04f8626cb6", "parents": [ "bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7d" ], "author": { "name": "Atsushi Nemoto", "email": "anemo@mba.ocn.ne.jp", "time": "Tue Sep 08 17:53:05 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:05 2009 -0700" }, "message": "dmaengine: Move all map_sg/unmap_sg for slave channel to its client\n\nDan Williams wrote:\n... DMA-slave clients request specific channels and know the hardware\ndetails at a low level, so it should not be too high an expectation to\npush dma mapping responsibility to the client.\n\nAlso this patch includes DMA_COMPL_{SRC,DEST}_UNMAP_SINGLE support for\ndw_dmac driver.\n\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nAcked-by: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nSigned-off-by: Atsushi Nemoto \u003canemo@mba.ocn.ne.jp\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "bbea0b6e0d214ef1511b9c6ccf3af26b38f0af7d", "tree": "5f2145c023b9145d1461ecb63c839fd32f762378", "parents": [ "e6c7ecb64e08ef346cb7062b4a5421f00bc602bd" ], "author": { "name": "Ira Snyder", "email": "iws@ovro.caltech.edu", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "message": "fsldma: Add DMA_SLAVE support\n\nUse the DMA_SLAVE capability of the DMAEngine API to copy/from a\nscatterlist into an arbitrary list of hardware address/length pairs.\n\nThis allows a single DMA transaction to copy data from several different\ndevices into a scatterlist at the same time.\n\nThis also adds support to enable some controller-specific features such as\nexternal start and external pause for a DMA transaction.\n\n[dan.j.williams@intel.com: rebased on tx_list movement]\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nAcked-by: Li Yang \u003cleoli@freescale.com\u003e\nAcked-by: Kumar Gala \u003cgalak@kernel.crashing.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n" }, { "commit": "e6c7ecb64e08ef346cb7062b4a5421f00bc602bd", "tree": "73424d223391302a9a16df65378d78f25fd05929", "parents": [ "162b96e63e518aa6ff029ce23de12d7f027483bf" ], "author": { "name": "Ira Snyder", "email": "iws@ovro.caltech.edu", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "message": "fsldma: split apart external pause and request count features\n\nWhen using the Freescale DMA controller in external control mode, both the\nrequest count and external pause bits need to be setup correctly. This was\nbeing done with the same function.\n\nThe 83xx controller lacks the external pause feature, but has a similar\nfeature called external start. This feature requires that the request count\nbits be setup correctly.\n\nSplit the function into two parts, to make it possible to use the external\nstart feature on the 83xx controller.\n\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "162b96e63e518aa6ff029ce23de12d7f027483bf", "tree": "532191d0cef7cf975b70a07b1c69a293d6f552f7", "parents": [ "0803172778901e24a75ab074798d98c2b7411559" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "message": "ioat2,3: cacheline align software descriptor allocations\n\nAll the necessary fields for handling an ioat2,3 ring entry can fit into\none cacheline. Move -\u003elen prior to -\u003etxd in struct ioat_ring_ent, and\nmove allocation of these entries to a hw-cache-aligned kmem cache to\nreduce the number of cachelines dirtied for descriptor management.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "0803172778901e24a75ab074798d98c2b7411559", "tree": "a3e1d0cf4228d65dc1fac2ad56f3beb6b6f3474b", "parents": [ "1979b186b80449ac6574d97c254b694c8a99b703" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:04 2009 -0700" }, "message": "dmaengine: kill tx_list\n\nThe tx_list attribute of struct dma_async_tx_descriptor is common to\nmost, but not all dma driver implementations. None of the upper level\ncode (dmaengine/async_tx) uses it, so allow drivers to implement it\nlocally if they need it. This saves sizeof(struct list_head) bytes for\ndrivers that do not manage descriptors with a linked list (e.g.: ioatdma\nv2,3).\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "1979b186b80449ac6574d97c254b694c8a99b703", "tree": "9befdf33c11c0b0e4ce6720c7c81efeb7005ce7c", "parents": [ "285a3c71640ad7101b7237b8fbaa4ead22c6551c" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:03 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:03 2009 -0700" }, "message": "txx9dmac: implement a private tx_list\n\nDrop txx9dmac\u0027s use of tx_list from struct dma_async_tx_descriptor in\npreparation for removal of this field.\n\nCc: Atsushi Nemoto \u003canemo@mba.ocn.ne.jp\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "285a3c71640ad7101b7237b8fbaa4ead22c6551c", "tree": "d4da48d227f2bc069cb3c1074c6267b5e29426e1", "parents": [ "64203b67274680e95e0c2eec935a22fc94e9ecb5" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:03 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:03 2009 -0700" }, "message": "at_hdmac: implement a private tx_list\n\nDrop at_hdmac\u0027s use of tx_list from struct dma_async_tx_descriptor in\npreparation for removal of this field.\n\nCc: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "64203b67274680e95e0c2eec935a22fc94e9ecb5", "tree": "93d56edbf3ecccdd0cffae3a20c3a7b7dd17cd5a", "parents": [ "ea25968a32a621b02c3715d6b649f0c6ef53c24e" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:03 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:03 2009 -0700" }, "message": "mv_xor: implement a private tx_list\n\nDrop mv_xor\u0027s use of tx_list from struct dma_async_tx_descriptor in\npreparation for removal of this field.\n\nCc: Saeed Bishara \u003csaeed@marvell.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "ea25968a32a621b02c3715d6b649f0c6ef53c24e", "tree": "8da75c38c0ac0690eb03e89ccf146d062ba4d855", "parents": [ "308136d1abcb2d759bac40ed4f5d42ac4af59d8b" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:02 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:02 2009 -0700" }, "message": "ioat: implement a private tx_list\n\nDrop ioatdma\u0027s use of tx_list from struct dma_async_tx_descriptor in\npreparation for removal of this field.\n\nCc: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "308136d1abcb2d759bac40ed4f5d42ac4af59d8b", "tree": "c0cf21c5144929332a5f99d1aff8393e6cddcbbb", "parents": [ "eda34234578fd822c950fd06b5c5ff7ac08b3001" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:02 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:02 2009 -0700" }, "message": "iop-adma: implement a private tx_list\n \nDrop iop-adma\u0027s use of tx_list from struct dma_async_tx_descriptor in\npreparation for removal of this field.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "eda34234578fd822c950fd06b5c5ff7ac08b3001", "tree": "860b3c9d347ddd57e6884f9f1e019370de4d45b1", "parents": [ "e0bd0f8cb09cf3ccac1425f0f3a6705106c4d65c" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:02 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:02 2009 -0700" }, "message": "fsldma: implement a private tx_list\n\nDrop fsldma\u0027s use of tx_list from struct dma_async_tx_descriptor in\npreparation for removal of this field.\n\nCc: Li Yang \u003cleoli@freescale.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "e0bd0f8cb09cf3ccac1425f0f3a6705106c4d65c", "tree": "664db6534e1654e98142ae01dab0aa223196d3d7", "parents": [ "e12c4fa377ffda2490476caae17f24daaf9c9bd7" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:02 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:53:02 2009 -0700" }, "message": "dw_dmac: implement a private tx_list\n\nDrop dw_dmac\u0027s use of tx_list from struct dma_async_tx_descriptor in\npreparation for removal of this field.\n\nCc: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "e12c4fa377ffda2490476caae17f24daaf9c9bd7", "tree": "aa7a19d8f7f931709a8a835a4b0d441f83d759fd", "parents": [ "a348a7e6fdbcd2d5192a09719a479bb238fde727", "4b652f0db3be891c7b76b109c3b55003b920fc96" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:52:57 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:52:57 2009 -0700" }, "message": "Merge branch \u0027ioat\u0027 into dmaengine\n" }, { "commit": "a6417dd58d6832f123f36c6f22c63ec1ab62ce1c", "tree": "b8aa7273a874904396c79099facd104eeb4074e0", "parents": [ "6506cbca6b5b36d682bd39afcbf3f575c81dddb6" ], "author": { "name": "Roland Dreier", "email": "rdreier@cisco.com", "time": "Tue Sep 08 17:43:03 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:43:03 2009 -0700" }, "message": "I/OAT: Convert to PCI_VDEVICE()\n\nTrivial cleanup to make the PCI ID table easier to read.\n\n[dan.j.williams@intel.com: extended to v3.2 devices]\nSigned-off-by: Roland Dreier \u003crolandd@cisco.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "6506cbca6b5b36d682bd39afcbf3f575c81dddb6", "tree": "ea82de689e7712eaa76209afcaf9a8678dac9f3f", "parents": [ "e3232714d465c42ac631929b990f5e35e2d8a955" ], "author": { "name": "Roland Dreier", "email": "rdreier@cisco.com", "time": "Tue Sep 08 17:43:03 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:43:03 2009 -0700" }, "message": "Add MODULE_DEVICE_TABLE() so ioatdma module is autoloaded\n\nThe ioatdma module is missing aliases for the PCI devices it supports,\nso it is not autoloaded on boot. Add a MODULE_DEVICE_TABLE() to get\nthese aliases.\n\nSigned-off-by: Roland Dreier \u003crolandd@cisco.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "e3232714d465c42ac631929b990f5e35e2d8a955", "tree": "f6b9fe66bd11cdae420f558bebf7e8d4b89b52b4", "parents": [ "b265b11fc1a0bd6ae5a7fde12e374583a52ab326" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:43:02 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:43:02 2009 -0700" }, "message": "ioat3: segregate raid engines\n\nThe cleanup routine for the raid cases imposes extra checks for handling\nraid descriptors and extended descriptors. If the channel does not\nsupport raid it can avoid this extra overhead by using the ioat2 cleanup\npath.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "b265b11fc1a0bd6ae5a7fde12e374583a52ab326", "tree": "8a864413b52e06f11f7f0299cdefd398999e82fb", "parents": [ "58c8649e0e25de511c4a66ce3fa38891e2ec4e9e" ], "author": { "name": "Tom Picard", "email": "tom.s.picard@intel.com", "time": "Tue Sep 08 17:43:01 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:43:01 2009 -0700" }, "message": "ioat3: ioat3.2 pci ids for Jasper Forest\n\nJasper Forest introduces raid offload support via ioat3.2 support. When\nraid offload is enabled two (out of 8 channels) will report raid5/raid6\noffload capabilities. The remaining channels will only report ioat3.0\ncapabilities (memcpy).\n\nSigned-off-by: Tom Picard \u003ctom.s.picard@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "58c8649e0e25de511c4a66ce3fa38891e2ec4e9e", "tree": "edb87012a3e42a7bbaa26a1172442da6ea389632", "parents": [ "ae786624c27411c1d38823f640b39f3d97412d5a" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:43:00 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:43:00 2009 -0700" }, "message": "ioat3: interrupt descriptor support\n\nThe async_tx api uses the DMA_INTERRUPT operation type to terminate a\nchain of issued operations with a callback routine.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "ae786624c27411c1d38823f640b39f3d97412d5a", "tree": "87ca33dae521c2c5622ea67dde97611e77d77df8", "parents": [ "d69d235b7da2778891640ee95efcd68075978904" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:43:00 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:43:00 2009 -0700" }, "message": "ioat3: support xor via pq descriptors\n\nIf a platform advertises pq capabilities, but not xor, then use\nioat3_prep_pqxor and ioat3_prep_pqxor_val to simulate xor support.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "d69d235b7da2778891640ee95efcd68075978904", "tree": "e7f22d38d8a742ddbca167af123f4987ada8926c", "parents": [ "9de6fc717bdc574cf5faf9d46ce0f9d6265c7952" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:59 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:59 2009 -0700" }, "message": "ioat3: pq support\n\nioat3.2 adds support for raid6 syndrome generation (xor sum of galois\nfield multiplication products) using up to 8 sources. It can also\nperform an pq-zero-sum operation to validate whether the syndrome for a\ngiven set of sources matches a previously computed syndrome.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "9de6fc717bdc574cf5faf9d46ce0f9d6265c7952", "tree": "55cb18ecfae85033d61f730b5f32d2ac1fb572bc", "parents": [ "b094ad3be564e7cc59cca4ff0256550d3a55dd3b" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:58 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:58 2009 -0700" }, "message": "ioat3: xor self test\n\nThis adds a hardware specific self test to be called from ioat_probe.\nIn the ioat3 case we will have tests for all the different raid\noperations, while ioat1 and ioat2 will continue to just test memcpy.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "b094ad3be564e7cc59cca4ff0256550d3a55dd3b", "tree": "d69f515b2ee6af2b0f12bb3028d7c7f5b3390794", "parents": [ "e61dacaeb3918cd00cd642e8fb0828324ac59819" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:57 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:57 2009 -0700" }, "message": "ioat3: xor support\n\nioat3.2 adds xor offload support for up to 8 sources. It can also\nperform an xor-zero-sum operation to validate whether all given sources\nsum to zero, without writing to a destination. Xor descriptors differ\nfrom memcpy in that one operation may require multiple descriptors\ndepending on the number of sources. When the number of sources exceeds\n5 an extended descriptor is needed. These descriptors need to be\naccounted for when updating the DMA_COUNT register.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "e61dacaeb3918cd00cd642e8fb0828324ac59819", "tree": "70c4acf1cf33502bdca8da16bd88c0daab2bbc29", "parents": [ "5669e31c5a4874f1634bc0ffba268a6e2fa0cdd2" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:57 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:57 2009 -0700" }, "message": "ioat3: enable dca for completion writes\n\nTag completion writes for direct cache access to reduce the latency of\nchecking for descriptor completions.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "5669e31c5a4874f1634bc0ffba268a6e2fa0cdd2", "tree": "3ef3f6724e7a812ba83b420c3915c4a46762aeb7", "parents": [ "bf40a6869c9198bdf56fe173961feb89e9f0d961" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:56 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:56 2009 -0700" }, "message": "ioat: add \u0027ioat\u0027 sysfs attributes\n\nExport driver attributes for diagnostic purposes:\n\u0027ring_size\u0027: total number of descriptors available to the engine\n\u0027ring_active\u0027: number of descriptors in-flight\n\u0027capabilities\u0027: supported operation types for this channel\n\u0027version\u0027: Intel(R) QuickData specfication revision\n\nThis also allows some chattiness to be removed from the driver startup\nas this information is now available via sysfs.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "bf40a6869c9198bdf56fe173961feb89e9f0d961", "tree": "3d1b6bf44647857997113fe1b036fb46e360d8a7", "parents": [ "2aec048cdc4a5a81163a42a61df903f76a27e737" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:55 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:55 2009 -0700" }, "message": "ioat3: split ioat3 support to its own file, add memset\n\nUp until this point the driver for Intel(R) QuickData Technology\nengines, specification versions 2 and 3, were mostly identical save for\na few quirks. Version 3.2 hardware adds many new capabilities (like\nraid offload support) requiring some infrastructure that is not relevant\nfor v2. For better code organization of the new funcionality move v3\nand v3.2 support to its own file dma_v3.c, and export some routines from\nthe base files (dma.c and dma_v2.c) that can be reused directly.\n\nThe first new capability included in this code reorganization is support\nfor v3.2 memset operations.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "2aec048cdc4a5a81163a42a61df903f76a27e737", "tree": "00347decc9b145f4c805c8475b980d2641b8ec11", "parents": [ "128f2d567f906d38b11d993d8d97b9b988848e26" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:54 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:54 2009 -0700" }, "message": "ioat3: hardware version 3.2 register / descriptor definitions\n\nioat3.2 adds raid5 and raid6 offload capabilities.\n\nSigned-off-by: Tom Picard \u003ctom.s.picard@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "128f2d567f906d38b11d993d8d97b9b988848e26", "tree": "523fd4b737bd44bccddb2425ae0b16f78a819e19", "parents": [ "83544ae9f3991bfc7d5e0fe9a3008cd05a8d57b7" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:53 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:53 2009 -0700" }, "message": "ioat2+: add fence support\n\nIn preparation for adding more operation types to the ioat3 path the\ndriver needs to honor the DMA_PREP_FENCE flag. For example the async_tx api\nwill hand xor-\u003ememcpy-\u003exor chains to the driver with the \u0027fence\u0027 flag set on\nthe first xor and the memcpy operation. This flag in turn sets the \u0027fence\u0027\nflag in the descriptor control field telling the hardware that future\ndescriptors in the chain depend on the result of the current descriptor, so\nwait for all writes to complete before starting the next operation.\n\nNote that ioat1 does not prefetch the descriptor chain, so does not\nrequire/support fenced operations.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "83544ae9f3991bfc7d5e0fe9a3008cd05a8d57b7", "tree": "bc4b28c2e5bdae01a2c8a250176fcdac6ae7a8ce", "parents": [ "9308add6ea4fedeba37b0d7c4630a542bd34f214" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:53 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:53 2009 -0700" }, "message": "dmaengine, async_tx: support alignment checks\n\nSome engines have transfer size and address alignment restrictions. Add\na per-operation alignment property to struct dma_device that the async\nroutines and dmatest can use to check alignment capabilities.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "9308add6ea4fedeba37b0d7c4630a542bd34f214", "tree": "5b94b9c8eebc7a7ef6879a7fdfc553c6758312dc", "parents": [ "138f4c359d23d2ec38d18bd70dd9613ae515fe93" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:52 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:52 2009 -0700" }, "message": "dmaengine: cleanup unused transaction types\n\nNo drivers currently implement these operation types, so they can be\ndeleted.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "138f4c359d23d2ec38d18bd70dd9613ae515fe93", "tree": "ad7fafba6eac74d9d92ade839a65171466d67a70", "parents": [ "0403e3827788d878163f9ef0541b748b0f88ca5d" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:51 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:51 2009 -0700" }, "message": "dmaengine, async_tx: add a \"no channel switch\" allocator\n\nChannel switching is problematic for some dmaengine drivers as the\narchitecture precludes separating the -\u003eprep from -\u003esubmit. In these\ncases the driver can select ASYNC_TX_DISABLE_CHANNEL_SWITCH to modify\nthe async_tx allocator to only return channels that support all of the\nrequired asynchronous operations.\n\nFor example MD_RAID456\u003dy selects support for asynchronous xor, xor\nvalidate, pq, pq validate, and memcpy. When\nASYNC_TX_DISABLE_CHANNEL_SWITCH\u003dy any channel with all these\ncapabilities is marked DMA_ASYNC_TX allowing async_tx_find_channel() to\nquickly locate compatible channels with the guarantee that dependency\nchains will remain on one channel. When\nASYNC_TX_DISABLE_CHANNEL_SWITCH\u003dn async_tx_find_channel() may select\nchannels that lead to operation chains that need to cross channel\nboundaries using the async_tx channel switch capability.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "f9dd2134374c8de6b911e2b8652c6c9622eaa658", "tree": "c1b8f8d622941606b9e7247ab31d811ba4295011", "parents": [ "4b652f0db3be891c7b76b109c3b55003b920fc96", "07a3b417dc3d00802bd7b4874c3e811f0b015a7d" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:29 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:42:29 2009 -0700" }, "message": "Merge branch \u0027md-raid6-accel\u0027 into ioat3.2\n\nConflicts:\n\tinclude/linux/dmaengine.h\n" }, { "commit": "4b652f0db3be891c7b76b109c3b55003b920fc96", "tree": "a7747543a2076a2f58f423297e0da78b2963a04d", "parents": [ "a309218acee8606f7e235da20cc826eb06d9b0f6" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 12:02:15 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:38:54 2009 -0700" }, "message": "net_dma: poll for a descriptor after allocation failure\n\nHandle descriptor allocation failures by polling for a descriptor. The\ndriver will force forward progress when polled. In the best case this\npolling interval will be the time it takes for one dma memcpy\ntransaction to complete. In the worst case, channel hang, we will need\nto wait 100ms for the cleanup watchdog to fire (ioatdma driver).\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "a309218acee8606f7e235da20cc826eb06d9b0f6", "tree": "abf2cc9830b6a5a52a165e6a736e85cd5d7b36c0", "parents": [ "09c8a5b85e5f1e74a19bdd7c85547429d51df1cd" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 12:02:01 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:38:54 2009 -0700" }, "message": "ioat2,3: dynamically resize descriptor ring\n\nIncrement the allocation order of the descriptor ring every time we run\nout of descriptors up to a maximum of allocation order specified by the\nmodule parameter \u0027ioat_max_alloc_order\u0027. After each idle period\ndecrement the allocation order to a minimum order of\n\u0027ioat_ring_alloc_order\u0027 (i.e. the default ring size, tunable as a module\nparameter).\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "09c8a5b85e5f1e74a19bdd7c85547429d51df1cd", "tree": "9bb255d9f596ab062996de49032875e8b9253971", "parents": [ "ad643f54c8514998333bc6c7b201fda2267496be" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 12:01:49 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:30:24 2009 -0700" }, "message": "ioat: switch watchdog and reset handler from workqueue to timer\n\nIn order to support dynamic resizing of the descriptor ring or polling\nfor a descriptor in the presence of a hung channel the reset handler\nneeds to make progress while in a non-preemptible context. The current\nworkqueue implementation precludes polling channel reset completion\nunder spin_lock().\n\nThis conversion also allows us to return to opportunistic cleanup in the\nioat2 case as the timer implementation guarantees at least one cleanup\nafter every descriptor is submitted. This means the worst case\ncompletion latency becomes the timer frequency (for exceptional\ncircumstances), but with the benefit of avoiding busy waiting when the\nlock is contended.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "ad643f54c8514998333bc6c7b201fda2267496be", "tree": "c92bbecd74912ada08dfa94662b52e63d4c5df46", "parents": [ "345d852391cf3fdc73f23a9ca522c6e7b5eb5a52" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 12:01:38 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:30:24 2009 -0700" }, "message": "ioat1: trim ioat_dma_desc_sw\n\nSave 4 bytes per software descriptor by transmitting tx_cnt in an unused\nportion of the hardware descriptor.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "345d852391cf3fdc73f23a9ca522c6e7b5eb5a52", "tree": "a029ab0c4e66a6ea7c7a7b76c06bcffe92fab5e8", "parents": [ "f6ab95b55735fa03cad8d0f966647e5df206e207" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 12:01:30 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:30:24 2009 -0700" }, "message": "ioat: ___devinit annotate the initialization paths\n\nMark all single use initialization routines with __devinit.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "f6ab95b55735fa03cad8d0f966647e5df206e207", "tree": "958127a8b5e171d53d26cd1a40d128e34bf8c7b1", "parents": [ "bb3207863014c7310593146f11fbc6573eab43c8" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 12:01:21 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:30:24 2009 -0700" }, "message": "ioat: preserve chanctrl bits when re-arming interrupts\n\nThe register write in ioat_dma_cleanup_tasklet is unfortunate in two\nways:\n1/ It clears the extra \u0027enable\u0027 bits that we set at alloc_chan_resources time\n2/ It gives the impression that it disables interrupts when it is in\n fact re-arming interrupts\n\n[ Impact: fix, persist the value of the chanctrl register when re-arming ]\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "bb3207863014c7310593146f11fbc6573eab43c8", "tree": "d54da64e459d28969cdd9250cadaaa581cbae43d", "parents": [ "4fb9b9e8d55880523db550043dfb204696dd0422" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 12:01:14 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:30:24 2009 -0700" }, "message": "ioat: ignore reserved bits for chancnt and xfercap\n\nDon\u0027t trust that the reserved bits are always zero, also sanity check\nthe returned value.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "4fb9b9e8d55880523db550043dfb204696dd0422", "tree": "733a672aeb819bb8133b16329a6b5088cf9ee693", "parents": [ "6df9183a153291a2585a8dfe67597fc18c201147" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 12:01:04 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:30:24 2009 -0700" }, "message": "ioat: cleanup completion status reads\n\nThe cleanup path makes an effort to only perform an atomic read of the\n64-bit completion address. However in the 32-bit case it does not\nmatter if we read the upper-32 and lower-32 non-atomically because the\nupper-32 will always be zero.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "6df9183a153291a2585a8dfe67597fc18c201147", "tree": "5e5f3b3da9308e20f2dda71c85242460bb7cacfa", "parents": [ "38e12f64a165e83617c21dae3c15972fd8d639f5" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 12:00:55 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:30:23 2009 -0700" }, "message": "ioat: add some dev_dbg() calls\n\nProvide some output for debugging the driver.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "38e12f64a165e83617c21dae3c15972fd8d639f5", "tree": "43f0951cf0b91b0d831a469d0147c1c4cdd15dfa", "parents": [ "5cbafa65b92ee4f5b8ba915cddf94b91f186b989" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 12:00:46 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:30:23 2009 -0700" }, "message": "ioat1: kill unused unmap parameters\n\nThe unified ioat1/ioat2 ioat_dma_unmap() implementation derives the\nsource and dest addresses from the unmap descriptor. There is no longer\na need to track this information in struct ioat_desc_sw.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "5cbafa65b92ee4f5b8ba915cddf94b91f186b989", "tree": "f074c9dbcdedf05c5567a4e456a15120895363a6", "parents": [ "dcbc853af6f0c056088e4df0794d9bf36184809e" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Aug 26 13:01:44 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:55 2009 -0700" }, "message": "ioat2,3: convert to a true ring buffer\n\nReplace the current linked list munged into a ring with a native ring\nbuffer implementation. The benefit of this approach is reduced overhead\nas many parameters can be derived from ring position with simple pointer\ncomparisons and descriptor allocation/freeing becomes just a\nmanipulation of head/tail pointers.\n\nIt requires a contiguous allocation for the software descriptor\ninformation.\n\nSince this arrangement is significantly different from the ioat1 chain,\nmove ioat2,3 support into its own file and header. Common routines are\nexported from driver/dma/ioat/dma.[ch].\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "dcbc853af6f0c056088e4df0794d9bf36184809e", "tree": "1cbab40167487cff6dc8984a00756cfc39dff3f3", "parents": [ "a6a39ca1badbeafc16941fcf2c1010c8c65c8ddc" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 28 14:44:50 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:55 2009 -0700" }, "message": "ioat: prepare the code for ioat[12]_dma_chan split\n\nPrepare the code for the conversion of the ioat2 linked-list-ring into a\nnative ring buffer. After this conversion ioat2 channels will share\nless of the ioat1 infrastructure, but there will still be places where\nsharing is possible. struct ioat_chan_common is created to house the\nchannel attributes that will remain common between ioat1 and ioat2\nchannels.\n\nFor every routine that accesses both common and hardware specific fields\nthe old unified \u0027ioat_chan\u0027 pointer is split into an \u0027ioat\u0027 and \u0027chan\u0027\npointer. Where \u0027chan\u0027 references common fields and \u0027ioat\u0027 the\nhardware/version specific.\n\n[ Impact: pure structure member movement/variable renames, no logic changes ]\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n" }, { "commit": "a6a39ca1badbeafc16941fcf2c1010c8c65c8ddc", "tree": "1f6e4bf5e5ab831ce9cb6de645a1f03545c8cf0a", "parents": [ "a0587bcf3e64029a4da2a5666cad18df38db0d56" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 28 14:44:05 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:55 2009 -0700" }, "message": "ioat: fix self test interrupts\n\nIf a callback is to be attached to a descriptor the channel needs to\nknow at -\u003eprep time so it can set the interrupt enable bit. This is in\npreparation for moving descriptor ioat2 descriptor preparation from\n-\u003esubmit to -\u003eprep.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "a0587bcf3e64029a4da2a5666cad18df38db0d56", "tree": "475b3a2a7cd102f40d7c16fed431c227576c255a", "parents": [ "c7984f4e4e3af3bf8027d636283ea8658c7f80b9" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 28 14:44:04 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:55 2009 -0700" }, "message": "ioat1: move descriptor allocation from submit to prep\n\nThe async_tx api assumes that after a successful -\u003eprep a subsequent\n-\u003esubmit will not fail due to a lack of resources.\n\nThis also fixes a bug in the allocation failure case. Previously the\ndescriptors allocated prior to the allocation failure would not be\nreturned to the free list.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "c7984f4e4e3af3bf8027d636283ea8658c7f80b9", "tree": "81fb1adc44173505d447aa93142cc96a4bf03044", "parents": [ "77867fff033ea549096c49d863c564ad7d8be36f" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 28 14:44:04 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:55 2009 -0700" }, "message": "ioat: define descriptor control bit-field\n\nThis cleans up a mess of and\u0027ing and or\u0027ing bit definitions, and allows\nsimple assignments from the specified dma_ctrl_flags parameter.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "77867fff033ea549096c49d863c564ad7d8be36f", "tree": "d39bce48f29aa9ce6f23f15e73fab8333d91bc75", "parents": [ "f2427e276ffec5ce599c6bc116e0927269a360ef" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 28 14:44:04 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:54 2009 -0700" }, "message": "ioat: fix type mismatch for -\u003edmacount\n\n-\u003edmacount tracks the sequence number of active descriptors. It is\nwritten to the DMACOUNT register to update the channel\u0027s view of pending\ndescriptors in the chain. The register is 16-bits so -\u003edmacount should\nbe unsigned and 16-bit as well. Also modify -\u003edesccount to maintain\nalignment.\n\nThis was never a problem in practice because we never compared dmacount\nvalues, but this is a bug waiting to happen.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "f2427e276ffec5ce599c6bc116e0927269a360ef", "tree": "d23b47ad7a00daeba720c25bb900fd96bf226f54", "parents": [ "b31b78f1ab7806759622b703357e39a21f757281" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 28 14:42:38 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:54 2009 -0700" }, "message": "ioat: split ioat_dma_probe into core/version-specific routines\n\nTowards the removal of ioatdma_device.version split the initialization\npath into distinct versions. This conversion:\n1/ moves version specific probe code to version specific routines\n2/ removes the need for ioat_device\n3/ turns off the ioat1 msi quirk if the device is reinitialized for intx\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "b31b78f1ab7806759622b703357e39a21f757281", "tree": "70144a699561184ed9d7bcd0b0f8f2b102204947", "parents": [ "bc3c70258526a635325f1f15138a96297879bc1a" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 28 14:42:32 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:54 2009 -0700" }, "message": "ioat: kill function prototype ifdef guards\n\nThe only .c files that utilize these protected prototypes depend on\nCONFIG_INTEL_IOATDMA\u003dy, so there is no value gained in providing empty\nprototypes.\n\n[ Impact: pure cleanup ]\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "bc3c70258526a635325f1f15138a96297879bc1a", "tree": "65ced583f975cb19dc12f498f7e97536033fe74f", "parents": [ "e6c0b69a43150c1a37cf342ce5faedf12583bf79" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 28 14:33:42 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:54 2009 -0700" }, "message": "ioat: cleanup some long deref chains and 80 column collisions\n\n* reduce device-\u003ecommon. to dma-\u003e in ioat_dma_{probe,remove,selftest}\n* ioat_lookup_chan_by_index to ioat_chan_by_index\n* multi-line function definitions\n* ioat_desc_sw.async_tx to ioat_desc_sw.txd\n* desc-\u003etxd. to tx-\u003e in cleanup routine\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n" }, { "commit": "e6c0b69a43150c1a37cf342ce5faedf12583bf79", "tree": "955456982fea62d6557ad5992f19ee3e73e64bc2", "parents": [ "1f27adc2f050836c12deb4d99afe507636537a0b" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:44 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:44 2009 -0700" }, "message": "ioat: convert ioat_probe to pcim/devm\n\nThe driver currently duplicates much of what these routines offer, so\njust use the common code. For example -\u003eirq_mode tracks what interrupt\nmode was initialized, which duplicates the -\u003emsix_enabled and\n-\u003emsi_enabled handling in pcim_release.\n\nThis also adds a check to the return value of dma_async_device_register,\nwhich can fail.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" }, { "commit": "1f27adc2f050836c12deb4d99afe507636537a0b", "tree": "aeb0b1a0896dd1367174a46d29c7ebc18187a4f9", "parents": [ "584ec22759c06cdfc189c03a727f20038526245b" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:02 2009 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Sep 08 17:29:02 2009 -0700" }, "message": "ioat: move definitions to dma.h\n\nSome of these defines may be useful outside of dma.c and the header is\nprivate so there are no namespace pollution concerns.\n\nSigned-off-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n" } ], "next": "a348a7e6fdbcd2d5192a09719a479bb238fde727" }