)]}' { "log": [ { "commit": "44f2c586a3553154bc6549eb696c7716c85f910b", "tree": "1050bd39b5fd1d67c63dddd939223b60ad7f9a44", "parents": [ "fcc152f3bf55cec61167b173774cbf717b0ff5e4" ], "author": { "name": "Manuel Lauss", "email": "manuel.lauss@googlemail.com", "time": "Wed Oct 14 12:22:20 2009 +0200" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Nov 02 12:00:08 2009 +0100" }, "message": "MIPS: Alchemy: Fix hang with high-frequency edge interrupts\n\nThe handle_edge_irq() flowhandler disables edge int sources which occur\ntoo fast (i.e. another edge comes in before the irq handler function\nhad a chance to finish). Currently, the mask_ack() callback does not\nack the edges in hardware, leading to an endless loop in the flowhandler\nwhere it tries to shut up the irq source.\n\nWhen I rewrote the alchemy IRQ code I wrongly assumed the mask_ack()\ncallback was only used by the level flowhandler, hence it omitted the\n(at the time pointless) edge acks. Turned out I was wrong; so here\nis a complete mask_ack implementation for Alchemy IC, which fixes\nthe above mentioned problem.\n\nSigned-off-by: Manuel Lauss \u003cmanuel.lauss@gmail.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "39d2211d20518677511043d7ee16bbca6d0c5070", "tree": "fb34bae6372c6752543fae8aa716d84c1f7992cb", "parents": [ "72838a170372d6bb44bcb04a81aa2c83312cfbc0" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Oct 12 02:23:48 2009 +0200" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Nov 02 12:00:04 2009 +0100" }, "message": "MIPS: MTX-1: Fix build if CONFIG_PCI is disabled.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "c2e32149074501fc12f6e05f85812e07148a2276", "tree": "28aac84c5d0a79c11b2050c050ab511c1a661183", "parents": [ "eef34ec514054e4685745236dd5c9658f7aca69e" ], "author": { "name": "Roel Kluin", "email": "roel.kluin@gmail.com", "time": "Fri Sep 18 12:50:10 2009 -0700" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Wed Sep 30 21:47:01 2009 +0200" }, "message": "MIPS: Decrease size of au1xxx_dbdma_pm_regs[][]\n\nThere are 16 individual channels (NUM_DBDMA_CHANS) to save/restore plus the\nglobal ddma block config (the +1). The last register in a channel can be\nskipped since it\u0027s read-only (at offset 0x18).\n\nSigned-off-by: Roel Kluin \u003croel.kluin@gmail.com\u003e\nCc: Manuel Lauss \u003cmanuel.lauss@googlemail.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "51c870a2d8708bda83c4ba47f26012a8420bdaff", "tree": "7fd59e523a186552d02a2bea9d64dcf8cd776af1", "parents": [ "a0219d948dd712561817b0d7c95fd2f10b698203" ], "author": { "name": "Rusty Russell", "email": "rusty@rustcorp.com.au", "time": "Thu Sep 24 09:34:35 2009 -0600" }, "committer": { "name": "Rusty Russell", "email": "rusty@rustcorp.com.au", "time": "Thu Sep 24 09:34:36 2009 +0930" }, "message": "cpumask: remove dangerous CPU_MASK_ALL_PTR, \u0026CPU_MASK_ALL.: mips\n\n(Thanks to Al Viro for reminding me of this, via Ingo)\n\nCPU_MASK_ALL is the (deprecated) \"all bits set\" cpumask, defined as so:\n\n\t#define CPU_MASK_ALL (cpumask_t) { { ... } }\n\nTaking the address of such a temporary is questionable at best,\nunfortunately 321a8e9d (cpumask: add CPU_MASK_ALL_PTR macro) added\nCPU_MASK_ALL_PTR:\n\n\t#define CPU_MASK_ALL_PTR (\u0026CPU_MASK_ALL)\n\nWhich formalizes this practice. One day gcc could bite us over this\nusage (though we seem to have gotten away with it so far).\n\nSo replace everywhere which used \u0026CPU_MASK_ALL or CPU_MASK_ALL_PTR\nwith the modern \"cpu_all_mask\" (a real struct cpumask *), and remove\nCPU_MASK_ALL_PTR altogether.\n\nSigned-off-by: Rusty Russell \u003crusty@rustcorp.com.au\u003e\nAcked-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nReported-by: Al Viro \u003cviro@zeniv.linux.org.uk\u003e\nCc: Mike Travis \u003ctravis@sgi.com\u003e\n" }, { "commit": "a7bcb1ae6094db78b077ae17e92c69de7643014f", "tree": "b59e32e51c84bcc69a9458fa8b7bc8d11286dea0", "parents": [ "f7557dc8215a2e7eb22da583d03e1aef72c58b3c" ], "author": { "name": "Manuel Lauss", "email": "manuel.lauss@googlemail.com", "time": "Thu Aug 27 19:21:18 2009 +0200" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Sep 17 20:07:51 2009 +0200" }, "message": "MIPS: Alchemy: override loops_per_jiffy detection\n\nloops_per_jiffy depends on coreclk speed; preset it instead of\nletting the kernel waste precious microseconds trying to approximate it.\n\nSigned-off-by: Manuel Lauss \u003cmanuel.lauss@gmail.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "2882b0c63ac6085fd5c18959240b6f7d6ffb8d5b", "tree": "a95571203336aaec43dd505c81ab7dc8e46efa78", "parents": [ "9d24bafb0d1ecf636f71a56f9d6f071f5c7a882d" ], "author": { "name": "Manuel Lauss", "email": "manuel.lauss@googlemail.com", "time": "Sat Aug 22 18:09:27 2009 +0200" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Sep 17 20:07:50 2009 +0200" }, "message": "MIPS: Alchemy: get rid of allow_au1k_wait\n\nEliminate the \u0027allow_au1k_wait\u0027 variable. MIPS kernel installs the\nAlchemy-specific wait code before timer initialization; if the C0\ntimer must be used for timekeeping the wait function is set to NULL\nwhich means no wait implementation is available.\n\nAs a sideeffect, the \u0027wait instruction available\u0027 output in\n/proc/cpuinfo now correctly indicates whether \u0027wait\u0027 is usable.\n\nRun-tested on DB1200.\n\nSigned-off-by: Manuel Lauss \u003cmanuel.lauss@gmail.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "a1b021d3992d9be03b0abec1a7ed78e713b94206", "tree": "d6928ff79743aa275d6088f1db5abff6c75fd862", "parents": [ "619e22632ea3110323b1851a7fecb52bf8505fd2" ], "author": { "name": "Florian Fainelli", "email": "florian@openwrt.org", "time": "Sat Aug 01 23:51:20 2009 +0200" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Aug 03 17:52:46 2009 +0100" }, "message": "MIPS: MTX-1: Request button GPIO before setting its direction\n\nThis patch fixes the following warning at boot time:\nWARNING: at drivers/gpio/gpiolib.c:83 0x8021d5e0()\nautorequest GPIO-207\nModules linked in:\nCall Trace:[\u003c8011e0ec\u003e] 0x8011e0ec\n[\u003c80110a28\u003e] 0x80110a28\n[\u003c80110a28\u003e] 0x80110a28\n[..snip..]\n\nThe current code does not request the GPIO and attempts\nto set its direction, which is a violation of the GPIO API.\nThis patch also unhardcode the GPIO we request and use\nthe one we defined in the button driver.\n\nSigned-off-by: Florian Fainelli \u003cflorian@openwrt.org\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "ce65cc8fe22a572ea9ec88e203388558b6b863af", "tree": "26cafa2f81be0f44fac4142e40bb1596c58040cd", "parents": [ "b6c9f10517e99d806bebd04555801c787b9a3a23" ], "author": { "name": "Manuel Lauss", "email": "manuel.lauss@googlemail.com", "time": "Sat Jun 06 14:09:58 2009 +0200" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Wed Jun 17 11:06:29 2009 +0100" }, "message": "MIPS: Alchemy: devboards: Convert to gpio calls.\n\nReplace a few open-coded GPIO register accesses with gpio calls.\n\nSigned-off-by: Manuel Lauss \u003cmanuel.lauss@gmail.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "b6c9f10517e99d806bebd04555801c787b9a3a23", "tree": "381146f79bd66dcd5b83635462c99c14d25b5469", "parents": [ "bb706b28bbd647c2fd7f22d6bf03a18b9552be05" ], "author": { "name": "Manuel Lauss", "email": "manuel.lauss@googlemail.com", "time": "Sat Jun 06 14:09:57 2009 +0200" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Wed Jun 17 11:06:29 2009 +0100" }, "message": "MIPS: Alchemy: xxs1500: use linux gpio api.\n\nReplace a few GPIO register accesses in the board init code with calls to\nthe gpio api.\n\nSigned-off-by: Manuel Lauss \u003cmanuel.lauss@gmail.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "bb706b28bbd647c2fd7f22d6bf03a18b9552be05", "tree": "d3665800f631759b923de1a0083bd2483babee4b", "parents": [ "51e02b02e650183ff1277bcbad6a01d6ea0e9edb" ], "author": { "name": "Manuel Lauss", "email": "manuel.lauss@googlemail.com", "time": "Sat Jun 06 14:09:56 2009 +0200" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Wed Jun 17 11:06:28 2009 +0100" }, "message": "MIPS: Alchemy: MTX-1: Use linux gpio api.\n\nReplace a few GPIO register accesses in the board init code with calls\nto the gpio api.\n\nSigned-off-by: Manuel Lauss \u003cmanuel.lauss@gmail.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "51e02b02e650183ff1277bcbad6a01d6ea0e9edb", "tree": "413dfa5c93e2d01a42309f1cee6d6bf26d871962", "parents": [ "eeb09e6545bf68222798ccf3f355560a9e406435" ], "author": { "name": "Manuel Lauss", "email": "manuel.lauss@googlemail.com", "time": "Sat Jun 06 14:09:55 2009 +0200" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Wed Jun 17 11:06:28 2009 +0100" }, "message": "MIPS: Alchemy: Rewrite GPIO support.\n\nThe current in-kernel Alchemy GPIO support is far too inflexible for\nall my use cases. To address this, the following changes are made:\n\n* create generic functions which deal with manipulating the on-chip\n GPIO1/2 blocks. Such functions are universally useful.\n* Macros for GPIO2 shared interrupt management and block control.\n* support for both built-in CONFIG_GPIOLIB and fast, inlined GPIO macros.\n\n If CONFIG_GPIOLIB is not enabled, provide linux gpio framework\n compatibility by directly inlining the GPIO1/2 functions. GPIO access\n is limited to on-chip ones and they can be accessed as documented in\n the datasheets (GPIO0-31 and 200-215).\n\n If CONFIG_GPIOLIB is selected, two (2) gpio_chip-s, one for GPIO1 and\n one for GPIO2, are registered. GPIOs can still be accessed by using\n the numberspace established in the databooks.\n\n However this is not yet flexible enough for my uses: My Alchemy\n systems have a documented \"external\" gpio interface (fixed, different\n numberspace) and can support a variety of baseboards, some of which\n are equipped with I2C gpio expanders. I want to be able to provide\n the default 16 GPIOs of the CPU board numbered as 0..15 and also\n support gpio expanders, if present, starting as gpio16.\n\n To achieve this, a new Kconfig symbol for Alchemy is introduced,\n CONFIG_ALCHEMY_GPIO_INDIRECT, which boards can enable to signal\n that they don\u0027t want the Alchemy numberspace exposed to the outside\n world, but instead want to provide their own. Boards are now respon-\n sible for providing the linux gpio interface glue code (either in a\n custom gpio.h header (in board include directory) or with gpio_chips).\n\n To make the board-specific inlined gpio functions work, the MIPS\n Makefile must be changed so that the mach-au1x00/gpio.h header is\n included _after_ the board headers, by moving the inclusion of\n the mach-au1x00/ to the end of the header list.\n\n See arch/mips/include/asm/mach-au1x00/gpio.h for more info.\n\nSigned-off-by: Manuel Lauss \u003cmanuel.lauss@gmail.com\u003e\nAcked-by: Florian Fainelli \u003cflorian@openwrt.org\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "ad058e95f943e26205aa916b83b85ccb21bd4812", "tree": "0dd16ccb9ea079517ec8cb509a597f997a031092", "parents": [ "237e5a3443e5531336b880bbaf3e7bac110330f7" ], "author": { "name": "Manuel Lauss", "email": "mano@roarinelk.homelinux.net", "time": "Wed Apr 22 08:01:48 2009 +0200" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu May 14 13:50:27 2009 +0100" }, "message": "MIPS: Alchemy: Timer build fix\n\nFix breakage introduced by 8e19608e8b5c001e4a66ce482edc474f05fb7355.\n\nSigned-off-by: Manuel Lauss \u003cmano@roarinelk.homelinux.net\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "284901a90a9e0b812ca3f5f852cbbfb60d10249d", "tree": "06c1b5a0f83c90cfb662f756e7781977ce739ce8", "parents": [ "6afd142fd0dfba497246d0fab236c20a7b4bf778" ], "author": { "name": "Yang Hongyang", "email": "yanghy@cn.fujitsu.com", "time": "Mon Apr 06 19:01:15 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Apr 07 08:31:11 2009 -0700" }, "message": "dma-mapping: replace all DMA_32BIT_MASK macro with DMA_BIT_MASK(32)\n\nReplace all DMA_32BIT_MASK macro with DMA_BIT_MASK(32)\n\nSigned-off-by: Yang Hongyang\u003cyanghy@cn.fujitsu.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "91e8a30e90144bcd0fead02dc57976f304c3b3f7", "tree": "59877a38f8aaac8bc14c5f184a860f16b7a21785", "parents": [ "2f794d099da2f081de2fe19b289a3aa807f735fa" ], "author": { "name": "Manuel Lauss", "email": "mano@roarinelk.homelinux.net", "time": "Wed Mar 25 17:49:31 2009 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Mar 30 14:49:46 2009 +0200" }, "message": "MIPS: Alchemy: PB1200: use SMC91X platform data.\n\nAdd platform data for the smc91x on the PB1200/DB1200, and remove the\nnow unused AU1X00 entry in smc91x.h.\n\nSigned-off-by: Manuel Lauss \u003cmano@roarinelk.homelinux.net\u003e\n" }, { "commit": "c87e09096dcd1ea3da8dfe434ee694fac51031c8", "tree": "d988b5b545173c79ac013977720d62c7d26ec337", "parents": [ "3e168ae286f5203d4b4aae0ae15c0d6282bcdd21" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Mar 30 14:49:44 2009 +0200" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Mar 30 14:49:44 2009 +0200" }, "message": "MIPS: Enable GENERIC_HARDIRQS_NO__DO_IRQ for all platforms\n\n__do_IRQ() is deprecated and will go away.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "47c969ee54e142eba71626f99b3d99cc461b84f3", "tree": "79f23092fd31e4482477958a2b5fa081b7000d8a", "parents": [ "12e22e8e60add9e1ccd61509ab7fd6fc1c214c52" ], "author": { "name": "Florian Fainelli", "email": "florian@openwrt.org", "time": "Thu Jan 15 16:46:48 2009 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Mar 30 14:49:42 2009 +0200" }, "message": "MIPS: Au1000: convert to using gpiolib\n\nThis patch converts the GPIO board code to use gpiolib.\n\nSigned-off-by: Florian Fainelli \u003cflorian@openwrt.org\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "4b0d3f5c28c631c1aeb1860993572ad8468a4c11", "tree": "e12e6539b552017947a04c0feca6d02ae9cfd2fc", "parents": [ "5e6833892e7b745b164bae8b2edb75ccd1bee866" ], "author": { "name": "Roel Kluin", "email": "roel.kluin@gmail.com", "time": "Sat Jan 31 12:23:34 2009 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Feb 27 17:56:34 2009 +0000" }, "message": "MIPS: Alchemy: In plat_time_init() t reaches -1, tested: 0\n\nWith a postfix decrement t reaches -1 rather than 0, so the fall-back will\nnot occur.\n\nSigned-off-by: Roel Kluin \u003croel.kluin@gmail.com\u003e\nCc: mano@roarinelk.homelinux.net\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "2d2eca4d11933bd37a4944aae06e6122efffaea8", "tree": "25d12fdc96b247981fbe5de5b15e4146acbdc984", "parents": [ "0fc6bc0d6e953f6dd80c286c889d8d581e8f8d7a" ], "author": { "name": "Manuel Lauss", "email": "mano@roarinelk.homelinux.net", "time": "Tue Jan 06 10:34:52 2009 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Jan 30 21:33:01 2009 +0000" }, "message": "MIPS: Alchemy: time.c build fix\n\nIn Linus\u0027 current -git the cpumask member is now a pointer.\n\nSigned-off-by: Manuel Lauss \u003cmano@roarinelk.homelinux.net\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "61f9c58da57a80b0df1ced18a28cbbaebd4d417a", "tree": "cbeaa2353d98899e88c6d44dc8d1a16eabbb6a47", "parents": [ "ac15dad061d351281b0bafbae1ecdd84e601435a" ], "author": { "name": "Manuel Lauss", "email": "mano@roarinelk.homelinux.net", "time": "Sun Dec 21 09:26:27 2008 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sun Jan 11 09:57:27 2009 +0000" }, "message": "MIPS: Alchemy: new userspace suspend interface for development boards.\n\nReplace the current sysctl-based suspend interface with a new sysfs-\nbased one which also uses the Linux-2.6 suspend model.\n\nTo configure wakeup sources, a subtree for the demoboards is created\nunder /sys/power/db1x:\n\nsys/\n`-- power\n `-- db1x\n |-- gpio0\n |-- gpio1\n |-- gpio2\n |-- gpio3\n |-- gpio4\n |-- gpio5\n |-- gpio6\n |-- gpio7\n |-- timer\n |-- timer_timeout\n |-- wakemsk\n `-- wakesrc\n\nThe nodes \u0027gpio[0-7]\u0027 and \u0027timer\u0027 configure the GPIO0..7 and M2\nbits of the SYS_WAKEMSK (wakeup source enable) register. Writing \u00271\u0027\nenables a wakesource, 0 disables it.\n\nThe \u0027timer_timeout\u0027 node holds the timeout in seconds after which the\nTOYMATCH2 event should wake the system.\n\nThe \u0027wakesrc\u0027 node holds the SYS_WAKESRC register after wakeup (in hex),\nthe \u0027wakemsk\u0027 node can be used to get/set the wakeup mask directly.\n\nFor example, to have the timer wake the system after 10 seconds of sleep,\nthe following must be done in userspace:\n\necho 10 \u003e /sys/power/db1x/timer_timeout\necho 1 \u003e /sys/power/db1x/timer\necho mem \u003e /sys/power/sleep\n\nThis patch also removes the homebrew CPU frequency switching code. I don\u0027t\nunderstand how it could have ever worked reliably; it does not communicate\nthe clock changes to peripheral devices other than uarts.\n\nSigned-off-by: Manuel Lauss \u003cmano@roarinelk.homelinux.net\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n\n create mode 100644 arch/mips/alchemy/devboards/pm.c\n" }, { "commit": "ac15dad061d351281b0bafbae1ecdd84e601435a", "tree": "dc5536f68f14e3a07f3af1105cfc23a2c317f21f", "parents": [ "564365b0fc3395ed55501ef25705664888cebdbc" ], "author": { "name": "Manuel Lauss", "email": "mano@roarinelk.homelinux.net", "time": "Sun Dec 21 09:26:26 2008 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sun Jan 11 09:57:27 2009 +0000" }, "message": "MIPS: Alchemy: dbdma suspend/resume support.\n\nImplement suspend/resume for DBDMA controller and its channels.\n\nSigned-off-by: Manuel Lauss \u003cmano@roarinelk.homelinux.net\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "564365b0fc3395ed55501ef25705664888cebdbc", "tree": "ed2228df7ea13585f014937b4fc0a6cd7138a674", "parents": [ "2699cdfb765c3b7d77d28ea3bc7d84e486697177" ], "author": { "name": "Manuel Lauss", "email": "mano@roarinelk.homelinux.net", "time": "Sun Dec 21 09:26:25 2008 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sun Jan 11 09:57:27 2009 +0000" }, "message": "MIPS: Alchemy: Fix up PM code on Au1550/Au1200\n\nAu1550/Au1200 have a different memory controller which requires additi-\nonal code to properly put memory to sleep (code taken from AMD/RMI\u0027s\nLinux-2.6.11 source package).\n\nAlso fix up the remaining pm-related paths to compile on Au1200/Au1550\nplatforms.\n\nSigned-off-by: Manuel Lauss \u003cmano@roarinelk.homelinux.net\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "2699cdfb765c3b7d77d28ea3bc7d84e486697177", "tree": "690eb6e847c7acfc0a5693a385907da480f33fd8", "parents": [ "0c694de12b54fa96b9555e07603f567906ce21c8" ], "author": { "name": "Manuel Lauss", "email": "mano@roarinelk.homelinux.net", "time": "Sun Dec 21 09:26:24 2008 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sun Jan 11 09:57:27 2009 +0000" }, "message": "MIPS: Alchemy: move calc_clock function.\n\nNow that nothing in time.c depends on calc_clock, it can\nbe moved to clocks.c where it belongs.\nWhile at it, give it a better non-generic name and call it\nas soon as possible in plat_mem_init.\n\nSigned-off-by: Manuel Lauss \u003cmano@roarinelk.homelinux.net\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "0c694de12b54fa96b9555e07603f567906ce21c8", "tree": "c7528273c1d86069cb6e83bd2b36706f663f1eb2", "parents": [ "779e7d41ad004946603da139da99ba775f74cb1c" ], "author": { "name": "Manuel Lauss", "email": "mano@roarinelk.homelinux.net", "time": "Sun Dec 21 09:26:23 2008 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sun Jan 11 09:57:27 2009 +0000" }, "message": "MIPS: Alchemy: RTC counter clocksource / clockevent support.\n\nAdd support for the 32 kHz counter1 (RTC) as clocksource / clockevent\ndevice. As a nice side effect, this also enables use of the \u0027wait\u0027\ninstruction for runtime idle power savings.\n\nIf the counters aren\u0027t enabled/working properly, fall back on the\ncp0 counter clock code.\n\nSigned-off-by: Manuel Lauss \u003cmano@roarinelk.homelinux.net\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "074cf656700ddd1d2bd7f815f78e785418beb898", "tree": "af55e5f9d36775df851924303e44fdde7cff8654", "parents": [ "1820ec1d2b993f3ec00169e881504aa4541a9bf7" ], "author": { "name": "Manuel Lauss", "email": "mano@roarinelk.homelinux.net", "time": "Sun Dec 21 09:26:21 2008 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sun Jan 11 09:57:26 2009 +0000" }, "message": "MIPS: Alchemy: remove cpu_table.\n\nRemove the cpu_table:\n- move detection of whether c0_config[OD] is read-only and should be set\n to fix various chip errata to au1000 headers.\n- move detection of write-only sys_cpupll to au1000 headers.\n- remove the BCLK switching code: Activation of this features should be\n left to the boards using the chips since it also affects external devices\n tied to BCLK, and only the board designers know whether it is safe to\n enable.\n\nSigned-off-by: Manuel Lauss \u003cmano@roarinelk.homelinux.net\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n\n delete mode 100644 arch/mips/alchemy/common/cputable.c\n" }, { "commit": "1820ec1d2b993f3ec00169e881504aa4541a9bf7", "tree": "18c7250dd41b227a2d8224a617793f33a09d783e", "parents": [ "558d1de8ba9ebb1cc3f3062f1371b9330772164f" ], "author": { "name": "Manuel Lauss", "email": "mano@roarinelk.homelinux.net", "time": "Sun Dec 21 09:26:20 2008 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sun Jan 11 09:57:26 2009 +0000" }, "message": "MIPS: Alchemy: remove get/set_au1x00_lcd_clock().\n\nThere are no in-tree users, so remove them.\n\nSigned-off-by: Manuel Lauss \u003cmano@roarinelk.homelinux.net\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "197b0d31eb3e82f598bf13da6ee777d906c611f3", "tree": "663ecf85c0096a695f425bb602012ea7ca9e57de", "parents": [ "785e3268e2951d4c0c21417c8e5d8004b2ab2480" ], "author": { "name": "Manuel Lauss", "email": "mano@roarinelk.homelinux.net", "time": "Sun Dec 21 09:26:18 2008 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sun Jan 11 09:57:26 2009 +0000" }, "message": "MIPS: Alchemy: pb1200: update CPLD cascade irq handler.\n\nTested on Db1200.\n\nSigned-off-by: Manuel Lauss \u003cmano@roarinelk.homelinux.net\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "785e3268e2951d4c0c21417c8e5d8004b2ab2480", "tree": "3e7e98dbaf2592f22f65090325a823d36caa13f7", "parents": [ "7179380ee9bdeb5fa2ff07581f512fe0f5382e5b" ], "author": { "name": "Manuel Lauss", "email": "mano@roarinelk.homelinux.net", "time": "Sun Dec 21 09:26:17 2008 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sun Jan 11 09:57:26 2009 +0000" }, "message": "MIPS: Alchemy: update core interrupt code.\n\nThis patch attempts to modernize core Alchemy interrupt handling code.\n\n- add irq_chips for irq controllers instead of irq type,\n- add a set_type() hook to change irq trigger type during runtime,\n- add a set_wake() hook to control GPIO0..7 based wakeup,\n- use linux\u0027 IRQF_TRIGGER_ constants instead of homebrew ones,\n- enable GENERIC_HARDIRQS_NO__DO_IRQ.\n- simplify plat_irq_dispatch\n- merge au1xxx_irqmap into irq.c file, the only place where its\n contents are referenced.\n- board_init_irq() is now mandatory for every board; use it to register\n the remaining (gpio-based) interrupt sources; update all boards\n accordingly.\n\nRun-tested on Db1200 and other Au1200 based platforms.\n\nSigned-off-by: Manuel Lauss \u003cmano@roarinelk.homelinux.net\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n\n delete mode 100644 arch/mips/alchemy/common/au1xxx_irqmap.c\n" }, { "commit": "7179380ee9bdeb5fa2ff07581f512fe0f5382e5b", "tree": "12bc5c0cfc3506434b0e51829bbbb66aaadf491a", "parents": [ "23ba25d56606eec6fabc37c1efcbd48837dc9adc" ], "author": { "name": "Manuel Lauss", "email": "mano@roarinelk.homelinux.net", "time": "Sun Dec 21 09:26:16 2008 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sun Jan 11 09:57:25 2009 +0000" }, "message": "MIPS: Alchemy: move commandline mangling out of common code\n\nNot every alchemy-based board might want these options forced on it,\nand most of this stuff seems to be intended for devboard code anyway.\nRemove commandline mangling code out of common chip code and instead\nadd relevant sections to all in-tree boards to not change existing\nbehaviour.\n\nSigned-off-by: Manuel Lauss \u003cmano@roarinelk.homelinux.net\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "23ba25d56606eec6fabc37c1efcbd48837dc9adc", "tree": "b034fe449d8896d2718cc088f54e91470ae258ee", "parents": [ "58e75e86cf9af1130b3c628d924e6df0bc72832f" ], "author": { "name": "Manuel Lauss", "email": "mano@roarinelk.homelinux.net", "time": "Sun Dec 21 09:26:15 2008 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sun Jan 11 09:57:25 2009 +0000" }, "message": "MIPS: Alchemy: devboards: consolidate files\n\nShare some code and merge small files:\n- Extract the prom init code from all devboard files (they only differ in\n memory configuration).\n- Merge the irq configuration into board setup code.\n- Merge smaller files into board setup code.\n\nSigned-off-by: Manuel Lauss \u003cmano@roarinelk.homelinux.net\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n\n delete mode 100644 arch/mips/alchemy/devboards/db1x00/init.c\n delete mode 100644 arch/mips/alchemy/devboards/pb1000/init.c\n delete mode 100644 arch/mips/alchemy/devboards/pb1000/irqmap.c\n delete mode 100644 arch/mips/alchemy/devboards/pb1100/init.c\n delete mode 100644 arch/mips/alchemy/devboards/pb1100/irqmap.c\n delete mode 100644 arch/mips/alchemy/devboards/pb1200/init.c\n delete mode 100644 arch/mips/alchemy/devboards/pb1500/init.c\n delete mode 100644 arch/mips/alchemy/devboards/pb1500/irqmap.c\n delete mode 100644 arch/mips/alchemy/devboards/pb1550/init.c\n delete mode 100644 arch/mips/alchemy/devboards/pb1550/irqmap.c\n create mode 100644 arch/mips/alchemy/devboards/prom.c\n" }, { "commit": "58e75e86cf9af1130b3c628d924e6df0bc72832f", "tree": "0c3e7511671a74ba5302aa5edbe2695cfbdee9ed", "parents": [ "a86c7f72454c4e855d5d6c80ed9f7f2ac55b001a" ], "author": { "name": "Manuel Lauss", "email": "mano@roarinelk.homelinux.net", "time": "Sun Dec 21 09:26:14 2008 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sun Jan 11 09:57:25 2009 +0000" }, "message": "MIPS: Alchemy: Move development board code to common subdirectory\n\nThis should ease sharing of common devboard code.\n\nSigned-off-by: Manuel Lauss \u003cmano@roarinelk.homelinux.net\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "2bd2dd059ca7406a030bace8dccdb25f635578c1", "tree": "505426d1faa78e128eb4aedd2cc7c4b384979d4c", "parents": [ "797c3f322454f5994e88b0e0bfc34cd4ad521d38" ], "author": { "name": "Julia Lawall", "email": "julia@diku.dk", "time": "Tue Nov 25 14:12:32 2008 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sun Jan 11 09:57:19 2009 +0000" }, "message": "MIPS: Alchemy: Change strict_strtol to strict_strtoul\n\nSince memsize is unsigned, it would seem better to use strict_strtoul that\nstrict_strtol.\n\nA simplified version of the semantic patch that makes this change is as\nfollows: (http://www.emn.fr/x-info/coccinelle/)\n\n// \u003csmpl\u003e\n@s2@\nlong e;\nposition p;\n@@\n\nstrict_strtol@p(...,\u0026e)\n\n@@\nposition p !\u003d s2.p;\ntype T;\nT e;\n@@\n\n- strict_strtol@p\n+ strict_strtoul\n (...,\u0026e)\n// \u003c/smpl\u003e\n\nSigned-off-by: Julia Lawall \u003cjulia@diku.dk\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "f591eb1e6896e26675e91a319cc93f3800dbaad4", "tree": "c3f925431a393b59e5fc9bee2ea77ac596ae19cc", "parents": [ "fa36b04386422951a7c73f9210403d1a2eaffe92" ], "author": { "name": "Manuel Lauss", "email": "mano@roarinelk.homelinux.net", "time": "Tue Oct 21 08:59:14 2008 +0200" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Mon Oct 27 16:18:27 2008 +0000" }, "message": "MIPS: Alchemy: Wire up SD controller on DB/PB1200 boards.\n\nAdd au1xmmc platform data for PB1200/DB1200 boards and wire up the 2 SD\ncontrollers for them.\n\nSigned-off-by: Manuel Lauss \u003cmano@roarinelk.homelinux.net\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "e8c7c482347574ecdd45c43e32c332d5fc2ece61", "tree": "c741aa6cdb4e897df9f9476d83a816a7a2b058dd", "parents": [ "8d2d91e86b4153cc2305ec86fe908048f459ff7f" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Sep 16 19:12:16 2008 +0200" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Sat Oct 11 16:18:50 2008 +0100" }, "message": "MIPS: Alchemy: rename directory\n\nIt\u0027s more than the au1000 these days.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" } ] }