)]}'
{
  "log": [
    {
      "commit": "6faf17f6f1ffc586d16efc2f9fa2083a7785ee74",
      "tree": "383d4a10cdc0b02bd8bc3a873613a68a06748cd7",
      "parents": [
        "adda766193ea1cf3137484a9521972d080d0b7af"
      ],
      "author": {
        "name": "Chris Wright",
        "email": "chrisw@sous-sol.org",
        "time": "Fri Aug 28 13:00:06 2009 -0700"
      },
      "committer": {
        "name": "Jesse Barnes",
        "email": "jbarnes@virtuousgeek.org",
        "time": "Sun Aug 30 08:37:25 2009 -0700"
      },
      "message": "PCI SR-IOV: correct broken resource alignment calculations\n\nAn SR-IOV capable device includes an SR-IOV PCIe capability which\ndescribes the Virtual Function (VF) BAR requirements.  A typical SR-IOV\ndevice can support multiple VFs whose BARs must be in a contiguous region,\neffectively an array of VF BARs.  The BAR reports the size requirement\nfor a single VF.  We calculate the full range needed by simply multiplying\nthe VF BAR size with the number of possible VFs and create a resource\nspanning the full range.\n\nThis all seems sane enough except it artificially inflates the alignment\nrequirement for the VF BAR.  The VF BAR need only be aligned to the size\nof a single BAR not the contiguous range of VF BARs.  This can cause us\nto fail to allocate resources for the BAR despite the fact that we\nactually have enough space.\n\nThis patch adds a thin PCI specific layer over the generic\nresource_alignment() function which is aware of the special nature of\nVF BARs and does sorting and allocation based on the smaller alignment\nrequirement.\n\nI recognize that while resource_alignment is generic, it\u0027s basically a\nPCI helper.  An alternative to this patch is to add PCI VF BAR specific\ninformation to struct resource.  I opted for the extra layer rather than\nadding such PCI specific information to struct resource.  This does\nhave the slight downside that we don\u0027t cache the BAR size and re-read\nfor each alignment query (happens a small handful of times during boot\nfor each VF BAR).\n\nSigned-off-by: Chris Wright \u003cchrisw@sous-sol.org\u003e\nCc: Ivan Kokshaysky \u003cink@jurassic.park.msu.ru\u003e\nCc: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\nCc: Matthew Wilcox \u003cmatthew@wil.cx\u003e\nCc: Yu Zhao \u003cyu.zhao@intel.com\u003e\nCc: stable@kernel.org\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n"
    },
    {
      "commit": "687d680985b1438360a9ba470ece8b57cd205c3b",
      "tree": "ae253608531e5c3e823600974c610e722e7de759",
      "parents": [
        "1053414068bad659479e6efa62a67403b8b1ec0a",
        "008fe148cb0fb51d266baabe2c09997b21cf90c6"
      ],
      "author": {
        "name": "Linus Torvalds",
        "email": "torvalds@linux-foundation.org",
        "time": "Mon Jun 22 21:38:22 2009 -0700"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@linux-foundation.org",
        "time": "Mon Jun 22 21:38:22 2009 -0700"
      },
      "message": "Merge git://git.infradead.org/~dwmw2/iommu-2.6.31\n\n* git://git.infradead.org/~dwmw2/iommu-2.6.31:\n  intel-iommu: Fix one last ia64 build problem in Pass Through Support\n  VT-d: support the device IOTLB\n  VT-d: cleanup iommu_flush_iotlb_psi and flush_unmaps\n  VT-d: add device IOTLB invalidation support\n  VT-d: parse ATSR in DMA Remapping Reporting Structure\n  PCI: handle Virtual Function ATS enabling\n  PCI: support the ATS capability\n  intel-iommu: dmar_set_interrupt return error value\n  intel-iommu: Tidy up iommu-\u003egcmd handling\n  intel-iommu: Fix tiny theoretical race in write-buffer flush.\n  intel-iommu: Clean up handling of \"caching mode\" vs. IOTLB flushing.\n  intel-iommu: Clean up handling of \"caching mode\" vs. context flushing.\n  VT-d: fix invalid domain id for KVM context flush\n  Fix !CONFIG_DMAR build failure introduced by Intel IOMMU Pass Through Support\n  Intel IOMMU Pass Through Support\n\nFix up trivial conflicts in drivers/pci/{intel-iommu.c,intr_remapping.c}\n"
    },
    {
      "commit": "8c1c699fec9e9021bf6ff0285dee086bb27aec90",
      "tree": "4af7bd96c1b651633ff7b6721959aeacd120e4ee",
      "parents": [
        "c465def6bfe834b62623caa9b98f2d4f4739875a"
      ],
      "author": {
        "name": "Yu Zhao",
        "email": "yu.zhao@intel.com",
        "time": "Sat Jun 13 15:52:13 2009 +0800"
      },
      "committer": {
        "name": "Jesse Barnes",
        "email": "jbarnes@virtuousgeek.org",
        "time": "Tue Jun 16 14:30:15 2009 -0700"
      },
      "message": "PCI: cleanup Function Level Reset\n\nThis patch enhances the FLR functions:\n  1) remove disable_irq() so the shared IRQ won\u0027t be disabled.\n  2) replace the 1s wait with 100, 200 and 400ms wait intervals\n     for the Pending Transaction.\n  3) replace mdelay() with msleep().\n  4) add might_sleep().\n  5) lock the device to prevent PM suspend from accessing the CSRs\n     during the reset.\n  6) coding style fixes.\n\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n"
    },
    {
      "commit": "4d135dbee7b0a89e946f7ba284f2b957505a2c3a",
      "tree": "332fb82ad8721cd1c3b8f0260971b2389f76ad5a",
      "parents": [
        "af4c5f985afd8d4cfdf402aaa03677f2cb96e37c"
      ],
      "author": {
        "name": "Yu Zhao",
        "email": "yu.zhao@intel.com",
        "time": "Wed May 20 17:11:57 2009 +0800"
      },
      "committer": {
        "name": "Jesse Barnes",
        "email": "jbarnes@virtuousgeek.org",
        "time": "Thu Jun 11 12:04:20 2009 -0700"
      },
      "message": "PCI: fix SR-IOV function dependency link problem\n\nPCIe root complex integrated endpoint does not implement ARI, so this\nkind of endpoint uses 3-bit function number. The function dependency\nlink of the integrated endpoint should be calculated using the device\nnumber plus the value from function dependency link register.\n\nNormal endpoint always implements ARI and the function dependency link\nregister contains 8-bit function number (i.e. `devfn\u0027 from software\u0027s\nperspective).\n\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n"
    },
    {
      "commit": "e277d2fc79d6abb86fafadb58dca0b9c498a9aa7",
      "tree": "6f7a6c5bf2b300bec9fa76266eeb9089dc82e651",
      "parents": [
        "302b4215daa0a704c843da40fd2529e5757a72da"
      ],
      "author": {
        "name": "Yu Zhao",
        "email": "yu.zhao@intel.com",
        "time": "Mon May 18 13:51:33 2009 +0800"
      },
      "committer": {
        "name": "David Woodhouse",
        "email": "David.Woodhouse@intel.com",
        "time": "Mon May 18 11:25:58 2009 +0100"
      },
      "message": "PCI: handle Virtual Function ATS enabling\n\nThe SR-IOV spec requires that the Smallest Translation Unit and\nthe Invalidate Queue Depth fields in the Virtual Function ATS\ncapability are hardwired to 0. If a function is a Virtual Function,\nthen and set its Physical Function\u0027s STU before enabling the ATS.\n\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n"
    },
    {
      "commit": "302b4215daa0a704c843da40fd2529e5757a72da",
      "tree": "1bc40108fceafd3fbc9faee38c971fa94d560b13",
      "parents": [
        "dd7264355a203c3456dbba04db471947d3b55e7e"
      ],
      "author": {
        "name": "Yu Zhao",
        "email": "yu.zhao@intel.com",
        "time": "Mon May 18 13:51:32 2009 +0800"
      },
      "committer": {
        "name": "David Woodhouse",
        "email": "David.Woodhouse@intel.com",
        "time": "Mon May 18 11:25:54 2009 +0100"
      },
      "message": "PCI: support the ATS capability\n\nThe PCIe ATS capability makes the Endpoint be able to request the\nDMA address translation from the IOMMU and cache the translation\nin the device side, thus alleviate IOMMU pressure and improve the\nhardware performance in the I/O virtualization environment.\n\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n"
    },
    {
      "commit": "52a8873ba4e82d6e87f8478b3e7f9c12d8b37c38",
      "tree": "0af7af907d29c3af3f5b15f24f069aa4312ff76f",
      "parents": [
        "296ccb086dfb89b5b8d73ef08c795ffdff12a597"
      ],
      "author": {
        "name": "Randy Dunlap",
        "email": "randy.dunlap@oracle.com",
        "time": "Wed Apr 01 17:45:30 2009 -0700"
      },
      "committer": {
        "name": "Jesse Barnes",
        "email": "jbarnes@virtuousgeek.org",
        "time": "Mon Apr 06 11:25:33 2009 -0700"
      },
      "message": "PCI-IOV: fix missing kernel-doc\n\nFix PCI iov kernel-doc warning:\n\nWarning(drivers/pci/iov.c:638): No description found for parameter \u0027nr_virtfn\u0027\n\nSigned-off-by: Randy Dunlap \u003crandy.dunlap@oracle.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n"
    },
    {
      "commit": "74bb1bcc7dbbc9ddef773bf3395d7ff92aaaad2e",
      "tree": "38dd25aed251b00a4b34612320beb64f4a058814",
      "parents": [
        "dd7cc44d0bcec5e9c42fe52e88dc254ae62eac8d"
      ],
      "author": {
        "name": "Yu Zhao",
        "email": "yu.zhao@intel.com",
        "time": "Fri Mar 20 11:25:16 2009 +0800"
      },
      "committer": {
        "name": "Jesse Barnes",
        "email": "jbarnes@virtuousgeek.org",
        "time": "Fri Mar 20 10:48:28 2009 -0700"
      },
      "message": "PCI: handle SR-IOV Virtual Function Migration\n\nAdd or remove a Virtual Function after receiving a Migrate In or Out\nRequest.\n\nReviewed-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n"
    },
    {
      "commit": "dd7cc44d0bcec5e9c42fe52e88dc254ae62eac8d",
      "tree": "742b2c903580eded1e352988b068c0362eccc634",
      "parents": [
        "480b93b7837fb3cf0579a42f4953ac463a5b9e1e"
      ],
      "author": {
        "name": "Yu Zhao",
        "email": "yu.zhao@intel.com",
        "time": "Fri Mar 20 11:25:15 2009 +0800"
      },
      "committer": {
        "name": "Jesse Barnes",
        "email": "jbarnes@virtuousgeek.org",
        "time": "Fri Mar 20 10:48:26 2009 -0700"
      },
      "message": "PCI: add SR-IOV API for Physical Function driver\n\nAdd or remove the Virtual Function when the SR-IOV is enabled or\ndisabled by the device driver. This can happen anytime rather than\nonly at the device probe stage.\n\nReviewed-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n"
    },
    {
      "commit": "a28724b0fb909d247229a70761c90bb37b13366a",
      "tree": "7c5332004a8f52e676076b39aa03aeb45cb03f2a",
      "parents": [
        "8c5cdb6adc6688b9b8fd82ea4a5cf4674dabad79"
      ],
      "author": {
        "name": "Yu Zhao",
        "email": "yu.zhao@intel.com",
        "time": "Fri Mar 20 11:25:13 2009 +0800"
      },
      "committer": {
        "name": "Jesse Barnes",
        "email": "jbarnes@virtuousgeek.org",
        "time": "Fri Mar 20 10:48:24 2009 -0700"
      },
      "message": "PCI: reserve bus range for SR-IOV device\n\nReserve the bus number range used by the Virtual Function when\npcibios_assign_all_busses() returns true.\n\nReviewed-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n"
    },
    {
      "commit": "8c5cdb6adc6688b9b8fd82ea4a5cf4674dabad79",
      "tree": "79fbfde0cedf983b87cf6f782c108000d5c5752d",
      "parents": [
        "d1b054da8f599905f3c18a218961dcf17f9d5f13"
      ],
      "author": {
        "name": "Yu Zhao",
        "email": "yu.zhao@intel.com",
        "time": "Fri Mar 20 11:25:12 2009 +0800"
      },
      "committer": {
        "name": "Jesse Barnes",
        "email": "jbarnes@virtuousgeek.org",
        "time": "Fri Mar 20 10:48:24 2009 -0700"
      },
      "message": "PCI: restore saved SR-IOV state\n\nRestore the volatile registers in the SR-IOV capability after the\nD3-\u003eD0 transition.\n\nReviewed-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n"
    },
    {
      "commit": "d1b054da8f599905f3c18a218961dcf17f9d5f13",
      "tree": "99b62e6771c3b73142dd0622463bed0e19724342",
      "parents": [
        "8293b0f629095efbe7c7e3f9b437f8c040c19eb5"
      ],
      "author": {
        "name": "Yu Zhao",
        "email": "yu.zhao@intel.com",
        "time": "Fri Mar 20 11:25:11 2009 +0800"
      },
      "committer": {
        "name": "Jesse Barnes",
        "email": "jbarnes@virtuousgeek.org",
        "time": "Fri Mar 20 10:48:22 2009 -0700"
      },
      "message": "PCI: initialize and release SR-IOV capability\n\nIf a device has the SR-IOV capability, initialize it (set the ARI\nCapable Hierarchy in the lowest numbered PF if necessary; calculate\nthe System Page Size for the VF MMIO, probe the VF Offset, Stride\nand BARs). A lock for the VF bus allocation is also initialized if\na PF is the lowest numbered PF.\n\nReviewed-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n"
    }
  ]
}