)]}' { "log": [ { "commit": "761434a318a64bf521f8abcc920e1d9837640fa2", "tree": "7590c47fbcadbbfea1a6f7ecdda0441dced26791", "parents": [ "91d3f9bacdb4950d2f79fe2ba296aa249f60d06c" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Fri Nov 06 16:22:44 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Nov 06 14:01:23 2009 -0800" }, "message": "PCI ASPM: fix oops on root port removal\n\nFix the following BUG_ON() problem reported by Alex Chiang.\n\nThis problem happened when removing PCIe root port using PCI logical\nhotplug operation.\n\nThe immediate cause of this problem is that the pointer to invalid\ndata structure is passed to pcie_update_aspm_capable() by\npcie_aspm_exit_link_state(). When pcie_aspm_exit_link_state() received\na pointer to root port link, it unconfigures the root port link and\nfrees its data structure at first. At this point, there are not links\nto configure under the root port and the data structure for root port\nlink is already freed. So pcie_aspm_exit_link_state() must not call\npcie_update_aspm_capable() and pcie_config_aspm_path().\n\nThis patch fixes the problem by changing pcie_aspm_exit_link_state()\nnot to call pcie_update_aspm_capable() and pcie_config_aspm_path() if\nthe specified link is root port link.\n\n------------[ cut here ]------------\nkernel BUG at drivers/pci/pcie/aspm.c:606!\ninvalid opcode: 0000 [#1] SMP DEBUG_PAGEALLOC\nlast sysfs file: /sys/devices/pci0000:40/0000:40:13.0/remove\nCPU 1\nModules linked in: shpchp\nPid: 9345, comm: sysfsd Not tainted 2.6.32-rc5 #98 ProLiant DL785 G6\nRIP: 0010:[\u003cffffffff811df69b\u003e] [\u003cffffffff811df69b\u003e] pcie_update_aspm_capable+0x15/0xbe\nRSP: 0018:ffff88082a2f5ca0 EFLAGS: 00010202\nRAX: 0000000000000e77 RBX: ffff88182cc3e000 RCX: ffff88082a33d006\nRDX: 0000000000000001 RSI: ffffffff811dff4a RDI: ffff88182cc3e000\nRBP: ffff88082a2f5cc0 R08: ffff88182cc3e000 R09: 0000000000000000\nR10: ffff88182fc00180 R11: ffff88182fc00198 R12: ffff88182cc3e000\nR13: 0000000000000000 R14: ffff88182cc3e000 R15: ffff88082a2f5e20\nFS: 00007f259a64b6f0(0000) GS:ffff880864600000(0000) knlGS:0000000000000000\nCS: 0010 DS: 0018 ES: 0018 CR0: 000000008005003b\nCR2: 00007feb53f73da0 CR3: 000000102cc94000 CR4: 00000000000006e0\nDR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000\nDR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400\nProcess sysfsd (pid: 9345, threadinfo ffff88082a2f4000, task ffff88082a33cf00)\nStack:\n ffff88182cc3e000 ffff88182cc3e000 0000000000000000 ffff88082a33cf00\n\u003c0\u003e ffff88082a2f5cf0 ffffffff811dff52 ffff88082a2f5cf0 ffff88082c525168\n\u003c0\u003e ffff88402c9fd2f8 ffff88402c9fd2f8 ffff88082a2f5d20 ffffffff811d7db2\nCall Trace:\n [\u003cffffffff811dff52\u003e] pcie_aspm_exit_link_state+0xf5/0x11e\n [\u003cffffffff811d7db2\u003e] pci_stop_bus_device+0x76/0x7e\n [\u003cffffffff811d7d67\u003e] pci_stop_bus_device+0x2b/0x7e\n [\u003cffffffff811d7e4f\u003e] pci_remove_bus_device+0x15/0xb9\n [\u003cffffffff811dcb8c\u003e] remove_callback+0x29/0x3a\n [\u003cffffffff81135aeb\u003e] sysfs_schedule_callback_work+0x15/0x6d\n [\u003cffffffff81072790\u003e] worker_thread+0x19d/0x298\n [\u003cffffffff8107273b\u003e] ? worker_thread+0x148/0x298\n [\u003cffffffff81135ad6\u003e] ? sysfs_schedule_callback_work+0x0/0x6d\n [\u003cffffffff810765c0\u003e] ? autoremove_wake_function+0x0/0x38\n [\u003cffffffff810725f3\u003e] ? worker_thread+0x0/0x298\n [\u003cffffffff8107629e\u003e] kthread+0x7d/0x85\n [\u003cffffffff8102eafa\u003e] child_rip+0xa/0x20\n [\u003cffffffff8102e4bc\u003e] ? restore_args+0x0/0x30\n [\u003cffffffff81076221\u003e] ? kthread+0x0/0x85\n [\u003cffffffff8102eaf0\u003e] ? child_rip+0x0/0x20\nCode: 89 e5 8a 50 48 31 c0 c0 ea 03 83 e2 07 e8 b2 de fe ff c9 48 98 c3 55 48 89 e5 41 56 49 89 fe 41 55 41 54 53 48 83 7f 10 00 74 04 \u003c0f\u003e 0b eb fe 48 8b 05 da 7d 63 00 4c 8d 60 e8 4c 89 e1 eb 24 4c\nRIP [\u003cffffffff811df69b\u003e] pcie_update_aspm_capable+0x15/0xbe\n RSP \u003cffff88082a2f5ca0\u003e\n---[ end trace 6ae0f65bdeab8555 ]---\n\nReported-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nTested-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "55a1098476619d5d8f4cdae7240ea759274dead7", "tree": "841931bc1c5297788c28f55b4ba2a73d7a22442d", "parents": [ "964fe080d94db82a3268443e9b9ece4c60246414" ], "author": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Oct 27 09:39:18 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Oct 27 09:39:18 2009 -0700" }, "message": "Revert \"PCI: get larger bridge ranges when space is available\"\n\nThis reverts commit 308cf8e13f42f476dfd6552aeff58fdc0788e566. This\npatch had trouble with transparent bridges, among other things. A more\nreadable and correct version should land in 2.6.33.\n\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "5deab536654f95345ea11e8ec6ed5c778df348b5", "tree": "4f6557fccab0e5521498f834f984fa96ea4e5f48", "parents": [ "726206f84c67303cc004aacfd45d37f9277a29f6" ], "author": { "name": "Shane Huang", "email": "shane.huang@amd.com", "time": "Tue Oct 13 11:14:00 2009 +0800" }, "committer": { "name": "Jeff Garzik", "email": "jgarzik@redhat.com", "time": "Fri Oct 16 06:21:20 2009 -0400" }, "message": "ahci / atiixp / pci quirks: rename AMD SB900 into Hudson-2\n\nThis patch renames the code name SB900 into Hudson-2\n\nSigned-off-by: Shane Huang \u003cshane.huang@amd.com\u003e\nSigned-off-by: Jeff Garzik \u003cjgarzik@redhat.com\u003e\n" }, { "commit": "86ae13b006e48959981248493efd3ff4b2828b3d", "tree": "c823456de41e8488ac1aac9f4cf0a0a31b9495c9", "parents": [ "03266d28ca5bf1959ee91dc6554c01b790975352" ], "author": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Mon Oct 12 16:22:46 2009 +0200" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Oct 13 10:20:16 2009 -0700" }, "message": "headers: Fix build after \u003clinux/sched.h\u003e removal\n\nCommit d43c36dc6b357fa1806800f18aa30123c747a6d1 (\"headers: remove\nsched.h from interrupt.h\") left some build errors in some configurations\ndue to drivers having depended on getting header files \"accidentally\".\n\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n[ Combined several one-liners from Ingo into one single patch - Linus ]\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "80fa680d22c11912a0be84b8139422eba1327322", "tree": "a43e38d55505dab7b3448a210d88238b80c50d91", "parents": [ "2caa731819a633bec5a56736e64c562b7e193666", "9a821b231644028f8e2a853eb33d1184e925b183" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Oct 13 10:04:40 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Oct 13 10:04:40 2009 -0700" }, "message": "Merge git://git.infradead.org/~dwmw2/iommu-2.6.32\n\n* git://git.infradead.org/~dwmw2/iommu-2.6.32:\n x86: Move pci_iommu_init to rootfs_initcall()\n Run pci_apply_final_quirks() sooner.\n Mark pci_apply_final_quirks() __init rather than __devinit\n Rename pci_init() to pci_apply_final_quirks(), move it to quirks.c\n intel-iommu: Yet another BIOS workaround: Isoch DMAR unit with no TLB space\n intel-iommu: Decode (and ignore) RHSA entries\n intel-iommu: Make \"Unknown DMAR structure\" message more informative\n" }, { "commit": "2caa731819a633bec5a56736e64c562b7e193666", "tree": "e93f5c50c33c7cf5a9cc3ea29dd1d868b4f14d5c", "parents": [ "589bf8d52b5bbb580962438ad9403ec6853bc12b", "30fc24b5cbc55f9e6c686e2710cc812419bddc0c" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Oct 12 14:38:34 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Oct 12 14:38:34 2009 -0700" }, "message": "Merge branch \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6\n\n* \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6:\n PCI: Prevent AER driver from being loaded on non-root port PCIE devices\n PCI: get larger bridge ranges when space is available\n PCI: pci.c: fix kernel-doc notation\n PCI quirk: TI XIO200a erroneously reports support for fast b2b transfers\n PCI PM: Read device power state from register after updating it\n PCI: remove pci_assign_resource_fixed()\n PCI: PCIe portdrv: remove \"-driver\" from driver name\n" }, { "commit": "cf6f3bf7e587a00217d7509b440f694711c76b2e", "tree": "0a7f166bcaca397981e89e13e68d54440d1214e5", "parents": [ "00010268842bda320d43159324651c330e1e8136" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Oct 12 12:51:22 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Oct 12 14:42:09 2009 +0100" }, "message": "Run pci_apply_final_quirks() sooner.\n\nHaving this as a device_initcall() means that some real device drivers\ncan actually initialise _before_ the quirks are run, which is wrong.\n\nWe want it to run _before_ device_initcall(), but _after_ fs_initcall(),\nsince some arch-specific PCI initialisation like pcibios_assign_resources()\nis done at fs_initcall().\n\nWe could use rootfs_initcall() but I actually want to use that for the\nIOMMU initialisation, which has to come after the quirks, but still\nbefore the real devices. So use fs_initcall_sync() instead -- since this\nis entirely synchronous, it doesn\u0027t hurt that it\u0027ll escape the\nsynchronisation.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "00010268842bda320d43159324651c330e1e8136", "tree": "97a9cb7187c2b1594c859816f793e0d8a0f9990e", "parents": [ "8d86fb2c80ec376b35ae64ac858d406ae1d42a3f" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Oct 12 12:50:34 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Oct 12 14:42:06 2009 +0100" }, "message": "Mark pci_apply_final_quirks() __init rather than __devinit\n\nIt doesn\u0027t get invoked on hotplug; it can be thrown away after init.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "8d86fb2c80ec376b35ae64ac858d406ae1d42a3f", "tree": "66ae9941d9f9785fd75365c357b706ff2d31f67a", "parents": [ "e0fc7e0b4b5e69616f10a894ab9afff3c64be74e" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Oct 12 12:48:43 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon Oct 12 14:42:04 2009 +0100" }, "message": "Rename pci_init() to pci_apply_final_quirks(), move it to quirks.c\n\nThis function may have done more in the past, but all it does now is\napply the PCI_FIXUP_FINAL quirks. So name it sensibly and put it where\nit belongs.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "d43c36dc6b357fa1806800f18aa30123c747a6d1", "tree": "339ce510073ecbe9b3592008f7dece7b277035ef", "parents": [ "69585dd69e663a40729492c7b52eb82477a2027a" ], "author": { "name": "Alexey Dobriyan", "email": "adobriyan@gmail.com", "time": "Wed Oct 07 17:09:06 2009 +0400" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun Oct 11 11:20:58 2009 -0700" }, "message": "headers: remove sched.h from interrupt.h\n\nAfter m68k\u0027s task_thread_info() doesn\u0027t refer to current,\nit\u0027s possible to remove sched.h from interrupt.h and not break m68k!\nMany thanks to Heiko Carstens for allowing this.\n\nSigned-off-by: Alexey Dobriyan \u003cadobriyan@gmail.com\u003e\n" }, { "commit": "30fc24b5cbc55f9e6c686e2710cc812419bddc0c", "tree": "58a6ca580ab9fef9081e4921775b9b2c33ca0ab2", "parents": [ "308cf8e13f42f476dfd6552aeff58fdc0788e566" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Oct 07 09:28:56 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Oct 07 09:28:56 2009 -0700" }, "message": "PCI: Prevent AER driver from being loaded on non-root port PCIE devices\n\nA bug was seen on boards using a PLX 8518 switch device which advertises\nAER on each of it\u0027s transparent bridges. The AER driver was loaded for\neach bridge and this driver tried to access the AER source ID register\nwhenever an interrupt occured on the shared PCI INTX lines. The source\nID register does not exist on non root port PCIE device\u0027s which\nadvertise AER and trying to access this register causes a unsupported\nrequest error on the bridge. Thus, when the next interrupt occurs,\nanother error is found and the non existent source ID register is\naccessed again, and so it goes on.\n\nThe result is a spammed dmesg with unsupported request PCI express\nerrors on the bridge device that the AER driver is loaded against.\n\nReported-by: Malcolm Crossley \u003cmalcolm.crossley2@gefanuc.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nTested-by: Malcolm Crossley \u003cmalcolm.crossley2@gefanuc.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "308cf8e13f42f476dfd6552aeff58fdc0788e566", "tree": "e3a12e8519900667ec93ad9a21a71e6e5d035b6a", "parents": [ "19eea630f7c56038dd80fe2f6910c78655bf29c8" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Sun Sep 13 15:57:10 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Oct 07 09:28:18 2009 -0700" }, "message": "PCI: get larger bridge ranges when space is available\n\nFound one system:\n[ 71.120590] pci 0000:40:05.0: scanning behind bridge, config 4f4a40, pass 0\n[ 71.138283] PCI: Scanning bus 0000:4a\n[ 71.140341] pci 0000:4a:00.0: found [15b3:6278] class 000c06 header type 00\n[ 71.157173] pci 0000:4a:00.0: reg 10 64bit mmio: [0x000000-0x0fffff]\n[ 71.161697] pci 0000:4a:00.0: reg 18 64bit mmio pref: [0x000000-0x7fffff]\n[ 71.179403] pci 0000:4a:00.0: reg 20 64bit mmio pref: [0x000000-0xfffffff]\n[ 71.185366] pci 0000:4a:00.0: calling quirk_resource_alignment+0x0/0x1dd\n[ 71.200846] pci 0000:4a:00.0: disabling ASPM on pre-1.1 PCIe device. You can enable it with \u0027pcie_aspm\u003dforce\u0027\n[ 71.219623] PCI: Fixups for bus 0000:4a\n[ 71.222194] pci 0000:40:05.0: bridge 32bit mmio: [0xcf000000-0xcf0fffff]\n[ 71.238662] pci 0000:40:05.0: bridge 64bit mmio pref: [0xcd800000-0xcdffffff]\n[ 71.255793] PCI: Bus scan for 0000:4a returning with max\u003d4a\n\nDevice needs a big pref mmio, but BIOS doesn\u0027t allocate mmio to it aside\nfrom a small MMIO range. Later, the kernel will not allocate resources to\nthat to the device:\n[ 99.574030] pci 0000:4a:00.0: BAR 4: can\u0027t allocate mem resource [0xd0000000-0xcdffffff]\n[ 99.580102] pci 0000:4a:00.0: BAR 2: got res [0xcd800000-0xcdffffff] bus [0xcd800000-0xcdffffff] flags 0x12120c\n[ 99.602307] pci 0000:4a:00.0: BAR 2: moved to bus [0xcd800000-0xcdffffff] flags 0x12120c\n[ 99.615991] pci 0000:4a:00.0: BAR 0: got res [0xcf000000-0xcf0fffff] bus [0xcf000000-0xcf0fffff] flags 0x120204\n[ 99.634499] pci 0000:4a:00.0: BAR 0: moved to bus [0xcf000000-0xcf0fffff] flags 0x120204\n[ 99.654318] pci 0000:40:05.0: PCI bridge, secondary bus 0000:4a\n[ 99.658766] pci 0000:40:05.0: IO window: disabled\n[ 99.675478] pci 0000:40:05.0: MEM window: 0xcf000000-0xcf0fffff\n[ 99.681663] pci 0000:40:05.0: PREFETCH window: 0x000000cd800000-0x000000cdffffff\n\nSo try to get a big range in the pci bridge if there is no child using\nthat range. With the patch we get:\n[ 99.104525] pci 0000:4a:00.0: BAR 4: got res [0xfc080000000-0xfc08fffffff] bus [0xfc080000000-0xfc08fffffff] flags 0x12120c\n[ 99.123624] pci 0000:4a:00.0: BAR 4: moved to bus [0xfc080000000-0xfc08fffffff] flags 0x12120c\n[ 99.131977] pci 0000:4a:00.0: BAR 2: got res [0xfc090000000-0xfc0907fffff] bus [0xfc090000000-0xfc0907fffff] flags 0x12120c\n[ 99.149788] pci 0000:4a:00.0: BAR 2: moved to bus [0xfc090000000-0xfc0907fffff] flags 0x12120c\n[ 99.169248] pci 0000:4a:00.0: BAR 0: got res [0xc0200000-0xc02fffff] bus [0xc0200000-0xc02fffff] flags 0x120204\n[ 99.189508] pci 0000:4a:00.0: BAR 0: moved to bus [0xc0200000-0xc02fffff] flags 0x120204\n[ 99.206402] pci 0000:40:05.0: PCI bridge, secondary bus 0000:4a\n[ 99.210637] pci 0000:40:05.0: IO window: disabled\n[ 99.224856] pci 0000:40:05.0: MEM window: 0xc0200000-0xc03fffff\n[ 99.230019] pci 0000:40:05.0: PREFETCH window: 0x000fc080000000-0x000fc097ffffff\n\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "19eea630f7c56038dd80fe2f6910c78655bf29c8", "tree": "6d142e7c861b0d40774dc9edacb4ae9be4041e3a", "parents": [ "1f56f4a2b4d12c1c348cab23024024396ec7cddc" ], "author": { "name": "Randy Dunlap", "email": "randy.dunlap@oracle.com", "time": "Thu Sep 17 15:28:22 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Oct 07 09:28:18 2009 -0700" }, "message": "PCI: pci.c: fix kernel-doc notation\n\nFix kernel-doc notation (\u0026 warnings) in pci/pci.c.\n\nSigned-off-by: Randy Dunlap \u003crandy.dunlap@oracle.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "1f56f4a2b4d12c1c348cab23024024396ec7cddc", "tree": "0b7f00bebd3e613d929791549d44689e9aa0387b", "parents": [ "e13cdbd71fe12c4e191b737c4a3dbfdb4b2de03b" ], "author": { "name": "Gabe Black", "email": "gabe.black@ni.com", "time": "Tue Oct 06 09:19:45 2009 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Oct 07 09:28:17 2009 -0700" }, "message": "PCI quirk: TI XIO200a erroneously reports support for fast b2b transfers\n\nThis quirk will disable fast back to back transfer on the secondary bus\nsegment of the TI Bridge.\n\nSigned-off-by: Gabe Black \u003cgabe.black@ni.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "e13cdbd71fe12c4e191b737c4a3dbfdb4b2de03b", "tree": "b46e5213273a569becbcf94cd3f4a60daab026f7", "parents": [ "b812cca4e2efe9a05de20ccf3f8587e7ac6e12fa" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Mon Oct 05 00:48:40 2009 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Oct 06 10:27:51 2009 -0700" }, "message": "PCI PM: Read device power state from register after updating it\n\nAfter attempting to change the power state of a PCI device\npci_raw_set_power_state() doesn\u0027t check if the value it wrote into\nthe device\u0027s PCI_PM_CTRL register has been stored in there, but\nunconditionally modifies the device\u0027s current_state field to reflect\nthe change. This may cause problems to happen if the power state of\nthe device hasn\u0027t been changed in fact, because it will make the PCI\nPM core make a wrong assumption.\n\nTo prevent such situations from happening modify\npci_raw_set_power_state() so that it reads the device\u0027s PCI_PM_CTRL\nregister after writing into it and uses the value read from the\nregister to update the device\u0027s current_state field. Also make it\nprint a message saying that the device refused to change its power\nstate as requested (returning an error code in such cases would cause\nsuspend regressions to appear on some systems, where device drivers\u0027\nsuspend routines return error codes if pci_set_power_state() fails).\n\nReviewed-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "b812cca4e2efe9a05de20ccf3f8587e7ac6e12fa", "tree": "6c1c5f056e54daf14b10ec6e3461ea67f6e5d78a", "parents": [ "e3fb20f9c8783d6e27cf84389a9606e410733eef" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Mon Oct 05 16:38:13 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Oct 06 09:42:04 2009 -0700" }, "message": "PCI: remove pci_assign_resource_fixed()\n\nAdrian commented out this function in 2baad5f96b49, but I don\u0027t think\nit\u0027s even worth cluttering the file with the unused code.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "e3fb20f9c8783d6e27cf84389a9606e410733eef", "tree": "ece2a369a2c95148a622e7e2faf56fdd20d0c716", "parents": [ "0eca52a92735f43462165efe00a7e394345fb38e" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Mon Oct 05 16:47:34 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Oct 06 09:41:48 2009 -0700" }, "message": "PCI: PCIe portdrv: remove \"-driver\" from driver name\n\nNo need to include \"-driver\" in the driver name.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nCC: Tom Long Nguyen \u003ctom.l.nguyen@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "e0fc7e0b4b5e69616f10a894ab9afff3c64be74e", "tree": "32b6d394c47bd61e530fd322d473dd79c9b70db9", "parents": [ "17b6097753e926ca546189463070a7e94e7ea9fa" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Wed Sep 30 09:12:17 2009 -0700" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Wed Sep 30 09:12:17 2009 -0700" }, "message": "intel-iommu: Yet another BIOS workaround: Isoch DMAR unit with no TLB space\n\nAsus decided to ship a BIOS which configures sound DMA to go via the\ndedicated IOMMU unit, but assigns precisely zero TLB entries to that\nunit. Which causes the whole thing to deadlock, including the DMA\ntraffic on the _other_ IOMMU units. Nice one.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "b24715027aab5e586c4ab1d035f3e543307dea69", "tree": "01688402d1694b42f9821e00fc6b4b0913de397f", "parents": [ "53cddfcc0e760d2b364878b6dadbd0c6d087cfae" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Mon Sep 21 19:28:49 2009 +0000" }, "committer": { "name": "Len Brown", "email": "len.brown@intel.com", "time": "Fri Sep 25 14:24:22 2009 -0400" }, "message": "ACPICA: fixup after acpi_get_object_info() change\n\nCommit 15b8dd53f5ffa changed info-\u003ehardware_id from a static array to\na pointer. If hardware_id is non-NULL, it points to a NULL-terminated\nstring, so we don\u0027t need to terminate it explicitly. However, it may\nbe NULL; in that case, we *can\u0027t* add a NULL terminator.\n\nThis causes a NULL pointer dereference oops for devices without _HID.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nCC: Lin Ming \u003cming.m.lin@intel.com\u003e\nCC: Bob Moore \u003crobert.moore@intel.com\u003e\nCC: Gary Hade \u003cgaryhade@us.ibm.com\u003e\nSigned-off-by: Len Brown \u003clen.brown@intel.com\u003e\n" }, { "commit": "17b6097753e926ca546189463070a7e94e7ea9fa", "tree": "a39bb6715db3951e3dbb2f7b64fc57ef46f3f04b", "parents": [ "4de75cf9391b538bbfe7dc0a9782f1ebe8e242ad" ], "author": { "name": "Roland Dreier", "email": "rdreier@cisco.com", "time": "Thu Sep 24 12:14:00 2009 -0700" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Thu Sep 24 12:19:39 2009 -0700" }, "message": "intel-iommu: Decode (and ignore) RHSA entries\n\nI recently got a system where the DMAR table included a couple of RHSA\n(remapping hardware static affinity) entries. Rather than printing a\nmessage about an \"Unknown DMAR structure,\" it would probably be more\nuseful to dump the RHSA structure (as other DMAR structures are dumped).\n\nSigned-off-by: Roland Dreier \u003crolandd@cisco.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "b7f21bb2e23b4fec16b448a34889f467465be659", "tree": "3569f95b5ebf5bcce03aad976ef69b9b818de832", "parents": [ "7ca263cdf8cf74d0f1c6f48d07d556de92e3bec9", "76baeebf7df493703eeb4428eac015bdb7fabda6" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Sep 24 09:57:08 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Sep 24 09:57:08 2009 -0700" }, "message": "Merge branch \u0027linux-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6\n\n* \u0027linux-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: (21 commits)\n x86/PCI: make 32 bit NUMA node array int, not unsigned char\n x86/PCI: default pcibus cpumask to all cpus if it lacks affinity\n MAINTAINTERS: remove hotplug driver entries\n PCI: pciehp: remove slot capabilities definitions\n PCI: pciehp: remove error message definitions\n PCI: pciehp: remove number field\n PCI: pciehp: remove hpc_ops\n PCI: pciehp: remove pci_dev field\n PCI: pciehp: remove crit_sect mutex\n PCI: pciehp: remove slot_bus field\n PCI: pciehp: remove first_slot field\n PCI: pciehp: remove slot_device_offset field\n PCI: pciehp: remove hp_slot field\n PCI: pciehp: remove device field\n PCI: pciehp: remove bus field\n PCI: pciehp: remove slot_num_inc field\n PCI: pciehp: remove num_slots field\n PCI: pciehp: remove slot_list field\n PCI: fix VGA arbiter header file\n PCI: Disable AER with pci\u003dnomsi\n ...\n\nFixed up trivial conflicts in MAINTAINERS\n" }, { "commit": "4de75cf9391b538bbfe7dc0a9782f1ebe8e242ad", "tree": "e9ddd0d95767fd2868498e7e86305e579d9fe8ec", "parents": [ "b09a75fc5e77b7c58d097236f89b1ff72dcdb562" ], "author": { "name": "Roland Dreier", "email": "rdreier@cisco.com", "time": "Thu Sep 24 01:01:29 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Wed Sep 23 17:31:27 2009 -0700" }, "message": "intel-iommu: Make \"Unknown DMAR structure\" message more informative\n\nWe might as well print the type of the DMAR structure we don\u0027t know how\nto handle when skipping it. Then someone getting this message has a\nchance of telling whether the structure is just bogus, or if there\nreally is something valid that the kernel doesn\u0027t know how to handle.\n\nSigned-off-by: Roland Dreier \u003crolandd@cisco.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "b09a75fc5e77b7c58d097236f89b1ff72dcdb562", "tree": "8f818f1b3e44d9bc822b13dc7c368077981dd6ea", "parents": [ "cf63ff5fa4399e215cc5ef322ccd8bddfff9afa6", "b94996c99c8befed9cbbb8804a4625e203913318" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Sep 23 10:06:10 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Sep 23 10:06:10 2009 -0700" }, "message": "Merge git://git.infradead.org/iommu-2.6\n\n* git://git.infradead.org/iommu-2.6: (23 commits)\n intel-iommu: Disable PMRs after we enable translation, not before\n intel-iommu: Kill DMAR_BROKEN_GFX_WA option.\n intel-iommu: Fix integer wrap on 32 bit kernels\n intel-iommu: Fix integer overflow in dma_pte_{clear_range,free_pagetable}()\n intel-iommu: Limit DOMAIN_MAX_PFN to fit in an \u0027unsigned long\u0027\n intel-iommu: Fix kernel hang if interrupt remapping disabled in BIOS\n intel-iommu: Disallow interrupt remapping if not all ioapics covered\n intel-iommu: include linux/dmi.h to use dmi_ routines\n pci/dmar: correct off-by-one error in dmar_fault()\n intel-iommu: Cope with yet another BIOS screwup causing crashes\n intel-iommu: iommu init error path bug fixes\n intel-iommu: Mark functions with __init\n USB: Work around BIOS bugs by quiescing USB controllers earlier\n ia64: IOMMU passthrough mode shouldn\u0027t trigger swiotlb init\n intel-iommu: make domain_add_dev_info() call domain_context_mapping()\n intel-iommu: Unify hardware and software passthrough support\n intel-iommu: Cope with broken HP DC7900 BIOS\n iommu\u003dpt is a valid early param\n intel-iommu: double kfree()\n intel-iommu: Kill pointless intel_unmap_single() function\n ...\n\nFixed up trivial include lines conflict in drivers/pci/intel-iommu.c\n" }, { "commit": "b94996c99c8befed9cbbb8804a4625e203913318", "tree": "867d34ad9c837d35bbbf5921fb89b53378f67b48", "parents": [ "0c02a20ff7695f9c54cc7c013dda326270ccdac8" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Sep 19 15:28:12 2009 -0700" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Sep 19 15:28:12 2009 -0700" }, "message": "intel-iommu: Disable PMRs after we enable translation, not before\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "64de5af000e99f32dd49ff5dd9a0fd7db1f60305", "tree": "f26d720da22d1b3afd24c4edebb26f7b3318ba4b", "parents": [ "59c36286b74ae6a8adebf6e133a83d7f2e3e6704" ], "author": { "name": "Benjamin LaHaise", "email": "ben.lahaise@neterion.com", "time": "Wed Sep 16 21:05:55 2009 -0400" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Sep 19 09:26:20 2009 -0700" }, "message": "intel-iommu: Fix integer wrap on 32 bit kernels\n\nThe following 64 bit promotions are necessary to handle memory above the\n4GiB boundary correctly.\n\n[dwmw2: Fix the second part not to need 64-bit arithmetic at all]\n\nSigned-off-by: Benjamin LaHaise \u003cben.lahaise@neterion.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "59c36286b74ae6a8adebf6e133a83d7f2e3e6704", "tree": "ad6d608b560dc540330bdcc89e8702ac85993174", "parents": [ "2ebe31513fcbe7a781f27002f065b50ae195022f" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Sep 19 07:36:28 2009 -0700" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Sep 19 07:36:28 2009 -0700" }, "message": "intel-iommu: Fix integer overflow in dma_pte_{clear_range,free_pagetable}()\n\nIf end_pfn is equal to (unsigned long)-1, then the loop will never end.\n\nSeen on 32-bit kernel, but could have happened on 64-bit too once we get\nhardware that supports 64-bit guest addresses.\n\nChange both functions to a \u0027do {} while\u0027 loop with the test at the end,\nand check for the PFN having wrapper round to zero.\n\nReported-by: Benjamin LaHaise \u003cben.lahaise@neterion.com\u003e\nTested-by: Benjamin LaHaise \u003cben.lahaise@neterion.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "2ebe31513fcbe7a781f27002f065b50ae195022f", "tree": "e593fd5e1a2f952c768e7c235f9a25771a6ea59e", "parents": [ "074835f0143b83845af5044af2739c52c9f53808" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Sep 19 07:34:04 2009 -0700" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Sep 19 07:34:04 2009 -0700" }, "message": "intel-iommu: Limit DOMAIN_MAX_PFN to fit in an \u0027unsigned long\u0027\n\nThis means we\u0027re limited to 44-bit addresses on 32-bit kernels, and\nmakes it sane for us to use \u0027unsigned long\u0027 for PFNs throughout.\n\nWhich is just as well, really, since we already do that.\n\nReported-by: Benjamin LaHaise \u003cben.lahaise@neterion.com\u003e\nTested-by: Benjamin LaHaise \u003cben.lahaise@neterion.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "d26f0528d588e596955bf296a609afe52eafc099", "tree": "314f7a5637d5517a19f29d64a17e3459505def8f", "parents": [ "b963bd39c9000328f6ce4f12aa52abbb0c68ee91", "df43176c934f2bc01f7615a6e20a4b8e77dcdd11" ], "author": { "name": "Len Brown", "email": "len.brown@intel.com", "time": "Sat Sep 19 02:14:45 2009 -0400" }, "committer": { "name": "Len Brown", "email": "len.brown@intel.com", "time": "Sat Sep 19 02:14:45 2009 -0400" }, "message": "Merge branch \u0027misc-2.6.32\u0027 into release\n\nConflicts:\n\tdrivers/pci/dmar.c\n\nSigned-off-by: Len Brown \u003clen.brown@intel.com\u003e\n" }, { "commit": "985f38781d19101aba121df423f92c87b208c6df", "tree": "21b10413b6e24c0eaf5c3b2432e936749a672644", "parents": [ "d093d70a81b08673d1577ad73419998f02be9d29", "c9766237afa92e8d7f27bbcd4964f1b43fa0bce8" ], "author": { "name": "Len Brown", "email": "len.brown@intel.com", "time": "Sat Sep 19 01:45:22 2009 -0400" }, "committer": { "name": "Len Brown", "email": "len.brown@intel.com", "time": "Sat Sep 19 01:45:22 2009 -0400" }, "message": "Merge branch \u0027acpica\u0027 into release\n" }, { "commit": "eb27cae8adaa658a0bf31631baa1ce29d8183759", "tree": "bd7bca44cd16854deac228f1598d9fa2f8bf22af", "parents": [ "74fca6a42863ffacaf7ba6f1936a9f228950f657" ], "author": { "name": "Len Brown", "email": "len.brown@intel.com", "time": "Mon Jul 06 23:40:19 2009 -0400" }, "committer": { "name": "Len Brown", "email": "len.brown@intel.com", "time": "Sat Sep 19 01:33:27 2009 -0400" }, "message": "ACPI: linux/acpi.h should not include linux/dmi.h\n\nusers of acpi.h that need dmi.h should include it directly.\n\nSigned-off-by: Len Brown \u003clen.brown@intel.com\u003e\n" }, { "commit": "003d6a38ce1a59e0053a02fd9e9a65b588bc8e33", "tree": "c9b941f4798a2accca200b0b01c07353ce5b07e1", "parents": [ "71fd68e7d234f6b7d8407c8f486764d24f8411f4", "e55a5999ffcf72dc4d43d73618957964cb87065a" ], "author": { "name": "Len Brown", "email": "len.brown@intel.com", "time": "Sat Sep 19 00:37:13 2009 -0400" }, "committer": { "name": "Len Brown", "email": "len.brown@intel.com", "time": "Sat Sep 19 00:37:13 2009 -0400" }, "message": "Merge branch \u0027sfi-base\u0027 into release\n\nConflicts:\n\tdrivers/acpi/power.c\n\nSigned-off-by: Len Brown \u003clen.brown@intel.com\u003e\n" }, { "commit": "656927b119a6f2fe0ed453191e13eec6fe041f4c", "tree": "33a7468578e2010b761e20eca71c5934d574b9ed", "parents": [ "d9fb42a845f8e56d91017462650ba41e854f5552" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Tue Sep 15 17:34:05 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Sep 17 10:06:46 2009 -0700" }, "message": "PCI: pciehp: remove slot capabilities definitions\n\nUse generic PCIe slot capabilities register definitions instead of\ninternal definitions.\n\nAcked-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "d9fb42a845f8e56d91017462650ba41e854f5552", "tree": "30600b2e6d3cb3319d46e234f83779745d738818", "parents": [ "07a09694de556f307b1c5035cdf0f17c6243d1cd" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Tue Sep 15 17:33:30 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Sep 17 10:06:41 2009 -0700" }, "message": "PCI: pciehp: remove error message definitions\n\nRemove (almost) unused error message definitions.\n\nAcked-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "07a09694de556f307b1c5035cdf0f17c6243d1cd", "tree": "ceb0bc41419ab4f680e87f49e0c581177c2147f1", "parents": [ "82a9e79ef132cbf77de58aae35c1a14237f2fcde" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Tue Sep 15 17:31:16 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Sep 17 10:06:36 2009 -0700" }, "message": "PCI: pciehp: remove number field\n\nSince slot_cap field in struct controller contains physical slot\nnumber informationq, we don\u0027t need number field in struct slot.\n\nAcked-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "82a9e79ef132cbf77de58aae35c1a14237f2fcde", "tree": "1ca6f0dc69cb7e92df48d4f05b595b032e03e206", "parents": [ "385e24917ed8eeba25dddd8e63bf3fe3d53eafc5" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Tue Sep 15 17:30:48 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Sep 17 10:06:31 2009 -0700" }, "message": "PCI: pciehp: remove hpc_ops\n\nThe struct hpc_ops seems a set of hooks to controller specific\nroutines. But, it is meaningless because no hotplug controller driver\nfollows this framework.\n\nAcked-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "385e24917ed8eeba25dddd8e63bf3fe3d53eafc5", "tree": "8ab67402844702e534d9d0684fbb49db75883383", "parents": [ "6aaa6d06f57f3689afe27c1fad256c5d6aa9b271" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Tue Sep 15 17:30:14 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Sep 17 10:06:25 2009 -0700" }, "message": "PCI: pciehp: remove pci_dev field\n\nSince we have a pointer to pcie_device in struct controller, we don\u0027t\nneed a pointer to pci_dev.\n\nAcked-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "6aaa6d06f57f3689afe27c1fad256c5d6aa9b271", "tree": "37046e6aa57d03d9b5a890dc9bde34afe1b2f48e", "parents": [ "5f9cab7af6f7ef1e3cbb25217617eb5bd082aa7b" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Tue Sep 15 17:29:49 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Sep 17 10:06:18 2009 -0700" }, "message": "PCI: pciehp: remove crit_sect mutex\n\nThe crit_sect mutex defined in struct controller is to serialize\nhot-plug operations against multiple slots under the same bus. But,\nsince PCIe doesnstream port has only one slot at most, it is\nmeaningless and we don\u0027t need it.\n\nAcked-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "5f9cab7af6f7ef1e3cbb25217617eb5bd082aa7b", "tree": "6823c016ba3c2ace064ad39aee586dcf4c3e4cdc", "parents": [ "d54798f034b247b9d95a31cd755a4236655ca502" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Tue Sep 15 17:29:21 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Sep 17 10:06:14 2009 -0700" }, "message": "PCI: pciehp: remove slot_bus field\n\nRemove unused slot_bus field in struct controller.\n\nAcked-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "d54798f034b247b9d95a31cd755a4236655ca502", "tree": "7f1be3a0e83a171fd16656cfb89b24b0f8144e50", "parents": [ "a2359a334fb2c89347e031c4494282e6756e9ae7" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Tue Sep 15 17:28:53 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Sep 17 10:06:09 2009 -0700" }, "message": "PCI: pciehp: remove first_slot field\n\nThe slot number can be calculated only by physical slot number field\nin the slot capabilities register. So the first_slot field in struct\ncontroller is meaningless and we don\u0027t need it.\n\nAcked-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "a2359a334fb2c89347e031c4494282e6756e9ae7", "tree": "9ac5e61752318def916d47fd0ea27b62b19dbc3c", "parents": [ "0e3631593c38e8a09bf58a46c6f6a3426d3ad0f0" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Tue Sep 15 17:28:28 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Sep 17 10:06:02 2009 -0700" }, "message": "PCI: pciehp: remove slot_device_offset field\n\nSince the device number of the hot-slot under the PCIe downstream port\nis always 0, the slot_device_offset field in the slot is meaningless\nand we don\u0027t need it.\n\nAcked-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "0e3631593c38e8a09bf58a46c6f6a3426d3ad0f0", "tree": "e5b47555b2f4611c9c478367fe9000d3812c62b1", "parents": [ "d689f7eb364a51ccd857605dede0d6c22a1aad91" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Tue Sep 15 17:27:24 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Sep 17 10:05:58 2009 -0700" }, "message": "PCI: pciehp: remove hp_slot field\n\nThe hp_slot field is to identify the slot under the same\ncontroller. But, since PCIe downstream port has only one slot at most,\nit is meaningless and we don\u0027t need it.\n\nAcked-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "d689f7eb364a51ccd857605dede0d6c22a1aad91", "tree": "34efda76db5ec3e0c57034deb254014c55b93068", "parents": [ "ab9c6c86701b498445334db746aa2e8dc473c7b6" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Tue Sep 15 17:26:56 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Sep 17 10:05:51 2009 -0700" }, "message": "PCI: pciehp: remove device field\n\nThe device field in the struct slot is not necessary because it is\nalways 0 in pciehp driver.\n\nAcked-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "ab9c6c86701b498445334db746aa2e8dc473c7b6", "tree": "ebfdc650615be00a8047fb3448d96731a7197292", "parents": [ "6a11c135f3511743d09474ccaac2137d34c352a8" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Tue Sep 15 17:26:32 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Sep 17 10:05:46 2009 -0700" }, "message": "PCI: pciehp: remove bus field\n\nThe bus field in struct slot is not necessary.\n\nAcked-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "6a11c135f3511743d09474ccaac2137d34c352a8", "tree": "4d24d141eb01f49c1b12a7c77a85cf848ad87e6c", "parents": [ "e23727da77109ef856f7a76c1a7d2e2282f600f5" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Tue Sep 15 17:25:54 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Sep 17 10:05:41 2009 -0700" }, "message": "PCI: pciehp: remove slot_num_inc field\n\nThe slot_num_inc field in struct controller is unused and meaningless\nin pciehp driver.\n\nAcked-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "e23727da77109ef856f7a76c1a7d2e2282f600f5", "tree": "83d600080ea3cbb8bd064ddad040604e06f077ce", "parents": [ "8720d27dabf580278a7719fa8b5783d9878e2d42" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Tue Sep 15 17:25:17 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Sep 17 10:05:36 2009 -0700" }, "message": "PCI: pciehp: remove num_slots field\n\nSince PCIe downstream port has only one slot at most, we don\u0027t need\nnum_slots field in struct controller. Note that struct controller\nitself doesn\u0027t exist if PCIe downstream port has no slot.\n\nAcked-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "8720d27dabf580278a7719fa8b5783d9878e2d42", "tree": "229ee309a9a205f41650a01ff83c0a24b710a314", "parents": [ "e2d4304b7d2b85c45de89ec420037d6b9261a12d" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Tue Sep 15 17:24:46 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Sep 17 10:05:31 2009 -0700" }, "message": "PCI: pciehp: remove slot_list field\n\nSince PCIe downstream port has only one slot at most, we don\u0027t need\n\u0027slot_list\u0027 linked list to manage multiple slots under the port.\n\nAcked-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "3e77a3f7895e9c20756dc250282afa12f6d259a3", "tree": "fe9a701f8c7d86841846b52326fbec89c8e42c29", "parents": [ "7557b5d63259d55f716e62e528978d4866318515" ], "author": { "name": "Andi Kleen", "email": "andi@firstfloor.org", "time": "Wed Sep 16 22:40:22 2009 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Sep 17 10:05:27 2009 -0700" }, "message": "PCI: Disable AER with pci\u003dnomsi\n\nWhen booting with pci\u003dnomsi aer causes lost interrupts and\nlockdep inversions.\n\nSo check if MSIs are not disabled before initializing the aer\ndriver.\n\nSigned-off-by: Andi Kleen \u003cak@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "7557b5d63259d55f716e62e528978d4866318515", "tree": "a7de26e15fe8d551f7b853d9ecd47403f31b13db", "parents": [ "ab86e5765d41a5eb4239a1c04d613db87bea5ed8" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Sep 16 17:29:59 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Sep 17 10:05:16 2009 -0700" }, "message": "PCI ASPM: support L1 only\n\nThe definition of the ASPM support field in the Link Capabilities\nRegister had been changed by the \"ASPM optionality ECN\" as follows:\n\n\u003cBefore\u003e\n\t00b\tReserved\n\t01b\tL0s Supported\n\t10b\tReserved\n\t11b\tL0s and L1 Supported\n\n\u003cAfter\u003e\n\t00b\tNo ASPM Support\n\t01b\tL0s Supported\n\t10b\tL1 Supported\n\t11b\tL0s and L1 Supported\n\nCurrent linux ASPM driver doesn\u0027t enable ASPM if the support field is\n00b or 10b. So there is no impact about 00b. But current linux ASPM\ndriver doesn\u0027t enable L1 if the support field is 10b. With this patch,\n10b (L1 support) is handled properly.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "4406c56d0a4da7a37b9180abeaece6cd00bcc874", "tree": "65a85fa73a25d24cbed6d163fdcf8df1b934a0be", "parents": [ "6b7b352f2102e21f9d8f38e932f01d9c5705c073", "5e3573db2bd5db6925159279d99576a4635bdb66" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Sep 16 07:49:54 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Sep 16 07:49:54 2009 -0700" }, "message": "Merge branch \u0027linux-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6\n\n* \u0027linux-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: (75 commits)\n PCI hotplug: clean up acpi_run_hpp()\n PCI hotplug: acpiphp: use generic pci_configure_slot()\n PCI hotplug: shpchp: use generic pci_configure_slot()\n PCI hotplug: pciehp: use generic pci_configure_slot()\n PCI hotplug: add pci_configure_slot()\n PCI hotplug: clean up acpi_get_hp_params_from_firmware() interface\n PCI hotplug: acpiphp: don\u0027t cache hotplug_params in acpiphp_bridge\n PCI hotplug: acpiphp: remove superfluous _HPP/_HPX evaluation\n PCI: Clear saved_state after the state has been restored\n PCI PM: Return error codes from pci_pm_resume()\n PCI: use dev_printk in quirk messages\n PCI / PCIe portdrv: Fix pcie_portdrv_slot_reset()\n PCI Hotplug: convert acpi_pci_detect_ejectable() to take an acpi_handle\n PCI Hotplug: acpiphp: find bridges the easy way\n PCI: pcie portdrv: remove unused variable\n PCI / ACPI PM: Propagate wake-up enable for devices w/o ACPI support\n ACPI PM: Replace wakeup.prepared with reference counter\n PCI PM: Introduce device flag wakeup_prepared\n PCI / ACPI PM: Rework some debug messages\n PCI PM: Simplify PCI wake-up code\n ...\n\nFixed up conflict in arch/powerpc/kernel/pci_64.c due to OF device tree\nscanning having been moved and merged for the 32- and 64-bit cases. The\n\u0027needs_freset\u0027 initialization added in 6e19314cc (\"PCI/powerpc: support\nPCIe fundamental reset\") is now in arch/powerpc/kernel/pci_of_scan.c.\n" }, { "commit": "1aaf2e59135fd67321f47c11c64a54aac27014e9", "tree": "633ffa4db3ac6e8d566cba549510561ffd61d8f4", "parents": [ "66a4fe0cb80a9fde8cb173289afb863fd279466a", "936e894a976dd3b0f07f1f6f43c17b77b7e6146d" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Sep 15 09:19:20 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Sep 15 09:19:20 2009 -0700" }, "message": "Merge branch \u0027x86-txt-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip\n\n* \u0027x86-txt-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:\n x86, intel_txt: clean up the impact on generic code, unbreak non-x86\n x86, intel_txt: Handle ACPI_SLEEP without X86_TRAMPOLINE\n x86, intel_txt: Fix typos in Kconfig help\n x86, intel_txt: Factor out the code for S3 setup\n x86, intel_txt: tboot.c needs \u003casm/fixmap.h\u003e\n intel_txt: Force IOMMU on for Intel TXT launch\n x86, intel_txt: Intel TXT Sx shutdown support\n x86, intel_txt: Intel TXT reboot/halt shutdown support\n x86, intel_txt: Intel TXT boot support\n" }, { "commit": "133309a89e7430f907ebe85e78906ee12c311727", "tree": "daa96e6e82b63c0ef1538dcbb455d13595a1c83d", "parents": [ "5489375d481c8456c8259b48e107d03b05309d1d", "fc8e1ead9314cf0e0f1922e661428b93d3a50d88" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Sep 14 17:56:51 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Sep 14 17:56:51 2009 -0700" }, "message": "Merge branch \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input\n\n* \u0027for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input: (52 commits)\n Input: bcm5974 - silence uninitialized variables warnings\n Input: wistron_btns - add keymap for AOpen 1557\n Input: psmouse - use boolean type\n Input: i8042 - use platform_driver_probe\n Input: i8042 - use boolean type where it makes sense\n Input: i8042 - try disabling and re-enabling AUX port at close\n Input: pxa27x_keypad - allow modifying keymap from userspace\n Input: sunkbd - fix formatting\n Input: i8042 - bypass AUX IRQ delivery test on laptops\n Input: wacom_w8001 - simplify querying logic\n Input: atkbd - allow setting force-release bitmap via sysfs\n Input: w90p910_keypad - move a dereference below a NULL test\n Input: add twl4030_keypad driver\n Input: matrix-keypad - add function to build device keymap\n Input: tosakbd - fix cleaning up KEY_STROBEs after error\n Input: joydev - validate axis/button maps before clobbering current ones\n Input: xpad - add USB ID for the drumkit controller from Rock Band\n Input: w90p910_keypad - rename driver name to match platform\n Input: add new driver for Sentelic Finger Sensing Pad\n Input: psmouse - allow defining read-only attributes\n ...\n" }, { "commit": "5e3573db2bd5db6925159279d99576a4635bdb66", "tree": "a90efab044203abfda470f464cd056fe97497121", "parents": [ "e81995bb1c0077a312cb621abc406a36f65a986a" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Mon Sep 14 16:35:40 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Sep 14 17:39:14 2009 -0700" }, "message": "PCI hotplug: clean up acpi_run_hpp()\n\nThis patch cleans up acpi_run_hpp() and follows the style of acpi_run_hpx():\n - remove unnecessary METHOD_NAME__HPP #define\n - use ACPI_ALLOCATE_BUFFER rather than evaluating _HPP twice\n - validate _HPP package length (defined as 4 by the spec)\n - avoid ref to undefined data if FW provides \u003c 4 elements\n - remove temporary nui[] array\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nReviewed-by: Alex Chiang \u003cachiang@hp.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nAcked-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "e81995bb1c0077a312cb621abc406a36f65a986a", "tree": "9a451882e0c1528b4fbd9781605e0850d7bcb693", "parents": [ "11876e52e9148bf923795d6fcf8abed7f3662aaa" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Mon Sep 14 16:35:35 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Sep 14 17:39:12 2009 -0700" }, "message": "PCI hotplug: acpiphp: use generic pci_configure_slot()\n\nUse the generic pci_configure_slot() rather than the acpiphp-specific\ndecode_hpp() and program_hpp().\n\nUnlike the previous acpiphp-specific code, pci_configure_slot() programs\nPCIe settings when an _HPX method provides them, so acpiphp-managed PCIe\ndevices can now be configured.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nAcked-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "11876e52e9148bf923795d6fcf8abed7f3662aaa", "tree": "26c92c1064261e0c47897c4d1d14e52eda6a2a62", "parents": [ "d569c74d78ffcde2f163256e4da934ec3bacff0e" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Mon Sep 14 16:35:30 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Sep 14 17:39:11 2009 -0700" }, "message": "PCI hotplug: shpchp: use generic pci_configure_slot()\n\nUse the generic pci_configure_slot() rather than the SHPC-specific\nprogram_fw_provided_values().\n\nUnlike the previous SHPC-specific code, pci_configure_slot() programs PCIe\nsettings when an _HPX method provides them, so if it\u0027s possible to have an\nSHPC-managed PCIe device, it can now be configured.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nAcked-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "d569c74d78ffcde2f163256e4da934ec3bacff0e", "tree": "a4652df85c274f60b5677ac266e88f99e990f87c", "parents": [ "8838400db5193c37588813c2eb1249b821781950" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Mon Sep 14 16:35:25 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Sep 14 17:39:09 2009 -0700" }, "message": "PCI hotplug: pciehp: use generic pci_configure_slot()\n\nUse the generic pci_configure_slot() rather than the PCIe-specific\nprogram_fw_provided_values().\n\nUnlike the previous pciehp-specific code, we now walk through subordinate\ndevices even if there are no settings for the parent. This should be\nharmless because we won\u0027t change anything unless we discover firmware\nsettings farther down.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nAcked-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "8838400db5193c37588813c2eb1249b821781950", "tree": "9ddd0bfc93c0a0516d9af2aa450e5d41e9786bb7", "parents": [ "6a29172ba90e49c046245610caff9848307bfd6a" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Mon Sep 14 16:35:20 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Sep 14 17:39:05 2009 -0700" }, "message": "PCI hotplug: add pci_configure_slot()\n\nThis patch adds a new pci_configure_slot() function that programs the\nPCI bus characteristics for a newly-added device. This is based on\ncode in pciehp_pci.c, but should be generic enough to be used by pciehp,\nshpchp, and acpiphp.\n\nThe hotplug_params struct and the program_hpp_typeX() functions are based\non the ACPI definitions, but they aren\u0027t really ACPI-specific, and there\u0027s\nno alternate implementation, so I don\u0027t see the need to abstract them yet.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nReviewed-by: Alex Chiang \u003cachiang@hp.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nAcked-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "6a29172ba90e49c046245610caff9848307bfd6a", "tree": "41911e0b90cb6bec026f9eb2d4cc5e0f914afa75", "parents": [ "fca6825ad7382ae9df8ecda9068ac13ee9e343f4" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Mon Sep 14 16:35:15 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Sep 14 17:38:26 2009 -0700" }, "message": "PCI hotplug: clean up acpi_get_hp_params_from_firmware() interface\n\nThis patch makes acpi_get_hp_params_from_firmware() take a\npci_dev rather than a pci_bus and makes it return a standard\nint errno rather than acpi_status.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nAcked-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "fca6825ad7382ae9df8ecda9068ac13ee9e343f4", "tree": "2a1c1f852b049bb9f834f5cb443be39851022cc7", "parents": [ "dffb4bb560ed73937a52c68c304b232c743b49f7" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Mon Sep 14 16:35:10 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Sep 14 17:38:22 2009 -0700" }, "message": "PCI hotplug: acpiphp: don\u0027t cache hotplug_params in acpiphp_bridge\n\nWe always look up hotplug_params with decode_hpp() immediately before using\nthem, so we don\u0027t need to save them in the acpiphp_bridge struct. This\npatch follows the example of program_fw_provided_values() in pciehp_pci.c\nand shpchp_pci.c by just keeping the params on the stack while we need them.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nReviewed-by: Alex Chiang \u003cachiang@hp.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nAcked-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "dffb4bb560ed73937a52c68c304b232c743b49f7", "tree": "f2f0901b3a90c5a66ea140d1d7de52d1c7ba7924", "parents": [ "4b77b0a2ba27d64f58f16d8d4d48d8319dda36ff" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Mon Sep 14 16:35:05 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Sep 14 17:38:19 2009 -0700" }, "message": "PCI hotplug: acpiphp: remove superfluous _HPP/_HPX evaluation\n\ndecode_hpp() looks up hotplug PCI parameters from ACPI and saves them\nin the acpiphp_bridge structure. These parameters (in bridge-\u003ehpp) are\nonly used by the acpiphp_set_hpp_values() -\u003e program_hpp() path. In\nthat path, we always call decode_hpp() before program_hpp(), so there\u0027s\nno need to do it in init_bridge_misc().\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nReviewed-by: Alex Chiang \u003cachiang@hp.com\u003e\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nAcked-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "4b77b0a2ba27d64f58f16d8d4d48d8319dda36ff", "tree": "957f38dc1065e2880197e7ca5ffe1592515010b3", "parents": [ "999cce4a52d5abdda5d2cec6bac241899bc19e4c" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Wed Sep 09 23:49:59 2009 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Sep 14 13:41:46 2009 -0700" }, "message": "PCI: Clear saved_state after the state has been restored\n\nSome PCI devices fail if their standard configuration registers are\nrestored twice in a row. Prevent this from happening by making\npci_restore_state() clear the saved_state flag of the device right\nafter the device\u0027s standard configuration registers have been\npopulated with the previously saved values.\n\nSimplify PCI PM callbacks by removing the direct clearing of\nstate_saved from them, as it shouldn\u0027t be necessary any more (except\nin pci_pm_thaw(), where it has to be cleared, so that the values saved\nduring the \"freeze\" phase of hibernation are not used later by mistake).\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "999cce4a52d5abdda5d2cec6bac241899bc19e4c", "tree": "0702e1050d8b31a377e8aade76777c5f1d45869e", "parents": [ "fdcdaf6c4feca025de2f5e1b6c8e08ba0649e85a" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Wed Sep 09 23:51:27 2009 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Sep 14 13:41:42 2009 -0700" }, "message": "PCI PM: Return error codes from pci_pm_resume()\n\nCurrently pci_pm_resume() always returns 0, which makes the error\nvariable defined in there a bit pointless. Make pci_pm_resume()\nreturn error codes obtained from drivers\u0027 callbacks.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "fdcdaf6c4feca025de2f5e1b6c8e08ba0649e85a", "tree": "95ccb85ea58a025189652b067c8d03f5f3fd1e99", "parents": [ "e9d8288871efa0d98a1d1d1f17976b5b00a0234d" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Mon Sep 14 14:36:41 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Sep 14 13:39:00 2009 -0700" }, "message": "PCI: use dev_printk in quirk messages\n\nConvert quirk printks to dev_printk().\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nCC: Olaf Dabrunz \u003cod@suse.de\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "e9d8288871efa0d98a1d1d1f17976b5b00a0234d", "tree": "d446e04d904afeb5bda9598ec526d9beef2c5e95", "parents": [ "7f53866932fd08add06ee2f93ead129949158490" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Mon Sep 14 22:25:11 2009 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Sep 14 13:38:55 2009 -0700" }, "message": "PCI / PCIe portdrv: Fix pcie_portdrv_slot_reset()\n\nAfter commit c82f63e411f1b58427c103bd95af2863b1c96dd1\n(PCI: check saved state before restore) pcie_portdrv_slot_reset()\nmay not work correctly if dev-\u003eerror_state is equal to\npci_channel_io_frozen, because dev-\u003estate_saved need not be set at\nthat time. Fix this issue by setting dev-\u003estate_saved before\npci_restore_state() is called in pcie_portdrv_slot_reset().\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "7f53866932fd08add06ee2f93ead129949158490", "tree": "f01520afe3708a3c79233fa67d50124f0dac6335", "parents": [ "6edd7679db92376ca54f328d6b0f12291c2dab35" ], "author": { "name": "Alex Chiang", "email": "achiang@hp.com", "time": "Thu Sep 10 12:34:09 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Sep 14 08:46:58 2009 -0700" }, "message": "PCI Hotplug: convert acpi_pci_detect_ejectable() to take an acpi_handle\n\nacpi_pci_detect_ejectable() goes through effort to convert its\nstruct pci_bus arg to an acpi_handle, but every time we use this\ninterface, we already have the handle available.\n\nSo let\u0027s just use the handle instead of converting back and forth.\n\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nTested-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "6edd7679db92376ca54f328d6b0f12291c2dab35", "tree": "b04ce7c5965e30914f3ba6e70f6553363552d23f", "parents": [ "9965976a38f66fc170fc0528b3115bf1a8a58b0a" ], "author": { "name": "Alex Chiang", "email": "achiang@hp.com", "time": "Thu Sep 10 12:34:04 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Sep 14 08:46:48 2009 -0700" }, "message": "PCI Hotplug: acpiphp: find bridges the easy way\n\nInstead of constantly evaluating _ADR and _SEG over and over again,\nlet\u0027s simplify our lives by using:\n\n\tacpi_pci_find_root() for root bridges\n\tacpi_get_pci_dev() for p2p bridges\n\nThis change eliminates some copy \u0027n paste code and also allows us\nto simplify some internal interfaces.\n\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nTested-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nCc: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "86373435d2299b722ec87c416005953215f049c1", "tree": "40d9c8e8bdf2f48b9c69c3423cdad3c0feded67e", "parents": [ "483e3cd6a34ad2d7e41100bc1b98614ac42a4567", "c984123c7a888731b7e971e1c878b6f2b716b292" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Sep 11 16:38:33 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Sep 11 16:38:33 2009 -0700" }, "message": "Merge branch \u0027upstream-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev\n\n* \u0027upstream-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev: (25 commits)\n pata_rz1000: use printk_once\n ahci: kill @force_restart and refine CLO for ahci_kick_engine()\n pata_cs5535: add pci id for AMD based CS5535 controllers\n ahci: Add AMD SB900 SATA/IDE controller device IDs\n drivers/ata: use resource_size\n sata_fsl: Defer non-ncq commands when ncq commands active\n libata: add SATA PMP revision information for spec 1.2\n libata: fix off-by-one error in ata_tf_read_block()\n ahci: Gigabyte GA-MA69VM-S2 can\u0027t do 64bit DMA\n ahci: make ahci_asus_m2a_vm_32bit_only() quirk more generic\n dmi: extend dmi_get_year() to dmi_get_date()\n dmi: fix date handling in dmi_get_year()\n libata: unbreak TPM filtering by reorganizing ata_scsi_pass_thru()\n sata_sis: convert to slave_link\n sata_sil24: always set protocol override for non-ATAPI data commands\n libata: Export AHCI capabilities\n libata: Delegate nonrot flag setting to SCSI\n [libata] Add pata_rdc driver for RDC ATA devices\n drivers/ata: Remove unnecessary semicolons\n libata: remove spindown skipping and warning\n ...\n" }, { "commit": "12a499612e1ff439bdad240c7f86c55366941d4d", "tree": "9fd218631e0c8c26a5ffc41ebce1d65f8e826339", "parents": [ "eee2775d9924b22643bd89b2e568cc5eed7e8a04", "70590ea75b7f9ef4846b0b0f4400e8338dbcc7eb" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Sep 11 13:20:42 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Sep 11 13:20:42 2009 -0700" }, "message": "Merge branch \u0027irq-core-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip\n\n* \u0027irq-core-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:\n pci/intr_remapping: Allocate irq_iommu on node\n irq: Add irq_node() primitive\n irq: Make sure irq_desc for legacy irq get correct node setting\n genirq: Add prototype for handle_nested_irq()\n irq: Remove superfluous NULL pointer check in check_irq_resend()\n irq: Clean up by removing irqfixup MODULE_PARM_DESC()\n genirq: Fix comment describing suspend_device_irqs()\n genirq: Remove obsolete defines and typedefs\n" }, { "commit": "9965976a38f66fc170fc0528b3115bf1a8a58b0a", "tree": "9814ad7063145c84b05499efbb52ca8bb5f66340", "parents": [ "0baed8da1ed91b664759f6c7f955b3a804457389" ], "author": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Sep 11 08:46:07 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Sep 11 08:46:07 2009 -0700" }, "message": "PCI: pcie portdrv: remove unused variable\n\nRemove unused port_data variable left over from the MCH hotplug quirk\ncleanup.\n\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "074835f0143b83845af5044af2739c52c9f53808", "tree": "f573860163fda805b97656f7bc400f148179e1a9", "parents": [ "e936d0773df172ec8600777fdd72bbc1f75f22ad" ], "author": { "name": "Youquan Song", "email": "youquan.song@intel.com", "time": "Wed Sep 09 12:05:39 2009 -0400" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Fri Sep 11 16:40:10 2009 +0100" }, "message": "intel-iommu: Fix kernel hang if interrupt remapping disabled in BIOS\n\nBIOS clear DMAR table INTR_REMAP flag to disable interrupt remapping. Current\nkernel only check interrupt remapping(IR) flag in DRHD\u0027s extended capability\nregister to decide interrupt remapping support or not. But IR flag will not\nchange when BIOS disable/enable interrupt remapping.\n\nWhen user disable interrupt remapping in BIOS or BIOS often defaultly disable\ninterrupt remapping feature when BIOS is not mature.Though BIOS disable\ninterrupt remapping but intr_remapping_supported function will always report\nto OS support interrupt remapping if VT-d2 chipset populated. On this\ncases, kernel will continue enable interrupt remapping and result kernel panic.\nThis bug exist on almost all platforms with interrupt remapping support.\n\nThis patch add DMAR table INTR_REMAP flag check before enable interrupt\nremapping.\n\nSigned-off-by: Youquan Song \u003cyouquan.song@intel.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "e936d0773df172ec8600777fdd72bbc1f75f22ad", "tree": "c778f4d6aaee3e9ecbccbb4d0d31565a78e49a26", "parents": [ "adb2fe0277607d50f4e9ef06e1d180051a609c25" ], "author": { "name": "Youquan Song", "email": "youquan.song@intel.com", "time": "Mon Sep 07 10:58:07 2009 -0400" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Fri Sep 11 16:38:53 2009 +0100" }, "message": "intel-iommu: Disallow interrupt remapping if not all ioapics covered\n\nCurrent kernel enable interrupt remapping only when all the vt-d unit support\ninterrupt remapping. So it is reasonable we should also disallow enabling\nintr-remapping if there any io-apics that are not listed under vt-d units.\nOtherwise we can run into issues.\n\nAcked-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nSigned-off-by: Youquan Song \u003cyouquan.song@intel.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "e2dd90b1ad4c61ecb52f2424049d91ce6ccc1f17", "tree": "35bd3a9250963da71bfe0a4bd50e868a0335029b", "parents": [ "041b5eac254107cd3ba60034c38a411531cc64ee" ], "author": { "name": "Shane Huang", "email": "shane.huang@amd.com", "time": "Wed Jul 29 11:34:49 2009 +0800" }, "committer": { "name": "Jeff Garzik", "email": "jgarzik@redhat.com", "time": "Fri Sep 11 02:31:27 2009 -0400" }, "message": "ahci: Add AMD SB900 SATA/IDE controller device IDs\n\nAdd AMD SB900 SATA/IDE controller device IDs.\n\nSigned-off-by: Shane Huang \u003cshane.huang@amd.com\u003e\nSigned-off-by: Jeff Garzik \u003cjgarzik@redhat.com\u003e\n" }, { "commit": "0baed8da1ed91b664759f6c7f955b3a804457389", "tree": "673cb494cb7e98df71c33e16ab304a5618e263fe", "parents": [ "9b83ccd2f14f647936dcfbf4a9a20c501007dd69" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Tue Sep 08 23:16:24 2009 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 14:19:24 2009 -0700" }, "message": "PCI / ACPI PM: Propagate wake-up enable for devices w/o ACPI support\n\nSome PCI devices (not PCI Express), like PCI add-on cards, can\ngenerate PME#, but they don\u0027t have any special platform wake-up\nsupport. For this reason, even if they generate PME# to wake up the\nsystem from a sleep state, wake-up events are not generated by the\nplatform.\n\nIt turns out that, at least on some systems, PCI bridges and the PCI\nhost bridge have ACPI GPEs associated with them that, if enabled to\ngenerate wake-up events, allow the system to wake up if one of the\nadd-on devices asserts PME# while the system is in a sleep state.\nFollowing this observation, if a PCI device without direct ACPI\nwake-up support is prepared to wake up the system during a transition\ninto a sleep state (eg. suspend to RAM), try to configure the bridges\non the path from the device to the root bridge to wake-up the system.\n\nReviewed-by: Matthew Garrett \u003cmjg59@srcf.ucam.org\u003e\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "e80bb09d2c73d76a2a4cd79e4a83802dd901c642", "tree": "fff892db62dd092ab8e3d70d19d813d4979a2503", "parents": [ "df8db91fc3b543d373afa61beef35b072eea1368" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Tue Sep 08 23:14:49 2009 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 14:19:11 2009 -0700" }, "message": "PCI PM: Introduce device flag wakeup_prepared\n\nIntroduce a new PCI device flag, wakeup_prepared, to prevent PCI\nwake-up preparation code from being executed twice in a row for the\nsame device and for the same purpose.\n\nReviewed-by: Matthew Garrett \u003cmjg59@srcf.ucam.org\u003e\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "df8db91fc3b543d373afa61beef35b072eea1368", "tree": "969c172b1a301e55365668f1e7e6ba0a7e3a0818", "parents": [ "5bcc2fb4e8157d829a38093b98e23329ac8acff7" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Tue Sep 08 23:13:49 2009 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 14:19:06 2009 -0700" }, "message": "PCI / ACPI PM: Rework some debug messages\n\nMove a debug message from acpi_pci_sleep_wake() to\nacpi_pm_device_sleep_wake() and use the standard dev_*() macros\nin there.\n\nReviewed-by: Matthew Garrett \u003cmjg59@srcf.ucam.org\u003e\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "5bcc2fb4e8157d829a38093b98e23329ac8acff7", "tree": "458960ac494d1427ec96cbbfcaa68bd7c0e0b778", "parents": [ "748df9a4c65625c386674c9b54dde73de6cc5af5" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Tue Sep 08 23:12:59 2009 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 14:19:00 2009 -0700" }, "message": "PCI PM: Simplify PCI wake-up code\n\nRework the PCI wake-up code so that it\u0027s easier to read without\nchanging the functionality.\n\nReviewed-by: Matthew Garrett \u003cmjg59@srcf.ucam.org\u003e\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "28760489a3f1e136c5ae8581c0fa8f63511f2f4c", "tree": "a3c890e9c8d9e98385691d56f5c007d280514fe5", "parents": [ "0ba379ec0fb182a87b8891c5754abbcd9c035b4f" ], "author": { "name": "Eric W. Biederman", "email": "ebiederm@aristanetworks.com", "time": "Wed Sep 09 14:09:24 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 14:10:24 2009 -0700" }, "message": "PCI: pcie: Ensure hotplug ports have a minimum number of resources\n\nIn general a BIOS may goof or we may hotplug in a hotplug controller.\nIn either case the kernel needs to reserve resources for plugging\nin more devices in the future instead of creating a minimal resource\nassignment.\n\nWe already do this for cardbus bridges I am just adding a variant\nfor pcie bridges.\n\nv2: Make testing for pcie hotplug bridges based on a flag.\n\n So far we only set the flag for pcie but a header_quirk\n could easily be added for the non-standard pci hotplug\n bridges.\n\nSigned-off-by: Eric W. Biederman \u003cebiederm@aristanetworks.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "0ba379ec0fb182a87b8891c5754abbcd9c035b4f", "tree": "d2678b52e9e92a654f1997a9b6e891f47351c782", "parents": [ "b1c089b7caf18905bd1d87136cf7b8c837254932" ], "author": { "name": "Eric W. Biederman", "email": "ebiederm@xmission.com", "time": "Sun Sep 06 21:48:35 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 14:06:49 2009 -0700" }, "message": "PCI: Simplify hotplug mch quirk.\n\nThere is a very old quirk for the intel E7502 E7320 and E7525 memory\ncontroller hubs that disables usage of msi interrupts on pcie hotplug\nbridges of those devices, and disables changing the affinity of irqs.\n\nToday all we have to do to disable msi on a specific device is to set\ndev-\u003eno_msi, which is much more straightforward than the previous\nlogic.\n\nThe re-running of this fixup after pci hotplug happens below these\ndevices is totally bogus. All of the state we change is pure software\nstate and we don\u0027t change the hardware at all. Which means hotplug on\nthe lower devices doesn\u0027t have a chance to change this state. So we\ncan safely remove the special case from the pciehp driver and the pcie\nportdriver.\n\nI suspect the special case was someone\u0027s expermental debug code that\nslipped in. Certainly it isn\u0027t mentioned in commit\n6fb8880a61510295aece04a542767161f624dffe aka BKrev:\n41966101LJ_ogfOU0m2aE6teZfQnuQ where the code first appears.\n\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: \"Eric W. Biederman\" \u003cebiederm@xmission.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "b1c089b7caf18905bd1d87136cf7b8c837254932", "tree": "52859a8cdd9479c31d8c013f8cb2145cfb5a1a8b", "parents": [ "79e4b89be81b5e53bc4cb51788ca7a45cadb4ef3" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Mon Sep 07 17:16:59 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:50:13 2009 -0700" }, "message": "PCI: pcie, aer: report all error before recovery\n\nThis patch is required not to lost error records by action invoked on\nerror recovery, such as slot reset etc.\n\nFollowing sample (real machine + dummy record injected by aer-inject)\nshows that record of 28:00.1 could not be retrieved by recovery of 28:00.0:\n\n- Before:\n\npcieport-driver 0000:00:02.0: AER: Multiple Uncorrected (Non-Fatal) error received: id\u003d2801\ne1000e 0000:28:00.0: PCIE Bus Error: severity\u003dUncorrected (Non-Fatal), type\u003dTransaction Layer, id\u003d2800(Receiver ID)\ne1000e 0000:28:00.0: device [8086:1096] error status/mask\u003d00001000/00100000\ne1000e 0000:28:00.0: [12] Poisoned TLP (First)\ne1000e 0000:28:00.0: TLP Header: 00000000 00000001 00000002 00000003\ne1000e 0000:28:00.0: broadcast error_detected message\ne1000e 0000:28:00.0: broadcast slot_reset message\ne1000e 0000:28:00.0: setting latency timer to 64\ne1000e 0000:28:00.0: restoring config space at offset 0x1 (was 0x100547, writing 0x100147)\ne1000e 0000:28:00.0: PME# disabled\ne1000e 0000:28:00.0: PME# disabled\ne1000e 0000:28:00.1: setting latency timer to 64\ne1000e 0000:28:00.1: restoring config space at offset 0x1 (was 0x100547, writing 0x100147)\ne1000e 0000:28:00.1: PME# disabled\ne1000e 0000:28:00.1: PME# disabled\ne1000e 0000:28:00.0: broadcast resume message\ne1000e 0000:28:00.0: AER driver successfully recovered\ne1000e: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: RX/TX\n\n- After:\n\npcieport-driver 0000:00:02.0: AER: Multiple Uncorrected (Non-Fatal) error received: id\u003d2801\ne1000e 0000:28:00.0: PCIE Bus Error: severity\u003dUncorrected (Non-Fatal), type\u003dTransaction Layer, id\u003d2800(Receiver ID)\ne1000e 0000:28:00.0: device [8086:1096] error status/mask\u003d00001000/00100000\ne1000e 0000:28:00.0: [12] Poisoned TLP (First)\ne1000e 0000:28:00.0: TLP Header: 00000000 00000001 00000002 00000003\ne1000e 0000:28:00.1: PCIE Bus Error: severity\u003dUncorrected (Non-Fatal), type\u003dTransaction Layer, id\u003d2801(Receiver ID)\ne1000e 0000:28:00.1: device [8086:1096] error status/mask\u003d00081000/00100000\ne1000e 0000:28:00.1: [12] Poisoned TLP (First)\ne1000e 0000:28:00.1: [19] ECRC\ne1000e 0000:28:00.1: TLP Header: 00000000 00000001 00000002 00000003\ne1000e 0000:28:00.1: Error of this Agent(2801) is reported first\ne1000e 0000:28:00.0: broadcast error_detected message\ne1000e 0000:28:00.0: broadcast slot_reset message\ne1000e 0000:28:00.0: setting latency timer to 64\ne1000e 0000:28:00.0: restoring config space at offset 0x1 (was 0x100547, writing 0x100147)\ne1000e 0000:28:00.0: PME# disabled\ne1000e 0000:28:00.0: PME# disabled\ne1000e 0000:28:00.1: setting latency timer to 64\ne1000e 0000:28:00.1: restoring config space at offset 0x1 (was 0x100547, writing 0x100147)\ne1000e 0000:28:00.1: PME# disabled\ne1000e 0000:28:00.1: PME# disabled\ne1000e 0000:28:00.0: broadcast resume message\ne1000e 0000:28:00.0: AER driver successfully recovered\ne1000e: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: RX/TX\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "79e4b89be81b5e53bc4cb51788ca7a45cadb4ef3", "tree": "846f21ae6628559b68778d2e438ac3503c76ca79", "parents": [ "273024ded7b364e1305a31bf4eb197870284f279" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Mon Sep 07 17:16:45 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:50:05 2009 -0700" }, "message": "PCI: pcie, aer: change error print format\n\nUse dev_printk like format.\n\nSample (real machine + dummy error injected by aer-inject):\n\n- Before:\n\n+------ PCI-Express Device Error ------+\nError Severity : Corrected\nPCIE Bus Error type : Data Link Layer\nBad TLP :\nReceiver ID : 2800\nVendorID\u003d8086h, DeviceID\u003d1096h, Bus\u003d28h, Device\u003d00h, Function\u003d00h\n+------ PCI-Express Device Error ------+\nError Severity : Corrected\nPCIE Bus Error type : Data Link Layer\nBad TLP :\nBad DLLP :\nReceiver ID : 2801\nVendorID\u003d8086h, DeviceID\u003d1096h, Bus\u003d28h, Device\u003d00h, Function\u003d01h\nError of this Agent(2801) is reported first\n\n- After:\n\npcieport-driver 0000:00:02.0: AER: Multiple Corrected error received: id\u003d2801\ne1000e 0000:28:00.0: PCIE Bus Error: severity\u003dCorrected, type\u003dData Link Layer, id\u003d2800(Receiver ID)\ne1000e 0000:28:00.0: device [8086:1096] error status/mask\u003d00000040/00000000\ne1000e 0000:28:00.0: [ 6] Bad TLP\ne1000e 0000:28:00.1: PCIE Bus Error: severity\u003dCorrected, type\u003dData Link Layer, id\u003d2801(Receiver ID)\ne1000e 0000:28:00.1: device [8086:1096] error status/mask\u003d000000c0/00000000\ne1000e 0000:28:00.1: [ 6] Bad TLP\ne1000e 0000:28:00.1: [ 7] Bad DLLP\ne1000e 0000:28:00.1: Error of this Agent(2801) is reported first\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "273024ded7b364e1305a31bf4eb197870284f279", "tree": "f3aee59e082b25f8920c6c7d6a3d6ea741325c71", "parents": [ "3472a18773bc6661ea7f8de2b4172db7e00b67e6" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Mon Sep 07 17:16:20 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:49:56 2009 -0700" }, "message": "PCI: pcie, aer: flags to bits\n\nCompact struct and codes.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "3472a18773bc6661ea7f8de2b4172db7e00b67e6", "tree": "fdfc96e3014f8f76b7d3e58cb915880771d809bc", "parents": [ "e7a0d92b19f438011ad76c41755b56ec2ef05f64" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Mon Sep 07 17:16:00 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:49:36 2009 -0700" }, "message": "PCI: pcie, aer: remove unused macros\n\nCleanup.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "e7a0d92b19f438011ad76c41755b56ec2ef05f64", "tree": "f09cc40211ccf8c1b695d6394d9c184ea12b943d", "parents": [ "0d90c3ac0bb89acfbf481c8b06749b00eade6545" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Mon Sep 07 17:13:42 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:49:26 2009 -0700" }, "message": "PCI: pcie, aer: report multiple/first error on a device\n\nMultiple bits might be set in the Uncorrectable Error Status\nregister. But aer_print_error_source() only report a error of\nthe lowest bit set in the error status register.\n\nSo print strings for all bits unmasked and set.\n\nAnd check First Error Pointer to mark the error occured first.\nThis FEP is not valid when the corresponing bit of the Uncorrectable\nError Status register is not set, or unimplemented or undefined.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "0d90c3ac0bb89acfbf481c8b06749b00eade6545", "tree": "1f8bb597f08231c1f715fa6d6c72fa21089c1fef", "parents": [ "24dbb7beb2a207f423006c46830dfaacca5a1139" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Mon Sep 07 17:12:25 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:49:07 2009 -0700" }, "message": "PCI: pcie, aer: refer mask state in mask register properly\n\nERR_{,UN}CORRECTABLE_ERROR_MASK are set of error bits which linux know,\nset of PCI_ERR_COR_* and PCI_ERR_UNC_* defined in linux/pci_regs.h.\nThis masks make aerdrv not to report errors of unknown bit, while aerdrv\nhave ability to report such undefined errors as \"Unknown Error Bit %2d\".\n\nOTOH aerdrv_errprint does not have any check of setting in mask register.\nSo it could report masked wrong error by finding bit in status without\nknowing that the bit is masked in the mask register.\n\nThis patch changes aerdrv to use mask state in mask register propely\ninstead of defined/hardcoded ERR_{,UN}CORRECTABLE_ERROR_MASK.\nThis change prevents aerdrv from reporting masked error, and also enable\nreporting unknown errors.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "24dbb7beb2a207f423006c46830dfaacca5a1139", "tree": "2a2b7b85c11eb784c691c0857c59e8a6053004ae", "parents": [ "0d465f23502e0810443c90a9cf1cf5686c4af4f2" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Mon Sep 07 17:11:29 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:48:19 2009 -0700" }, "message": "PCI: pcie, aer: remove spinlock in aerdrv_errprint.c\n\nThe static buffer errmsg_buff[] is used only for building error\nmessage in fixed format, and is protected by a spinlock.\n\nThis patch removes this buffer and the spinlock.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "0d465f23502e0810443c90a9cf1cf5686c4af4f2", "tree": "7b40a9655387f20895e491ed6d0ad25bc2c66e4c", "parents": [ "1b4ffcf8432f7945e0bd0571f10a2f2bd1dbd850" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Mon Sep 07 17:10:40 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:47:46 2009 -0700" }, "message": "PCI: pcie, aer: fix report of multiple errors\n\nThe flag AER_MULTI_ERROR_VALID_FLAG in info-\u003eflag does mean that the\nroot port receives multiple error messages. Error messages can be\nposted from different devices, so it does not mean that each reported\ndevice has multiple errors.\n\nIf there are multiple error devices and the root port has valid error\nsource ID, it would be nice to report which device is the error source\nreported first.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "1b4ffcf8432f7945e0bd0571f10a2f2bd1dbd850", "tree": "1b95d1740ed46c89c28501e1d947c3c173f75436", "parents": [ "f15857569613a982568be88d034555d88eead0aa" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Mon Sep 07 17:09:58 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:47:32 2009 -0700" }, "message": "PCI: pcie, aer: init struct aer_err_info for reuse\n\nIn case of multiple errors, struct aer_err_info would be reused among\nall reported devices. So the info-\u003estatus should be initialized before\nrecycled. Otherwise error of one device might be reported as the error\nof another device. Also info-\u003eflags has similar problem on reporting\nTLP header.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f15857569613a982568be88d034555d88eead0aa", "tree": "a4d10a5e0f9013c2289226b80f2ee97b4107801d", "parents": [ "bd8fedd045d1d3f4e1f5daca179b0a49949ab538" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Mon Sep 07 17:08:59 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:47:16 2009 -0700" }, "message": "PCI: pcie, aer: rework MASK macros in aerdrv_errprint.c\n\nDefinitions of MASK macros in aerdrv_errprint.c are tricky and unsafe.\n\nFor example, AER_AGENT_TRANSMITTER_MASK(_sev, _stat) does work like:\n static inline func(int _sev, int _stat)\n {\n if (_sev \u003d\u003d AER_CORRECTABLE)\n return (_stat \u0026 (PCI_ERR_COR_REP_ROLL|PCI_ERR_COR_REP_TIMER));\n else\n return (_stat \u0026 PCI_ERR_COR_REP_ROLL);\n }\nIn case of else path here, for uncorrectable errors, testing bits in\n_stat by PCI_ERR_COR_* does not make sense because _stat should have only\nPCI_ERR_UNC_* bits originated in uncorrectable error status register.\nBut at this time this is safe because uncorrectable error using bit\nposition same to PCI_ERR_COR_REP_ROLL(\u003d bit position 8) is not defined.\nLikewise, AER_AGENT_COMPLETER_MASK is always PCI_ERR_UNC_COMP_ABORT but\nit works because bit 15 of correctable error status is not defined.\n\nIt means that these MASK macros will turn to be wrong once if new error\nis defined. (In fact, bit 15 of correctable is now defined in PCIe 2.1)\n\nThis patch changes these MASK macros to be more strict, not to return\nPCI_ERR_COR_* bits for uncorrectable error status and vise versa.\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "bd8fedd045d1d3f4e1f5daca179b0a49949ab538", "tree": "85d6c0739f0c461b9976a0ae1b3f2800751a4d33", "parents": [ "c9a918838c07cbef934c8ef818d8f0e719015c3a" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Mon Sep 07 17:08:14 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:46:54 2009 -0700" }, "message": "PCI: pcie, aer: AER_PR for printing in aerdrv_errprint.c\n\nAdd workaround macro to reduce the number of checkpatch warning:\n WARNING: printk() should include KERN_ facility level\n\nBefore:\n total: 0 errors, 10 warnings, 247 lines checked\nAfter:\n total: 0 errors, 1 warnings, 243 lines checked\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "c9a918838c07cbef934c8ef818d8f0e719015c3a", "tree": "fa0978d67632a15fdd014f448ac099ab1ec8df75", "parents": [ "b439b1d4e3ae3c36ed94ed233119ff0d145af257" ], "author": { "name": "Hidetoshi Seto", "email": "seto.hidetoshi@jp.fujitsu.com", "time": "Mon Sep 07 17:07:29 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:46:18 2009 -0700" }, "message": "PCI: pcie, aer: checkpatch style cleanup in pcie/aer/*\n\nBefore:\n drivers/pci/pcie/aer/aer_inject.c\n total: 4 errors, 4 warnings, 473 lines checked\n drivers/pci/pcie/aer/aerdrv.c\n total: 5 errors, 2 warnings, 333 lines checked\n drivers/pci/pcie/aer/aerdrv.h\n total: 1 errors, 0 warnings, 139 lines checked\n drivers/pci/pcie/aer/aerdrv_core.c\n total: 4 errors, 3 warnings, 872 lines checked\n drivers/pci/pcie/aer/aerdrv_errprint.c\n total: 12 errors, 11 warnings, 248 lines checked\n\nAfter:\n drivers/pci/pcie/aer/aer_inject.c\n total: 0 errors, 0 warnings, 466 lines checked\n drivers/pci/pcie/aer/aerdrv.c\n total: 0 errors, 0 warnings, 335 lines checked\n drivers/pci/pcie/aer/aerdrv.h\n total: 0 errors, 0 warnings, 139 lines checked\n drivers/pci/pcie/aer/aerdrv_core.c\n total: 0 errors, 0 warnings, 869 lines checked\n drivers/pci/pcie/aer/aerdrv_errprint.c\n total: 0 errors, 10 warnings, 247 lines checked\n\nSigned-off-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nReviewed-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "b439b1d4e3ae3c36ed94ed233119ff0d145af257", "tree": "073a9a0acdeb203bd7735a0a91c2b5f397f74852", "parents": [ "9dba910e9de2c4aa15ec1286f10052c107ef48ca" ], "author": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Thu Sep 03 15:27:27 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:44:34 2009 -0700" }, "message": "PCI: pci-stub: add pci_stub.ids parameter\n\nAdd ids module parameter which allows specifying initial IDs for the\npci-stub driver. When built into the kernel, pci-stub is linked\nbefore any real pci drivers and by setting up IDs from initialization\nit can prevent built-in drivers from attaching to specific devices.\n\nWhile at it, make pci_stub_probe() print out about devices it grabbed\nto weed out \"but my controller isn\u0027t being probed\" bug reports.\n\nSigned-off-by: Tejun Heo \u003ctj@kernel.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "9dba910e9de2c4aa15ec1286f10052c107ef48ca", "tree": "4870eccc95e406ae8d490136f5d65953203418c8", "parents": [ "825c423a35a80a8fd66398a3f9bde7f0b0187a76" ], "author": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Thu Sep 03 15:26:36 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:43:58 2009 -0700" }, "message": "PCI: separate out pci_add_dynid()\n\nSeparate out pci_add_dynid() from store_new_id() and export it so that\nin-kernel code can add PCI IDs dynamically. As the function will be\navailable regardless of HOTPLUG, put it and pull pci_free_dynids()\noutside of CONFIG_HOTPLUG.\n\nThis will be used by pci-stub to initialize initial IDs via module\nparam.\n\nWhile at it, remove bogus get_driver() failure check.\n\nSigned-off-by: Tejun Heo \u003ctj@kernel.org\u003e\nAcked-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\nReviewed-by: Grant Grundler \u003cgrundler@parisc-linux.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "825c423a35a80a8fd66398a3f9bde7f0b0187a76", "tree": "581b7f199a5fe0543a78139e18f05520964f2488", "parents": [ "6ed6a8dc83dc37d30c8a7ff2eae2ed054e34c91b" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Jul 29 14:39:58 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:29:50 2009 -0700" }, "message": "PCI hotplug: add support for 5.0G link speed\n\nAdd support for PCI-E 5.0 GT/s in max_bus_speed and cur_bus_speed.\n\nReviewed-by: Matthew Wilcox \u003cmatthew@wil.cx\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "6ed6a8dc83dc37d30c8a7ff2eae2ed054e34c91b", "tree": "6c81de63866cf4c14c846479f188696b8aacb6ba", "parents": [ "ac18018a414a90d841ea81d38fecb913c0ec1880" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Jul 29 14:39:07 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:29:49 2009 -0700" }, "message": "PCI hotplug: fix typo in pcie link speed info\n\nFix typo in PCI-E link speed.\n\nReviewed-by: Matthew Wilcox \u003cmatthew@wil.cx\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "ac18018a414a90d841ea81d38fecb913c0ec1880", "tree": "21eeedf2a160f50ae6f6bcba1ef7d5ee5d6cbfb4", "parents": [ "b7206cbf024dd43c42f9585e2017db1c1facd566" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Aug 19 11:02:13 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:29:49 2009 -0700" }, "message": "PCI ASPM: support per direction l0s management\n\nThe L0s state can be managed separately for each direction (upstream\ndirection and downstream direction) of the link. But in the current\nimplementation, those are mixed up. With this patch, L0s for each\ndirection are managed separately.\n\nTo maintain three states (upstream direction L0s, downstream L0s and\nL1), \u0027aspm_support\u0027, \u0027aspm_enabled\u0027, \u0027aspm_capable\u0027, \u0027aspm_disable\u0027\nand \u0027aspm_default\u0027 fields in struct pcie_link_state are changed to\n3-bit from 2-bit. The \u0027latency\u0027 field is separated to two \u0027latency_up\u0027\nand \u0027latency_dw\u0027 fields to maintain exit latencies for each direction\nof the link. For L0, \u0027latency_up.l0\u0027 and \u0027latency_dw.l0\u0027 are used to\nconfigure upstream direction L0s and downstream direction L0s\nrespectively. For L1, larger value of \u0027latency_up.l1\u0027 and\n\u0027latency_dw.l1\u0027 is considered as L1 exit latency.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "b7206cbf024dd43c42f9585e2017db1c1facd566", "tree": "cf84dccb916f90e445c08b244939a25203874aec", "parents": [ "07d92760d2ee542fe932f4e8b5807dd98481d1fd" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Aug 19 11:01:37 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:29:48 2009 -0700" }, "message": "PCI ASPM: support partial aspm enablement\n\nIn the current implementation, ASPM L0s/L1 is disabled for all links\nin the hierarchy if one of the link doesn\u0027t meet latency requirement.\nBut we can partially enable ASPM L0s/L1 on sub-tree in the hierarchy.\nThis patch allows partial L0s/L1 enablement in the hierarchy. And it\nalso reduce the calculation cost of ASPM configuration very much.\n\nIn the previous implementation, all links were enabled with the same\nstate. With this patch, enabled state for each link is determined\nsimply as follows (the \u0027requested\u0027 is from policy_to_aspm_state()).\n\n enabled \u003d requested \u0026 (link-\u003easpm_capable \u0026 link-\u003easpm_disable)\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "07d92760d2ee542fe932f4e8b5807dd98481d1fd", "tree": "47d94230d73567b16f9c9a307d1c8f08eff47184", "parents": [ "f1c0ca29ae72bc0c10282eada66c8a792ee98482" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Aug 19 11:00:25 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:29:47 2009 -0700" }, "message": "PCI ASPM: introduce capable flag\n\nIntroduce \u0027aspm_capable\u0027 field to maintain the capable ASPM setting of\nthe link. By the \u0027aspm_capable\u0027, we don\u0027t need to recheck latency\nevery time ASPM policy is changed.\n\nEach bit in \u0027aspm_capable\u0027 is associated to ASPM state (L0S/L1). The\nbit is set if the associated ASPM state is supported by the link and\nit satisfies the latency requirement (i.e. exit latency \u003c endpoint\nacceptable latency). The \u0027aspm_capable\u0027 is updated when\n\n - an endpoint device is added (boot time or hot-plug time)\n - an endpoint device is removed (hot-unplug time)\n - PCI power state is changed.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "f1c0ca29ae72bc0c10282eada66c8a792ee98482", "tree": "4629fc8c5f0a8537376636b997f6a62dddc63ac2", "parents": [ "fc87e919c0ce8e213edf2ffca17f384f059873d3" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Aug 19 10:59:52 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:29:46 2009 -0700" }, "message": "PCI ASPM: introduce disable flag\n\nIntroduce \u0027aspm_disable\u0027 flag to manage disabled ASPM state more\nrobust way.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "fc87e919c0ce8e213edf2ffca17f384f059873d3", "tree": "0bd3d67b0320c486e9ec1c846569c3a72baf6bc7", "parents": [ "8a339e7321f10dc2f28928ffadb69b6c7c2d5c3b" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Aug 19 10:58:46 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:29:45 2009 -0700" }, "message": "PCI ASPM: fix possible null pointer dereference\n\nFix possible NULL dereference in pcie_aspm_exit_link_state(). This\npatch also cleanup some code.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "8a339e7321f10dc2f28928ffadb69b6c7c2d5c3b", "tree": "b89669aed567cced569a0eb1fcb557268f608cee", "parents": [ "b127bd55d9cd9d5b40278b30645669d6d46933bc" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Aug 19 10:58:09 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:29:45 2009 -0700" }, "message": "PCI ASPM: remove redundant list check\n\nRemove the following check in __pcie_aspm_config_link() because it\nnerver be true.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "b127bd55d9cd9d5b40278b30645669d6d46933bc", "tree": "93aed7b6e6d0f164ee2678f36fe87c9a68ba5114", "parents": [ "6f1186be4feb3364d3a52cbea81e43e4d5296196" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Aug 19 10:57:31 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:29:44 2009 -0700" }, "message": "PCI ASPM: do not clear enabled field by support field\n\nWe must not clear bits in \u0027aspm_enabled\u0027 using \u0027aspm_support\u0027, or\n\u0027aspm_enabled\u0027 and \u0027aspm_default\u0027 might be different from the actual\nstate. In addtion, \u0027aspm_default\u0027 should be intialized even if\n\u0027aspm_support\u0027 is 0.\n\nAcked-by: Shaohua Li \u003cshaohua.li@intel.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" } ], "next": "6f1186be4feb3364d3a52cbea81e43e4d5296196" }