)]}' { "log": [ { "commit": "661382fe190475c17d0b3a6b5f0350b4f82f5939", "tree": "3609fdecc5b29a6875cbe92cca747096819db7b4", "parents": [ "3c0cb7c31c206aaedb967e44b98442bbeb17a6c4" ], "author": { "name": "Guennadi Liakhovetski", "email": "g.liakhovetski@gmx.de", "time": "Thu Jan 06 17:04:50 2011 +0000" }, "committer": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Fri Jan 07 11:03:26 2011 +0900" }, "message": "dma: shdma: don\u0027t register the global die notifier multiple times\n\nA recent patch has added a die notifier to the shdma driver, however,\nit registers a static die-notifier object in the probe routine, i.e.,\nfor each device instance. This is wrong and leads to a system lockup.\nThis patch moves the die notifier registration to module init and\nexit routines respectively.\n\nReported-by: Magnus Damm \u003cdamm@opensource.se\u003e\nSigned-off-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nSigned-off-by: Paul Mundt \u003clethal@linux-sh.org\u003e\n" }, { "commit": "3c0cb7c31c206aaedb967e44b98442bbeb17a6c4", "tree": "3ecba45d7ffae4fba4a5aafaef4af5b0b1105bde", "parents": [ "f70f5b9dc74ca7d0a64c4ead3fb28da09dc1b234", "404a02cbd2ae8bf256a2fa1169bdfe86bb5ebb34" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Jan 06 16:50:35 2011 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Jan 06 16:50:35 2011 -0800" }, "message": "Merge branch \u0027devel\u0027 of master.kernel.org:/home/rmk/linux-2.6-arm\n\n* \u0027devel\u0027 of master.kernel.org:/home/rmk/linux-2.6-arm: (416 commits)\n ARM: DMA: add support for DMA debugging\n ARM: PL011: add DMA burst threshold support for ST variants\n ARM: PL011: Add support for transmit DMA\n ARM: PL011: Ensure IRQs are disabled in UART interrupt handler\n ARM: PL011: Separate hardware FIFO size from TTY FIFO size\n ARM: PL011: Allow better handling of vendor data\n ARM: PL011: Ensure error flags are clear at startup\n ARM: PL011: include revision number in boot-time port printk\n ARM: vexpress: add sched_clock() for Versatile Express\n ARM i.MX53: Make MX53 EVK bootable\n ARM i.MX53: Some bug fix about MX53 MSL code\n ARM: 6607/1: sa1100: Update platform device registration\n ARM: 6606/1: sa1100: Fix platform device registration\n ARM i.MX51: rename IPU irqs\n ARM i.MX51: Add ipu clock support\n ARM: imx/mx27_3ds: Add PMIC support\n ARM: DMA: Replace page_to_dma()/dma_to_page() with pfn_to_dma()/dma_to_pfn()\n mx51: fix usb clock support\n MX51: Add support for usb host 2\n arch/arm/plat-mxc/ehci.c: fix errors/typos\n ...\n" }, { "commit": "404a02cbd2ae8bf256a2fa1169bdfe86bb5ebb34", "tree": "99119edc53fdca73ed7586829b8ee736e09440b3", "parents": [ "28cdac6690cb113856293bf79b40de33dbd8f974", "1051b9f0f9eab8091fe3bf98320741adf36b4cfa" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Jan 06 22:33:32 2011 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Thu Jan 06 22:33:32 2011 +0000" }, "message": "Merge branch \u0027devel-stable\u0027 into devel\n\nConflicts:\n\tarch/arm/mach-pxa/clock.c\n\tarch/arm/mach-pxa/clock.h\n" }, { "commit": "f862f904d357dc0d3612347a8dbabe6fae037fbb", "tree": "d7f5c2d5f85fd9e1cfc36beae904dc4f9cca04a3", "parents": [ "6f09e41d704fe0bc9157a5357480751d39361d01", "3c0eee3fe6a3a1c745379547c7e7c904aa64f6d5" ], "author": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Thu Jan 06 18:24:07 2011 +0900" }, "committer": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Thu Jan 06 18:24:07 2011 +0900" }, "message": "Merge branch \u0027master\u0027 of master.kernel.org:/pub/scm/linux/kernel/git/torvalds/linux-2.6 into sh-latest\n\nConflicts:\n\tarch/sh/kernel/cpu/sh2a/clock-sh7201.c\n\nSigned-off-by: Paul Mundt \u003clethal@linux-sh.org\u003e\n" }, { "commit": "1051b9f0f9eab8091fe3bf98320741adf36b4cfa", "tree": "68ea1c8f9c446d6ebd96caf3ba4ec73f1fa5ace6", "parents": [ "cde9efef401563943d5a58eb9b7274bfdc08ca9b", "a58154d1c3535f451a409abbd0bda6770b2d9380" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Jan 05 10:23:38 2011 +0000" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Wed Jan 05 10:23:38 2011 +0000" }, "message": "Merge branch \u0027for-rmk\u0027 of git://git.pengutronix.de/git/imx/linux-2.6 into devel-stable\n" }, { "commit": "d45fa563a62c908d0e9a581d4f091fed6371ebd0", "tree": "84b80c025132e7d4619709dd9134681c8b014fa2", "parents": [ "a1cf11d8f673a3ad91012c5da96beed06ecefde1", "8f33d5277fada0291ea495f7fd44a3e7b7aa41d3" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Jan 03 11:48:54 2011 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Jan 03 11:48:54 2011 -0800" }, "message": "Merge branch \u0027fixes\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx\n\n* \u0027fixes\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx:\n dmaengine: provide dummy functions for DMA_ENGINE\u003dn\n mv_xor: fix race in tasklet function\n" }, { "commit": "8333f65ef094e47020cd01452b4637e7daf5a77f", "tree": "1f41baeedeff9625d25e9c664d3bf762f3371855", "parents": [ "59a609d9b59be9452f168fe228befea53d5962ff" ], "author": { "name": "Saeed Bishara", "email": "saeed@marvell.com", "time": "Tue Dec 21 16:53:39 2010 +0200" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Jan 03 01:39:26 2011 -0800" }, "message": "mv_xor: fix race in tasklet function\n\nuse mv_xor_slot_cleanup() instead of __mv_xor_slot_cleanup() as the former function\naquires the spin lock that needed to protect the drivers data.\n\nCc: \u003cstable@kernel.org\u003e\nSigned-off-by: Saeed Bishara \u003csaeed@marvell.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "1fef891761ddcbd7e57ec3961a0fb748003222ac", "tree": "d192f1677521e17f1a943f8df570dd6449aa0da8", "parents": [ "d3d4b60b12369eded0ea0c5dffee0888ec4d80cd", "1d3f33d541312acd34bd2fa780396d111a0f73b1" ], "author": { "name": "Sascha Hauer", "email": "s.hauer@pengutronix.de", "time": "Mon Jan 03 10:15:11 2011 +0100" }, "committer": { "name": "Sascha Hauer", "email": "s.hauer@pengutronix.de", "time": "Mon Jan 03 10:15:11 2011 +0100" }, "message": "Merge branch \u0027sgu/mxs-core-v8\u0027 of git://git.pengutronix.de/git/ukl/linux-2.6 into imx-for-2.6.38-new\n" }, { "commit": "03aa18f550900855c1d3d17ac83c14a3d668d344", "tree": "6aab2e924e1c11a931fa6e491215e7f6b45b343a", "parents": [ "76496f8f2e104b8bb08db09c063a6817d18829a6" ], "author": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Fri Dec 17 19:16:10 2010 +0900" }, "committer": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Fri Dec 17 19:16:10 2010 +0900" }, "message": "dma: shdma: NMI support.\n\nPresently DMA transfers are interrupted and aborted by the NMI. This\nimplements some basic logic for more gracefully handling and clearing\neach controller\u0027s NMIF flag via the NMI die chain, needed to resume\ntransfers post-NMI.\n\nReported-by: Michael Szafranek \u003cMichael.Szafranek@emtrion.de\u003e\nSigned-off-by: Paul Mundt \u003clethal@linux-sh.org\u003e\n" }, { "commit": "5d43a1de26f37080b75d7c0cf2a0b97523457568", "tree": "824aa8c3a2ee1ce231aa30d2643f21b66c03c919", "parents": [ "7103b71b0ff6a5d8d71438e63dfc539a6f0a61bd", "59a609d9b59be9452f168fe228befea53d5962ff" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Dec 14 13:35:47 2010 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Dec 14 13:35:47 2010 -0800" }, "message": "Merge branch \u0027fixes\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx\n\n* \u0027fixes\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx:\n dmaengine: at_hdmac: fix buffer transfer size specification\n fsldma: fix issue of slow dma\n dmaengine i.MX SDMA: initialize on module_init\n dma : EG20T PCH: Fix miss-setting DMA descriptor\n intel_mid_dma: fix section mismatch warnings\n dmaengine: imx-sdma: fix bug in buffer descriptor initialization\n drivers/dma/ppc4xx: Use printf extension %pR for struct resource\n drivers/dma/ioat: Use the ccflag-y instead of EXTRA_CFLAGS\n drivers/dma/: Use the ccflag-y instead of EXTRA_CFLAGS\n dma: intel_mid_dma: fix double free on mid_setup_dma error path\n dma: imx-dma: fix imxdma_probe error path\n" }, { "commit": "59a609d9b59be9452f168fe228befea53d5962ff", "tree": "6ac0fe91c963ceefea29cf9cea039c4374f6aa24", "parents": [ "f3c677b997757326e1f29d33060719a6a5091950" ], "author": { "name": "Nicolas Ferre", "email": "nicolas.ferre@atmel.com", "time": "Mon Dec 13 13:48:41 2010 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Dec 14 00:39:29 2010 -0800" }, "message": "dmaengine: at_hdmac: fix buffer transfer size specification\n\nBuffer transfer size is the number of transfers to be performed in\nrelation with the width of the _source_ interface.\nSo in the DMA_FROM_DEVICE case, it should be the register width that\nshould be taken into account.\n\nSigned-off-by: Nicolas Ferre \u003cnicolas.ferre@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "f3c677b997757326e1f29d33060719a6a5091950", "tree": "3135e7ee4a04d5abd929cc863168c0c6a574e824", "parents": [ "c989a7fc139ec8975fdc230e2de42f3c4555880e" ], "author": { "name": "Forrest Shi", "email": "b29237@freescale.com", "time": "Thu Dec 09 16:14:04 2010 +0800" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Mon Dec 13 14:05:27 2010 -0800" }, "message": "fsldma: fix issue of slow dma\n\nFixed fsl dma slow issue by initializing dma mode register with\nbandwidth control. It boosts dma performance and should works\nwith 85xx board.\n\nSigned-off-by: Forrest Shi \u003cb29237@freescale.com\u003e\nSigned-off-by: Li Yang \u003cleoli@freescale.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "c989a7fc139ec8975fdc230e2de42f3c4555880e", "tree": "02c2a4d1b8c9210db13c74cbb36882f1d121377c", "parents": [ "943d8d8bca431d6c93f17bf38f4b09c65e0a81d7" ], "author": { "name": "Sascha Hauer", "email": "s.hauer@pengutronix.de", "time": "Mon Dec 06 11:09:57 2010 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Dec 07 15:38:07 2010 -0800" }, "message": "dmaengine i.MX SDMA: initialize on module_init\n\nThe firmware framework gets initialized during fs_initcall time, so\nwe are not allowed to call request_firmware earlier.\n\nSigned-off-by: Sascha Hauer \u003cs.hauer@pengutronix.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "943d8d8bca431d6c93f17bf38f4b09c65e0a81d7", "tree": "e9b81cba5e8c3f761a4848c4e7de73e4ab0b5aab", "parents": [ "cf2f9c59807f173b1c6a537fde7c83c8da876e56" ], "author": { "name": "Tomoya MORINAGA", "email": "tomoya-linux@dsn.okisemi.com", "time": "Wed Dec 01 19:49:48 2010 +0900" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Dec 07 15:07:08 2010 -0800" }, "message": "dma : EG20T PCH: Fix miss-setting DMA descriptor\n\nCurrently, in case of using scatter/gather mode, head of data is not sent to\n\ndestination. The cause is second descriptor address is set to NEXT.\n\nThe NEXT must have head of descriptor address.\n\nThis patch sets head of descriptor address to the NEXT.\n\nAcked-by: Yong Wang \u003cyoug.y.wang@intel.com\u003e\nSigned-off-by: Tomoya MORINAGA \u003ctomoya-linux@dsn.okisemi.com\u003e\n[dan.j.williams@intel.com: fixed up usage of virt_to_phys()]\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "cf2f9c59807f173b1c6a537fde7c83c8da876e56", "tree": "2de933c0f35e842bd08ae90b30edc64acc9a8fa1", "parents": [ "d2f5c276ea4b7b7e1b953926bac9d0b148fcce4e" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Dec 04 14:53:32 2010 -0800" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Dec 04 15:03:56 2010 -0800" }, "message": "intel_mid_dma: fix section mismatch warnings\n\nRename intel_mid_dma_pci to intel_mid_dma_pci_driver to pick up the\napplied annotations of that suffix.\n\nReported-by: \u003cmajor_Lee@wistron.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "d2f5c276ea4b7b7e1b953926bac9d0b148fcce4e", "tree": "5811fc0b75149a20fb5cdc7102d697ec699d005c", "parents": [ "a584bff5efae8c1d026e3a930e3d13a90264fafc" ], "author": { "name": "Anatolij Gustschin", "email": "agust@denx.de", "time": "Mon Nov 22 18:35:18 2010 +0100" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Dec 04 15:03:46 2010 -0800" }, "message": "dmaengine: imx-sdma: fix bug in buffer descriptor initialization\n\nCurrently while submitting scatterlists with more than one SG\nentry the DMA buffer address from the first SG entry is inserted\ninto all initialized DMA buffer descriptors. This is due to the\ntypo in the for_each_sg() loop where the scatterlist pointer is\nused for obtaining the DMA buffer address and _not_ the SG list\niterator.\n\nAs a result all received data will be written only into the first\nDMA buffer while reading. While writing the data from the first\nDMA buffer is send to the device multiple times. This caused\nthe filesystem destruction on the MMC card when using DMA in\nmxcmmc driver.\n\nSigned-off-by: Anatolij Gustschin \u003cagust@denx.de\u003e\nAcked-by: Sascha Hauer \u003cs.hauer@pengutronix.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "a584bff5efae8c1d026e3a930e3d13a90264fafc", "tree": "32aab71b23d45526d51963fb8ad8167375ef524b", "parents": [ "bca364d30d63825f36a03dcacf390943d4c2cb74" ], "author": { "name": "Joe Perches", "email": "joe@perches.com", "time": "Fri Nov 12 13:37:54 2010 -0800" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Dec 04 15:03:40 2010 -0800" }, "message": "drivers/dma/ppc4xx: Use printf extension %pR for struct resource\n\nUsing %pR standardizes the struct resource output.\n\nSigned-off-by: Joe Perches \u003cjoe@perches.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "bca364d30d63825f36a03dcacf390943d4c2cb74", "tree": "cbb5dec99c272e1bb64e3072557df08e328bd966", "parents": [ "87e51107323a84e26a5004337217fc954e8d9545" ], "author": { "name": "Tracey Dent", "email": "tdent48227@gmail.com", "time": "Sat Nov 06 17:01:37 2010 -0400" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Sat Dec 04 15:03:06 2010 -0800" }, "message": "drivers/dma/ioat: Use the ccflag-y instead of EXTRA_CFLAGS\n\nChanged Makefile to use \u003cmodules\u003e-y instead of \u003cmodules\u003e-objs. Following\n(documentation/kbuild/makefiles.txt).\n\nSigned-off-by: Tracey Dent \u003ctdent48227@gmail.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "5b28aa319bba96987316425a1131813d87cbab35", "tree": "7fac8d3e54717355d83ac3d3fd1e4ec7440d7126", "parents": [ "9ab4650f718a0e1cb8792bab4ef97efca4ac75c2" ], "author": { "name": "Sascha Hauer", "email": "s.hauer@pengutronix.de", "time": "Wed Oct 06 15:41:15 2010 +0200" }, "committer": { "name": "Sascha Hauer", "email": "s.hauer@pengutronix.de", "time": "Fri Dec 03 11:04:54 2010 +0100" }, "message": "dmaengine i.MX SDMA: Allow to run without firmware\n\nThe SDMA firmware consists of a ROM part and a RAM part.\nThe ROM part is always present in the SDMA engine and\nis sufficient for many cases.\nThis patch allows to pass in platform data containing\nthe script addresses in ROM, so loading a firmware is\noptional now.\n\nSigned-off-by: Sascha Hauer \u003cs.hauer@pengutronix.de\u003e\nAcked-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "87e51107323a84e26a5004337217fc954e8d9545", "tree": "8472fe98f9f4192579c2e03d200402dc648c4ae9", "parents": [ "51a1efe2e84493439db32c07471e835c752a7923" ], "author": { "name": "Tracey Dent", "email": "tdent48227@gmail.com", "time": "Sat Nov 06 17:01:36 2010 -0400" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Dec 03 01:51:43 2010 -0800" }, "message": "drivers/dma/: Use the ccflag-y instead of EXTRA_CFLAGS\n\nUse the ccflag-y flag instead of EXTRA_CFLAGS because EXTRA_CFLAGS is\ndeprecated and should now be switched. According to (documentation/kbuild/makefiles.txt).\n\nSigned-off-by: Tracey Dent \u003ctdent48227@gmail.com\u003e\nAcked-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "51a1efe2e84493439db32c07471e835c752a7923", "tree": "7608eba539917e5b666c9f67a63aa82449aeb43e", "parents": [ "cbeae41888bddb2d8c23db281de5f38f4be6a9bb" ], "author": { "name": "Axel Lin", "email": "axel.lin@gmail.com", "time": "Tue Nov 02 09:52:17 2010 +0800" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Dec 03 01:46:07 2010 -0800" }, "message": "dma: intel_mid_dma: fix double free on mid_setup_dma error path\n\nWe should not call kfree(dma) in mid_setup_dma error path because\nthe memory is allocated in intel_mid_dma_probe and will be freed\nin intel_mid_dma_probe error path if mid_setup_dma return error.\n\nSigned-off-by: Axel Lin \u003caxel.lin@gmail.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "cbeae41888bddb2d8c23db281de5f38f4be6a9bb", "tree": "ab4a16f0652337986a5def2929e06865e9fbbfbe", "parents": [ "e8a7e48bb248a1196484d3f8afa53bded2b24e71" ], "author": { "name": "Axel Lin", "email": "axel.lin@gmail.com", "time": "Tue Nov 02 09:12:57 2010 +0800" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Dec 03 01:39:03 2010 -0800" }, "message": "dma: imx-dma: fix imxdma_probe error path\n\notherwise, i will be -1 inside the latest iteration of the while loop.\n\nSigned-off-by: Axel Lin \u003caxel.lin@gmail.com\u003e\nAcked-by: Sascha Hauer \u003cs.hauer@pengutronix.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "e5843341e3ad8ff00332376cd0745026e4b5d45f", "tree": "3be222f33d467f1e4da62c231bfe664dcb8cc6b1", "parents": [ "698fd6a2c3ca05ec796072defb5c415289a86cdc" ], "author": { "name": "Guennadi Liakhovetski", "email": "g.liakhovetski@gmx.de", "time": "Wed Nov 24 09:48:10 2010 +0000" }, "committer": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Thu Nov 25 16:29:41 2010 +0900" }, "message": "dma: shdma: add a MODULE_ALIAS() to allow module autoloading\n\nSigned-off-by: Guennadi Liakhovetski \u003cg.liakhovetski@gmx.de\u003e\nSigned-off-by: Paul Mundt \u003clethal@linux-sh.org\u003e\n" }, { "commit": "d2df40857fd57f02906e6ac1484d10cb7accbc86", "tree": "e38165d29e15ada205297786ca33e088ad92a347", "parents": [ "1e431a9d6478940c0b5fcfa1c17a336fc0683409" ], "author": { "name": "Valdis.Kletnieks@vt.edu", "email": "Valdis.Kletnieks@vt.edu", "time": "Fri Oct 29 17:03:46 2010 -0400" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Oct 29 14:14:02 2010 -0700" }, "message": "drivers/dma/Kconfig: add part number for Topcliff.\n\nProduct codenames are OK, but once an actual product name is available,\nit should be referenced as well.\n\n http://ark.intel.com/chipset.aspx?familyID\u003d52499\n\nSigned-off-by: Valdis Kletnieks \u003cvaldis.kletnieks@vt.edu\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "e3e1288e86a07cdeb0aee5860a2dff111c6eff79", "tree": "cd22f8051a456c9d2b95698b6fe402776a67469b", "parents": [ "9ae6d039224def926656206725ae6e89d1331417", "964dc256bb91e990277010a3f6dc66daa130be8b" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Oct 27 19:04:36 2010 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Oct 27 19:04:36 2010 -0700" }, "message": "Merge branch \u0027next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx\n\n* \u0027next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: (48 commits)\n DMAENGINE: move COH901318 to arch_initcall\n dma: imx-dma: fix signedness bug\n dma/timberdale: simplify conditional\n ste_dma40: remove channel_type\n ste_dma40: remove enum for endianess\n ste_dma40: remove TIM_FOR_LINK option\n ste_dma40: move mode_opt to separate config\n ste_dma40: move channel mode to a separate field\n ste_dma40: move priority to separate field\n ste_dma40: add variable to indicate valid dma_cfg\n async_tx: make async_tx channel switching opt-in\n move async raid6 test to lib/Kconfig.debug\n dmaengine: Add Freescale i.MX1/21/27 DMA driver\n intel_mid_dma: change the slave interface\n intel_mid_dma: fix the WARN_ONs\n intel_mid_dma: Add sg list support to DMA driver\n intel_mid_dma: Allow DMAC2 to share interrupt\n intel_mid_dma: Allow IRQ sharing\n intel_mid_dma: Add runtime PM support\n DMAENGINE: define a dummy filter function for ste_dma40\n ...\n" }, { "commit": "87acf5ad87b275660e2508e6935b570a20b6a073", "tree": "c0a5d543289a953961171bcb8294e09eb912af0f", "parents": [ "abbce906d05ec37289cd0c3b4e35b2db26eab19b" ], "author": { "name": "Dzianis Kahanovich", "email": "mahatma@bspu.unibel.by", "time": "Wed Oct 27 20:33:05 2010 -0600" }, "committer": { "name": "Rusty Russell", "email": "rusty@rustcorp.com.au", "time": "Wed Oct 27 20:33:05 2010 +1030" }, "message": "NULL-terminate all pci_device_id tables\n\nNULL-terminating pci_device_id in pch_dma.c and scx200_acb.c\nfor appying MODULE_DEVICE_TABLE (to publish modalias-es).\n\nSigned-off-by: Dzianis Kahanovich \u003cmahatma@eu.by\u003e\nSigned-off-by: Rusty Russell \u003crusty@rustcorp.com.au\u003e\n" }, { "commit": "964dc256bb91e990277010a3f6dc66daa130be8b", "tree": "9908fa6c07c9feefa9635f1b66c9e2365aeea83e", "parents": [ "8267f16e8b67ea272f37f7072933dc0d3839693d" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@stericsson.com", "time": "Thu Oct 21 21:04:38 2010 +0200" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Oct 22 11:08:38 2010 -0700" }, "message": "DMAENGINE: move COH901318 to arch_initcall\n\nAfter moving the PL022 driver to subsys_initcall() due to the need\nof having stuff like regulators on the other end of the SPI link,\nI noticed that the COH901318 DMA engine will get probed before\nthe DMA engine, so move it to an arch_initcall().\n\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "8267f16e8b67ea272f37f7072933dc0d3839693d", "tree": "672a25b5bb2db8c1a440d0221d1069231071f6aa", "parents": [ "42e55736f7efd7658f8826a5f441c3ccb962db74" ], "author": { "name": "Sascha Hauer", "email": "s.hauer@pengutronix.de", "time": "Wed Oct 20 08:37:19 2010 +0200" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Oct 22 11:08:27 2010 -0700" }, "message": "dma: imx-dma: fix signedness bug\n\nmxdmac-\u003echannel was unsigned, so check (imxdmac-\u003echannel \u003c 0) for\nfailed imx_dma_request_by_prio() made no sence. Explicitly check\nsigned values.\nAlso, fix uninitialzed use of ret.\n\nSigned-off-by: Vasiliy Kulikov \u003csegooon@gmail.com\u003e\nSigned-off-by: Sascha Hauer \u003cs.hauer@pengutronix.de\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "092e0e7e520a1fca03e13c9f2d157432a8657ff2", "tree": "451897252c4c08c4b5a8ef535da156f1e817e80b", "parents": [ "79f14b7c56d3b3ba58f8b43d1f70b9b71477a800", "776c163b1b93c8dfa5edba885bc2bfbc2d228a5f" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Oct 22 10:52:56 2010 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Oct 22 10:52:56 2010 -0700" }, "message": "Merge branch \u0027llseek\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/bkl\n\n* \u0027llseek\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/bkl:\n vfs: make no_llseek the default\n vfs: don\u0027t use BKL in default_llseek\n llseek: automatically add .llseek fop\n libfs: use generic_file_llseek for simple_attr\n mac80211: disallow seeks in minstrel debug code\n lirc: make chardev nonseekable\n viotape: use noop_llseek\n raw: use explicit llseek file operations\n ibmasmfs: use generic_file_llseek\n spufs: use llseek in all file operations\n arm/omap: use generic_file_llseek in iommu_debug\n lkdtm: use generic_file_llseek in debugfs\n net/wireless: use generic_file_llseek in debugfs\n drm: use noop_llseek\n" }, { "commit": "42e55736f7efd7658f8826a5f441c3ccb962db74", "tree": "150a54e47af512c72a1ec105d31fcdfa9957a673", "parents": [ "9cb047d4d19fc15791a64d900d483405eae6200d", "5c3720935813c45c2893fdb53eb6f73f1aee93c7" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Oct 19 15:34:26 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Oct 19 15:34:26 2010 -0700" }, "message": "Merge branch \u0027dma40\u0027 into dmaengine\n" }, { "commit": "9cb047d4d19fc15791a64d900d483405eae6200d", "tree": "6a3655d0c4ddfe76c8f0bbdebe070d40238d49dc", "parents": [ "5fc6d897fde352bad5db5767e7260741a8cdd9e9" ], "author": { "name": "Nicolas Kaiser", "email": "nikai@nikai.net", "time": "Fri Oct 08 00:48:01 2010 +0200" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Oct 19 15:20:11 2010 -0700" }, "message": "dma/timberdale: simplify conditional\n\nSimplify: ((a \u0026\u0026 b) || (!a \u0026\u0026 !b)) \u003d\u003e (a \u003d\u003d b)\n\nSigned-off-by: Nicolas Kaiser \u003cnikai@nikai.net\u003e\nAcked-by: Jack Stone \u003cjwjstone@fastmail.fm\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "51f5d744ed07a6b82e5cbbeeabd73605d62dcfc9", "tree": "c9e0784f10734280277c3ab96f99917c7431432e", "parents": [ "4a6aed3c4eb69702335ed3689132d07eabaaf86d" ], "author": { "name": "Rabin Vincent", "email": "rabin.vincent@stericsson.com", "time": "Tue Oct 12 13:00:54 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Oct 19 15:17:07 2010 -0700" }, "message": "ste_dma40: remove enum for endianess\n\nA bool will suffice. The default is little endian.\n\nAcked-by: Jonas Aaberg \u003cjonas.aberg@stericsson.com\u003e\nSigned-off-by: Rabin Vincent \u003crabin.vincent@stericsson.com\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "20a5b6d043a9a12d01cec76993ba3658a6d36ba7", "tree": "6a2d943828027a758f6c26c97dc10a6975084b02", "parents": [ "38bdbf020ad7ae1bca564a7db238cdf8b2f462a8" ], "author": { "name": "Rabin Vincent", "email": "rabin.vincent@stericsson.com", "time": "Tue Oct 12 13:00:52 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Oct 19 15:17:07 2010 -0700" }, "message": "ste_dma40: move mode_opt to separate config\n\nDefaults are \"basic mode\" for physical channels, and \"logical source\nlogical destination\" for logical channels.\n\nAcked-by: Jonas Aaberg \u003cjonas.aberg@stericsson.com\u003e\nSigned-off-by: Rabin Vincent \u003crabin.vincent@stericsson.com\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "38bdbf020ad7ae1bca564a7db238cdf8b2f462a8", "tree": "ee8e859322c752d4db84670fc55c707cdc59ce82", "parents": [ "730c1871680774ea0700debc2981c7a53f51d92e" ], "author": { "name": "Rabin Vincent", "email": "rabin.vincent@stericsson.com", "time": "Tue Oct 12 13:00:51 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Oct 19 15:17:07 2010 -0700" }, "message": "ste_dma40: move channel mode to a separate field\n\nAnd keep it logical by default.\n\nAcked-by: Jonas Aaberg \u003cjonas.aberg@stericsson.com\u003e\nSigned-off-by: Rabin Vincent \u003crabin.vincent@stericsson.com\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "730c1871680774ea0700debc2981c7a53f51d92e", "tree": "0d3db14d2e241d060c749c183ffa124da4f946fc", "parents": [ "ce2ca1252ba8688a4997b4104793540f4c28c0d8" ], "author": { "name": "Rabin Vincent", "email": "rabin.vincent@stericsson.com", "time": "Tue Oct 12 13:00:50 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Oct 19 15:17:06 2010 -0700" }, "message": "ste_dma40: move priority to separate field\n\nAnd keep it low priority by default.\n\nAcked-by: Jonas Aaberg \u003cjonas.aberg@stericsson.com\u003e\nSigned-off-by: Rabin Vincent \u003crabin.vincent@stericsson.com\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "ce2ca1252ba8688a4997b4104793540f4c28c0d8", "tree": "137b6098794fbb4270cc9c65936c89ff70ec7661", "parents": [ "9646b7985e906e5fcea9375f016b4519c8318c21" ], "author": { "name": "Rabin Vincent", "email": "rabin.vincent@stericsson.com", "time": "Tue Oct 12 13:00:49 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Oct 19 15:17:06 2010 -0700" }, "message": "ste_dma40: add variable to indicate valid dma_cfg\n\nSince we want to reduce the amount of required channel\nconfiguration and remove channel_type, don\u0027t depend on it\nto indicate whether the configuration is valid.\n\nAcked-by: Jonas Aaberg \u003cjonas.aberg@stericsson.com\u003e\nSigned-off-by: Rabin Vincent \u003crabin.vincent@stericsson.com\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "6038f373a3dc1f1c26496e60b6c40b164716f07e", "tree": "a0d3bbd026eea41b9fc36b8c722cbaf56cd9f825", "parents": [ "1ec5584e3edf9c4bf2c88c846534d19cf986ba11" ], "author": { "name": "Arnd Bergmann", "email": "arnd@arndb.de", "time": "Sun Aug 15 18:52:59 2010 +0200" }, "committer": { "name": "Arnd Bergmann", "email": "arnd@arndb.de", "time": "Fri Oct 15 15:53:27 2010 +0200" }, "message": "llseek: automatically add .llseek fop\n\nAll file_operations should get a .llseek operation so we can make\nnonseekable_open the default for future file operations without a\n.llseek pointer.\n\nThe three cases that we can automatically detect are no_llseek, seq_lseek\nand default_llseek. For cases where we can we can automatically prove that\nthe file offset is always ignored, we use noop_llseek, which maintains\nthe current behavior of not returning an error from a seek.\n\nNew drivers should normally not use noop_llseek but instead use no_llseek\nand call nonseekable_open at open time. Existing drivers can be converted\nto do the same when the maintainer knows for certain that no user code\nrelies on calling seek on the device file.\n\nThe generated code is often incorrectly indented and right now contains\ncomments that clarify for each added line why a specific variant was\nchosen. In the version that gets submitted upstream, the comments will\nbe gone and I will manually fix the indentation, because there does not\nseem to be a way to do that using coccinelle.\n\nSome amount of new code is currently sitting in linux-next that should get\nthe same modifications, which I will do at the end of the merge window.\n\nMany thanks to Julia Lawall for helping me learn to write a semantic\npatch that does all this.\n\n\u003d\u003d\u003d\u003d\u003d begin semantic patch \u003d\u003d\u003d\u003d\u003d\n// This adds an llseek\u003d method to all file operations,\n// as a preparation for making no_llseek the default.\n//\n// The rules are\n// - use no_llseek explicitly if we do nonseekable_open\n// - use seq_lseek for sequential files\n// - use default_llseek if we know we access f_pos\n// - use noop_llseek if we know we don\u0027t access f_pos,\n// but we still want to allow users to call lseek\n//\n@ open1 exists @\nidentifier nested_open;\n@@\nnested_open(...)\n{\n\u003c+...\nnonseekable_open(...)\n...+\u003e\n}\n\n@ open exists@\nidentifier open_f;\nidentifier i, f;\nidentifier open1.nested_open;\n@@\nint open_f(struct inode *i, struct file *f)\n{\n\u003c+...\n(\nnonseekable_open(...)\n|\nnested_open(...)\n)\n...+\u003e\n}\n\n@ read disable optional_qualifier exists @\nidentifier read_f;\nidentifier f, p, s, off;\ntype ssize_t, size_t, loff_t;\nexpression E;\nidentifier func;\n@@\nssize_t read_f(struct file *f, char *p, size_t s, loff_t *off)\n{\n\u003c+...\n(\n *off \u003d E\n|\n *off +\u003d E\n|\n func(..., off, ...)\n|\n E \u003d *off\n)\n...+\u003e\n}\n\n@ read_no_fpos disable optional_qualifier exists @\nidentifier read_f;\nidentifier f, p, s, off;\ntype ssize_t, size_t, loff_t;\n@@\nssize_t read_f(struct file *f, char *p, size_t s, loff_t *off)\n{\n... when !\u003d off\n}\n\n@ write @\nidentifier write_f;\nidentifier f, p, s, off;\ntype ssize_t, size_t, loff_t;\nexpression E;\nidentifier func;\n@@\nssize_t write_f(struct file *f, const char *p, size_t s, loff_t *off)\n{\n\u003c+...\n(\n *off \u003d E\n|\n *off +\u003d E\n|\n func(..., off, ...)\n|\n E \u003d *off\n)\n...+\u003e\n}\n\n@ write_no_fpos @\nidentifier write_f;\nidentifier f, p, s, off;\ntype ssize_t, size_t, loff_t;\n@@\nssize_t write_f(struct file *f, const char *p, size_t s, loff_t *off)\n{\n... when !\u003d off\n}\n\n@ fops0 @\nidentifier fops;\n@@\nstruct file_operations fops \u003d {\n ...\n};\n\n@ has_llseek depends on fops0 @\nidentifier fops0.fops;\nidentifier llseek_f;\n@@\nstruct file_operations fops \u003d {\n...\n .llseek \u003d llseek_f,\n...\n};\n\n@ has_read depends on fops0 @\nidentifier fops0.fops;\nidentifier read_f;\n@@\nstruct file_operations fops \u003d {\n...\n .read \u003d read_f,\n...\n};\n\n@ has_write depends on fops0 @\nidentifier fops0.fops;\nidentifier write_f;\n@@\nstruct file_operations fops \u003d {\n...\n .write \u003d write_f,\n...\n};\n\n@ has_open depends on fops0 @\nidentifier fops0.fops;\nidentifier open_f;\n@@\nstruct file_operations fops \u003d {\n...\n .open \u003d open_f,\n...\n};\n\n// use no_llseek if we call nonseekable_open\n////////////////////////////////////////////\n@ nonseekable1 depends on !has_llseek \u0026\u0026 has_open @\nidentifier fops0.fops;\nidentifier nso ~\u003d \"nonseekable_open\";\n@@\nstruct file_operations fops \u003d {\n... .open \u003d nso, ...\n+.llseek \u003d no_llseek, /* nonseekable */\n};\n\n@ nonseekable2 depends on !has_llseek @\nidentifier fops0.fops;\nidentifier open.open_f;\n@@\nstruct file_operations fops \u003d {\n... .open \u003d open_f, ...\n+.llseek \u003d no_llseek, /* open uses nonseekable */\n};\n\n// use seq_lseek for sequential files\n/////////////////////////////////////\n@ seq depends on !has_llseek @\nidentifier fops0.fops;\nidentifier sr ~\u003d \"seq_read\";\n@@\nstruct file_operations fops \u003d {\n... .read \u003d sr, ...\n+.llseek \u003d seq_lseek, /* we have seq_read */\n};\n\n// use default_llseek if there is a readdir\n///////////////////////////////////////////\n@ fops1 depends on !has_llseek \u0026\u0026 !nonseekable1 \u0026\u0026 !nonseekable2 \u0026\u0026 !seq @\nidentifier fops0.fops;\nidentifier readdir_e;\n@@\n// any other fop is used that changes pos\nstruct file_operations fops \u003d {\n... .readdir \u003d readdir_e, ...\n+.llseek \u003d default_llseek, /* readdir is present */\n};\n\n// use default_llseek if at least one of read/write touches f_pos\n/////////////////////////////////////////////////////////////////\n@ fops2 depends on !fops1 \u0026\u0026 !has_llseek \u0026\u0026 !nonseekable1 \u0026\u0026 !nonseekable2 \u0026\u0026 !seq @\nidentifier fops0.fops;\nidentifier read.read_f;\n@@\n// read fops use offset\nstruct file_operations fops \u003d {\n... .read \u003d read_f, ...\n+.llseek \u003d default_llseek, /* read accesses f_pos */\n};\n\n@ fops3 depends on !fops1 \u0026\u0026 !fops2 \u0026\u0026 !has_llseek \u0026\u0026 !nonseekable1 \u0026\u0026 !nonseekable2 \u0026\u0026 !seq @\nidentifier fops0.fops;\nidentifier write.write_f;\n@@\n// write fops use offset\nstruct file_operations fops \u003d {\n... .write \u003d write_f, ...\n+\t.llseek \u003d default_llseek, /* write accesses f_pos */\n};\n\n// Use noop_llseek if neither read nor write accesses f_pos\n///////////////////////////////////////////////////////////\n\n@ fops4 depends on !fops1 \u0026\u0026 !fops2 \u0026\u0026 !fops3 \u0026\u0026 !has_llseek \u0026\u0026 !nonseekable1 \u0026\u0026 !nonseekable2 \u0026\u0026 !seq @\nidentifier fops0.fops;\nidentifier read_no_fpos.read_f;\nidentifier write_no_fpos.write_f;\n@@\n// write fops use offset\nstruct file_operations fops \u003d {\n...\n .write \u003d write_f,\n .read \u003d read_f,\n...\n+.llseek \u003d noop_llseek, /* read and write both use no f_pos */\n};\n\n@ depends on has_write \u0026\u0026 !has_read \u0026\u0026 !fops1 \u0026\u0026 !fops2 \u0026\u0026 !has_llseek \u0026\u0026 !nonseekable1 \u0026\u0026 !nonseekable2 \u0026\u0026 !seq @\nidentifier fops0.fops;\nidentifier write_no_fpos.write_f;\n@@\nstruct file_operations fops \u003d {\n... .write \u003d write_f, ...\n+.llseek \u003d noop_llseek, /* write uses no f_pos */\n};\n\n@ depends on has_read \u0026\u0026 !has_write \u0026\u0026 !fops1 \u0026\u0026 !fops2 \u0026\u0026 !has_llseek \u0026\u0026 !nonseekable1 \u0026\u0026 !nonseekable2 \u0026\u0026 !seq @\nidentifier fops0.fops;\nidentifier read_no_fpos.read_f;\n@@\nstruct file_operations fops \u003d {\n... .read \u003d read_f, ...\n+.llseek \u003d noop_llseek, /* read uses no f_pos */\n};\n\n@ depends on !has_read \u0026\u0026 !has_write \u0026\u0026 !fops1 \u0026\u0026 !fops2 \u0026\u0026 !has_llseek \u0026\u0026 !nonseekable1 \u0026\u0026 !nonseekable2 \u0026\u0026 !seq @\nidentifier fops0.fops;\n@@\nstruct file_operations fops \u003d {\n...\n+.llseek \u003d noop_llseek, /* no read or write fn */\n};\n\u003d\u003d\u003d\u003d\u003d End semantic patch \u003d\u003d\u003d\u003d\u003d\n\nSigned-off-by: Arnd Bergmann \u003carnd@arndb.de\u003e\nCc: Julia Lawall \u003cjulia@diku.dk\u003e\nCc: Christoph Hellwig \u003chch@infradead.org\u003e\n" }, { "commit": "c50a898fd4e736623ee175920db056194e0bb483", "tree": "271750360d57da1d982686d8435b8eb3bf3086e4", "parents": [ "cc60f8878eab892c03d06b10f389232b9b66bd83" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Oct 13 15:43:10 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Oct 13 15:43:10 2010 -0700" }, "message": "ioat2: fix performance regression\n\nCommit 0793448 \"DMAENGINE: generic channel status v2\" changed the interface for\nhow dma channel progress is retrieved. It inadvertently exported an internal\nhelper function ioat_tx_status() instead of ioat_dma_tx_status(). The latter\npolls the hardware to get the latest completion state, while the helper just\nevaluates the current state without touching hardware. The effect is that we\nend up waiting for completion timeouts or descriptor allocation errors before\nthe completion state is updated.\n\niperf (before fix):\n[SUM] 0.0-41.3 sec 364 MBytes 73.9 Mbits/sec\n\niperf (after fix):\n[SUM] 0.0- 4.5 sec 499 MBytes 940 Mbits/sec\n\nThis is a regression starting with 2.6.35.\n\nCc: \u003cstable@kernel.org\u003e\nCc: Dave Jiang \u003cdave.jiang@intel.com\u003e\nCc: Jesse Brandeburg \u003cjesse.brandeburg@intel.com\u003e\nCc: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nCc: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nReported-by: Richard Scobie \u003crichard@sauce.co.nz\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "5fc6d897fde352bad5db5767e7260741a8cdd9e9", "tree": "cb918dd33b8288aadead08b04b9f308f9d8bcbd1", "parents": [ "400fb7f6a0cfe13025cb0296fdb4737da7025a8a" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Oct 07 16:44:50 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Oct 07 17:08:32 2010 -0700" }, "message": "async_tx: make async_tx channel switching opt-in\n\nThe majority of drivers in drivers/dma/ will never establish cross\nchannel operation chains and do not need the extra overhead in struct\ndma_async_tx_descriptor. Make channel switching opt-in by default.\n\nCc: Anatolij Gustschin \u003cagust@denx.de\u003e\nCc: Ira Snyder \u003ciws@ovro.caltech.edu\u003e\nCc: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nCc: Saeed Bishara \u003csaeed@marvell.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "6391987d6f8ced7d0fafaa1440dcc57bb4b34d8f", "tree": "027a3989fceb18c45cf6d435a87b9879e38b8216", "parents": [ "9646b7985e906e5fcea9375f016b4519c8318c21", "e8689e63d4d2046079f2db9d494ac05c6885ac0c", "0d688662aab9d80078be82aa5aea561346643298", "1f1846c6ceed07c03ef036a27864befe0f773997", "20dd63900d238e17b122fe0c7376ff090867f528" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Oct 07 15:19:01 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Oct 07 15:19:01 2010 -0700" }, "message": "Merge branches \u0027dma40\u0027, \u0027pl08x\u0027, \u0027fsldma\u0027, \u0027imx\u0027 and \u0027intel-mid\u0027 into dmaengine\n" }, { "commit": "1f1846c6ceed07c03ef036a27864befe0f773997", "tree": "107e5cabb0e33c041283a2cebd46482381878adb", "parents": [ "1ec1e82f2510e2bdcb6268ed74aa79e1a7bc9594" ], "author": { "name": "Sascha Hauer", "email": "s.hauer@pengutronix.de", "time": "Wed Oct 06 10:25:55 2010 +0200" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Oct 07 15:18:03 2010 -0700" }, "message": "dmaengine: Add Freescale i.MX1/21/27 DMA driver\n\nThis driver is currently implemented as a user to the old i.MX\nDMA API. This allows us to convert each user of the old API to\nthe dmaengine API one by one. Once this is done the old DMA\ndriver can be merged into the i.MX dmaengine driver.\n\nV2: remove some debug leftovers and unused variables\n\nSigned-off-by: Sascha Hauer \u003cs.hauer@pengutronix.de\u003e\nAcked-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "20dd63900d238e17b122fe0c7376ff090867f528", "tree": "8f25adbbb5d49ca428df2596d1e2e24e8e40e428", "parents": [ "8b6492231d2a92352a6371eebd622e3bc824a663" ], "author": { "name": "Koul, Vinod", "email": "vinod.koul@intel.com", "time": "Mon Oct 04 10:38:43 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Oct 07 15:03:44 2010 -0700" }, "message": "intel_mid_dma: change the slave interface\n\nIn 2.6.36 kernel, dma slave control command was introduced,\nthis patch changes the intel-mid-dma driver to this\nnew kernel slave interface\n\nSigned-off-by: Vinod Koul \u003cvinod.koul@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "8b6492231d2a92352a6371eebd622e3bc824a663", "tree": "875a69042151b5c317a9dc4b89a63bbbfbd5c834", "parents": [ "576e3c394a6c427c9a1378ec88ef7eb97e731992" ], "author": { "name": "Koul, Vinod", "email": "vinod.koul@intel.com", "time": "Mon Oct 04 10:38:25 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Oct 07 15:03:43 2010 -0700" }, "message": "intel_mid_dma: fix the WARN_ONs\n\nMoved the WARN_ON to BUG_ON, as WARN_ON if hit,\ncan cause null pointer derefrences\n\nSigned-off-by: Vinod Koul \u003cvinod.koul@intel.com\u003e\nSigned-off-by: Alan Cox \u003calan@linux.intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "576e3c394a6c427c9a1378ec88ef7eb97e731992", "tree": "55cfcf13ac594a63d1f8056bca08c6db66edcb3e", "parents": [ "03b96dca010145f3896abcd443b7fddb9813a0e6" ], "author": { "name": "Ramesh Babu K V", "email": "ramesh.b.k.v@intel.com", "time": "Mon Oct 04 10:37:53 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Oct 07 15:03:43 2010 -0700" }, "message": "intel_mid_dma: Add sg list support to DMA driver\n\nFor a very high speed DMA various periphral devices need\nscatter-gather list support. The DMA hardware support link list items.\nThis list can be circular also (adding new flag DMA_PREP_CIRCULAR_LIST)\nRight now this flag is in driver header and should be moved to\ndmaengine header file eventually\n\nSigned-off-by: Ramesh Babu K V \u003cramesh.b.k.v@intel.com\u003e\nSigned-off-by: Vinod Koul \u003cvinod.koul@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "03b96dca010145f3896abcd443b7fddb9813a0e6", "tree": "53fe9bffa5a23b1b4e49f953a9d8eb23f4b79935", "parents": [ "b306df5e925bb584b2157f11f97c5eb20a13de4d" ], "author": { "name": "Yong Wang", "email": "yong.y.wang@intel.com", "time": "Mon Oct 04 10:37:27 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Oct 07 15:03:43 2010 -0700" }, "message": "intel_mid_dma: Allow DMAC2 to share interrupt\n\nAllow DMAC2 to share interrupt since exclusive interrupt line\nfor mrst DMAC2 is not provided on other platforms.\n\nSigned-off-by: Yong Wang \u003cyong.y.wang@intel.com\u003e\nSigned-off-by: Vinod Koul \u003cvinod.koul@intel.com\u003e\nSigned-off-by: Alan Cox \u003calan@linux.intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "b306df5e925bb584b2157f11f97c5eb20a13de4d", "tree": "10cf5276a242c69a57c73f53499ab049827ed0a1", "parents": [ "53a61badf47e674fb43d73cd22f0f8065098ddf6" ], "author": { "name": "Yong Wang", "email": "yong.y.wang@intel.com", "time": "Mon Oct 04 10:37:02 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Oct 07 15:03:43 2010 -0700" }, "message": "intel_mid_dma: Allow IRQ sharing\n\nintel_mid_dma driver allows interrupt sharing. Thus it needs\nto check whether IRQ source is the DMA controller and return\nthe appropriate IRQ return.\n\nSigned-off-by: Yong Wang \u003cyong.y.wang@intel.com\u003e\nSigned-off-by: Vinod Koul \u003cvinod.koul@intel.com\u003e\nSigned-off-by: Alan Cox \u003calan@linux.intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "53a61badf47e674fb43d73cd22f0f8065098ddf6", "tree": "abf0b87c397d9129f22bd34bbfc8d9f9cb139cab", "parents": [ "cc60f8878eab892c03d06b10f389232b9b66bd83" ], "author": { "name": "Koul, Vinod", "email": "vinod.koul@intel.com", "time": "Mon Oct 04 10:42:40 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Oct 07 15:03:42 2010 -0700" }, "message": "intel_mid_dma: Add runtime PM support\n\nThis patch adds runtime PM support in this dma driver\nfor 4 PCI Controllers\nWhenever the driver is idle (no channels grabbed), it\ncan go to low power state\nIt also adds the PCI suspend and resume support\n\nSigned-off-by: Vinod Koul \u003cvinod.koul@intel.com\u003e\nSigned-off-by: Alan Cox \u003calan@linux.intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "661385f9c34e15c2f2c57b80e8cb2c7b910fdbd3", "tree": "be7d9196566449473cc0b49138839b6ec2dd66a7", "parents": [ "a59670a40b4dd497630f9442feb259dde601e469" ], "author": { "name": "Per Forlin", "email": "per.friden@stericsson.com", "time": "Wed Oct 06 09:05:28 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Oct 07 14:56:36 2010 -0700" }, "message": "DMAENGINE: Remove stedma40_set_psize and pre_transfer hook in ste_dma40\n\nRemove obsolete pre_transfer hook in stedma40_chan_cfg. The\nintent of this hook is merely to handle burst size\ncompensation for ux500 variant MMCI. Remove obsolete stedma40_set_psize\nsince it is only called from pre_transfer. DMAEngine device_control\nreplaces the functionality of stedma40_set_psize.\n\nSigned-off-by: Per Forlin \u003cper.forlin@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "a59670a40b4dd497630f9442feb259dde601e469", "tree": "2ed346ae4dbd94e271ffeac5badba2c1723d8775", "parents": [ "819504f4861a5bc1e25c82409956388bb79fb635" ], "author": { "name": "Per Forlin", "email": "per.friden@stericsson.com", "time": "Wed Oct 06 09:05:27 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Oct 07 14:56:35 2010 -0700" }, "message": "DMAENGINE: Set burst size for phy and log chans in ste_dma40 dev_control\n\nSet burst for physical or logical channels respectively.\nConvert the values in dma_cfg to dma reg bits\nfor physical or logical channels.\n\nSigned-off-by: Per Forlin \u003cper.forlin@stericsson.com\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "819504f4861a5bc1e25c82409956388bb79fb635", "tree": "6adfb3ab04da0dfa87d677502fa902c93991b2b5", "parents": [ "a2c15fa4c122558472f8041515072218c8652c7e" ], "author": { "name": "Rabin Vincent", "email": "rabin.vincent@stericsson.com", "time": "Wed Oct 06 08:20:38 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Oct 07 14:54:55 2010 -0700" }, "message": "DMAENGINE: ste_dma40: fix resource leaks in error paths.\n\nFix some leaks of allocated descriptors in error paths.\n\nAcked-by: Jonas Aaberg \u003cjonas.aberg@stericsson.com\u003e\nSigned-off-by: Rabin Vincent \u003crabin.vincent@stericsson.com\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "a2c15fa4c122558472f8041515072218c8652c7e", "tree": "f4758cff216bd64a3ddff6e73d40cf2ffc8068c9", "parents": [ "c6134c967c5b8b5986371de335fa4ec39de268bc" ], "author": { "name": "Rabin Vincent", "email": "rabin.vincent@stericsson.com", "time": "Wed Oct 06 08:20:37 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Oct 07 14:54:55 2010 -0700" }, "message": "DMAENGINE: ste_dma40: fix desc_get\n\nFix desc_get to alloc a descriptor from the cache if the ones in the\nlist are waiting for the ack. Also, memzero the descriptor when\nallocated from the list to ensure all fields are cleared.\n\nAcked-by: Jonas Aaberg \u003cjonas.aberg@stericsson.com\u003e\nSigned-off-by: Rabin Vincent \u003crabin.vincent@stericsson.com\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "c6134c967c5b8b5986371de335fa4ec39de268bc", "tree": "d0ad380424a2fc37785a46118434b2b058cbda00", "parents": [ "f57b407cfd5fbd70251e9fa0ea7aa083ac06d25c" ], "author": { "name": "Rabin Vincent", "email": "rabin.vincent@stericsson.com", "time": "Wed Oct 06 08:20:36 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Oct 07 14:54:55 2010 -0700" }, "message": "DMAENGINE: ste_dma40: fix clk_get failure path\n\nclk_get returns an ERR_PTR.\n\nAcked-by: Jonas Aaberg \u003cjonas.aberg@stericsson.com\u003e\nSigned-off-by: Rabin Vincent \u003crabin.vincent@stericsson.com\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "f57b407cfd5fbd70251e9fa0ea7aa083ac06d25c", "tree": "061a24030aa22991f3510b1823171db06ce97b13", "parents": [ "3c0f24019f69c5199996ed9c76d05c92c6186ba8" ], "author": { "name": "Rabin Vincent", "email": "rabin.vincent@stericsson.com", "time": "Wed Oct 06 08:20:35 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Oct 07 14:54:54 2010 -0700" }, "message": "DMAENGINE: ste_dma40: fix disabled channels list\n\nThe value in the array, not the index, specifies the channel to be\ndisabled.\n\nAcked-by: Jonas Aaberg \u003cjonas.aberg@stericsson.com\u003e\nSigned-off-by: Rabin Vincent \u003crabin.vincent@stericsson.com\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "0d688662aab9d80078be82aa5aea561346643298", "tree": "61ce15bc08f757db7d94a37ab2100973c7e0e06c", "parents": [ "968f19ae802fdc6b6b6b5af6fe79cf23d281be0f" ], "author": { "name": "Ira Snyder", "email": "iws@ovro.caltech.edu", "time": "Thu Sep 30 11:46:47 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Oct 07 14:41:41 2010 -0700" }, "message": "ste_dma40: implement support for scatterlist to scatterlist copy\n\nNow that the DMAEngine API has support for scatterlist to scatterlist\ncopy, implement support for the STE DMA40 DMA controller.\n\nCc: Linus Walleij \u003clinus.ml.walleij@gmail.com\u003e\nAcked-by: Per Fridén \u003cper.friden@stericsson.com\u003e\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "968f19ae802fdc6b6b6b5af6fe79cf23d281be0f", "tree": "122f3912ed717627b0e5bac8c72f42ef2eb0cb6e", "parents": [ "c14330417ef2050f4bf38ac20e125785fea14351" ], "author": { "name": "Ira Snyder", "email": "iws@ovro.caltech.edu", "time": "Thu Sep 30 11:46:46 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Oct 07 14:41:41 2010 -0700" }, "message": "fsldma: improved DMA_SLAVE support\n\nNow that the generic DMAEngine API has support for scatterlist to\nscatterlist copying, the device_prep_slave_sg() portion of the\nDMA_SLAVE API is no longer necessary and has been removed.\n\nHowever, the device_control() portion of the DMA_SLAVE API is still\nuseful to control device specific parameters, such as externally\ncontrolled DMA transfers and maximum burst length.\n\nA special dma_ctrl_cmd has been added to enable externally controlled\nDMA transfers. This is currently specific to the Freescale DMA\ncontroller, but can easily be made generic when another user is found.\n\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "c14330417ef2050f4bf38ac20e125785fea14351", "tree": "0b8352bd377d873feff3ec684c0c027f89aa7b14", "parents": [ "a86ee03ce6f279ebe581a7a8c0c4393eaeb789ee" ], "author": { "name": "Ira Snyder", "email": "iws@ovro.caltech.edu", "time": "Thu Sep 30 11:46:45 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Oct 07 14:41:41 2010 -0700" }, "message": "fsldma: implement support for scatterlist to scatterlist copy\n\nNow that the DMAEngine API has support for scatterlist to scatterlist\ncopy, implement support for the Freescale DMA controller.\n\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "a86ee03ce6f279ebe581a7a8c0c4393eaeb789ee", "tree": "e662a6492370232e008d405e4ed7bfa4be0aea2e", "parents": [ "cc60f8878eab892c03d06b10f389232b9b66bd83" ], "author": { "name": "Ira Snyder", "email": "iws@ovro.caltech.edu", "time": "Thu Sep 30 11:46:44 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Oct 07 14:41:40 2010 -0700" }, "message": "dma: add support for scatterlist to scatterlist copy\n\nThis adds support for scatterlist to scatterlist DMA transfers. A\nsimilar interface is exposed by the fsldma driver (through the DMA_SLAVE\nAPI) and by the ste_dma40 driver (through an exported function).\n\nThis patch paves the way for making this type of copy operation a part\nof the generic DMAEngine API. Futher patches will add support in\nindividual drivers.\n\nSigned-off-by: Ira W. Snyder \u003ciws@ovro.caltech.edu\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "1ec1e82f2510e2bdcb6268ed74aa79e1a7bc9594", "tree": "f274f0b9ff704416492fe420174e65b9b640eff2", "parents": [ "6e3ecaf0ad49de0bed829d409a164e7107c02993" ], "author": { "name": "Sascha Hauer", "email": "s.hauer@pengutronix.de", "time": "Thu Sep 30 13:56:34 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Oct 05 15:49:26 2010 -0700" }, "message": "dmaengine: Add Freescale i.MX SDMA support\n\nThis patch adds support for the Freescale i.MX SDMA engine.\n\nThe SDMA engine is a scatter/gather DMA engine which is implemented\nas a seperate coprocessor. SDMA needs its own firmware which is\nrequested using the standard request_firmware mechanism. The firmware\nhas different entry points for each peripheral type, so drivers\nhave to pass the peripheral type to the DMA engine which in turn\npicks the correct firmware entry point from a table contained in\nthe firmware image itself.\nThe original Freescale code also supports support for transfering\ndata to the internal SRAM which needs different entry points to\nthe firmware. Support for this is currently not implemented. Also,\nsupport for the ASRC (asymmetric sample rate converter) is skipped.\n\nI took a very simple approach to implement dmaengine support. Only\na single descriptor is statically assigned to a each channel. This\nmeans that transfers can\u0027t be queued up but only a single transfer\nis in progress. This simplifies implementation a lot and is sufficient\nfor the usual device/memory transfers.\n\nSigned-off-by: Sascha Hauer \u003cs.hauer@pengutronix.de\u003e\nReviewed-by: Linus Walleij \u003clinus.ml.walleij@gmail.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "782bc950d84e404422ba21008fd51ee894c8d231", "tree": "c8a10b80bcc571c6de8a19c39b0f447ca61039d6", "parents": [ "b30a3f6257ed2105259b404d419b4964e363928c" ], "author": { "name": "Sascha Hauer", "email": "s.hauer@pengutronix.de", "time": "Thu Sep 30 13:56:32 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Oct 05 15:49:26 2010 -0700" }, "message": "dmaengine: add possibility for cyclic transfers\n\nCyclic transfers are useful for audio where a single buffer divided\nin periods has to be transfered endlessly until stopped. After being\nprepared the transfer is started using the dma_async_descriptor-\u003etx_submit\nfunction. dma_async_descriptor-\u003ecallback is called after each period.\nThe transfer is stopped using the DMA_TERMINATE_ALL callback.\nWhile being used for cyclic transfers the channel cannot be used\nfor other transfer types.\n\nSigned-off-by: Sascha Hauer \u003cs.hauer@pengutronix.de\u003e\nCc: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "e8689e63d4d2046079f2db9d494ac05c6885ac0c", "tree": "29196d65697acc7fd49af9e00f2068413e29b771", "parents": [ "b30a3f6257ed2105259b404d419b4964e363928c" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@stericsson.com", "time": "Tue Sep 28 15:57:37 2010 +0200" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Sep 29 16:13:51 2010 -0700" }, "message": "dmaengine: driver for the ARM PL080/PL081 PrimeCells v5\n\nThis creates a DMAengine driver for the ARM PL080/PL081 PrimeCells\nbased on the implementation earlier submitted by Peter Pearse.\nThis is working like a charm for memcpy and slave DMA to the PL011\nPrimeCell on the PB11MPCore.\n\nThis DMA controller is used in mostly unmodified form in the ARM\nRealView and Versatile platforms, in the ST-Ericsson Nomadik, and\nin the ST SPEAr platform.\n\nIt has been converted to use the header from the Samsung PL080\nderivate instead of its own defintions. The Samsungs have a custom\ndriver in their mach-* folders though, atleast we can share the\nregister definitions.\n\nCc: Peter Pearse \u003cpeter.pearse@arm.com\u003e\nCc: Ben Dooks \u003cben-linux@fluff.org\u003e\nCc: Kukjin Kim \u003ckgene.kim@samsung.com\u003e\nCc: Alessandro Rubini \u003crubini@unipv.it\u003e\nAcked-by: Viresh Kumar \u003cviresh.kumar@st.com\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\n[GFP_KERNEL to GFP_NOWAIT in pl08x_prep_dma_memcpy]\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "cc60f8878eab892c03d06b10f389232b9b66bd83", "tree": "1f2cc0671c1f84c8928c261700f370771d510cbb", "parents": [ "d3f3cf859db17cc5f8156c5bfcd032413e44483b" ], "author": { "name": "Simon Guinot", "email": "sguinot@lacie.com", "time": "Fri Sep 17 23:33:51 2010 +0200" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Sep 23 14:14:22 2010 -0700" }, "message": "dmaengine: fix interrupt clearing for mv_xor\n\nWhen using simultaneously the two DMA channels on a same engine, some\ntransfers are never completed. For example, an endless lock can occur\nwhile writing heavily on a RAID5 array (with async-tx offload support\nenabled).\n\nNote that this issue can also be reproduced by using the DMA test\nclient.\n\nOn a same engine, the interrupt cause register is shared between two\nDMA channels. This patch make sure that the cause bit is only cleared\nfor the requested channel.\n\nSigned-off-by: Simon Guinot \u003csguinot@lacie.com\u003e\nTested-by: Luc Saillard \u003cluc@saillard.org\u003e\nAcked-by: saeed bishara \u003csaeed.bishara@gmail.com\u003e\nCc: \u003cstable@kernel.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "9f9ff20d46c6728b092f34b6a642e1e81ab5e254", "tree": "ecf89d4f01277ce8c747fee02a67c6fb5f217ca3", "parents": [ "b30a3f6257ed2105259b404d419b4964e363928c" ], "author": { "name": "Dan Carpenter", "email": "error27@gmail.com", "time": "Sat Aug 14 11:01:45 2010 +0200" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Sep 22 15:29:17 2010 -0700" }, "message": "dma/shdma: move dereference below the NULL check\n\n\"param\" can be NULL here, so only dereference it after the check.\n\nSigned-off-by: Dan Carpenter \u003cerror27@gmail.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "3ac012af3b1b3a6b373f3a9f19c5362974856c2c", "tree": "6f71960819e88c98a4d61a0f52ad3dc9d9957385", "parents": [ "8f6fd7f50f7059e5725a36885af52e54b9df96b2" ], "author": { "name": "Jonas Aaberg", "email": "jonas.aberg@stericsson.com", "time": "Mon Aug 09 12:09:12 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Sep 22 14:53:47 2010 -0700" }, "message": "DMAENGINE: ste_dma40: don\u0027t pause/resume non-executing channels\n\nThere is no point in pausing what isn\u0027t running.\n\nSigned-off-by: Jonas Aaberg \u003cjonas.aberg@stericsson.com\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "698e4732e7c9cf9f1f3eac2b8cdce8d4fe2b90bd", "tree": "9716c813accd1f8f5f5fe6d4ad389fd64396c26d", "parents": [ "69f93faa57ed6c91b32aae1dcff7282fcb2872f5" ], "author": { "name": "Jonas Aaberg", "email": "jonas.aberg@stericsson.com", "time": "Mon Aug 09 12:08:56 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Sep 22 14:53:46 2010 -0700" }, "message": "DMAENGINE: ste_dma40: rewrote LCLA entries allocation code\n\nLLI allocation is now done on job level instead of channel level.\nPreviously the maximum length of a linked job in hw on a logical\nchannel was 8, since the LLIs where evenly divided. Now only\nexecuting jobs have allocated LLIs which increase the length to\na maximum of 64 links in HW.\n\nSigned-off-by: Jonas Aaberg \u003cjonas.aberg@stericsson.com\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "69f93faa57ed6c91b32aae1dcff7282fcb2872f5", "tree": "44a1e6ce05bae3d15d1cc028f10fc1dc46a2c54c", "parents": [ "9dbfbd35ce16e4f5a4d0d9e3f6e012b136fe80ea" ], "author": { "name": "Jonas Aaberg", "email": "jonas.aberg@stericsson.com", "time": "Mon Aug 09 12:08:49 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Sep 22 14:53:46 2010 -0700" }, "message": "DMAENGINE: ste_dma40: fix possible use of uninitialized variable\n\nSigned-off-by: Jonas Aaberg \u003cjonas.aberg@stericsson.com\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "9dbfbd35ce16e4f5a4d0d9e3f6e012b136fe80ea", "tree": "343750610afe11e4637a450bba74ec6a9106e733", "parents": [ "767a9675c4a68ada55f0f30d629db627bd47f012" ], "author": { "name": "Jonas Aaberg", "email": "jonas.aberg@stericsson.com", "time": "Mon Aug 09 12:08:41 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Sep 22 14:53:46 2010 -0700" }, "message": "DMAENGINE: ste_dma40: corrected is_paused behavior\n\nThe handling of pause detection was slightly incorrect.\n\nSigned-off-by: Jonas Aaberg \u003cjonas.aberg@stericsson.com\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "767a9675c4a68ada55f0f30d629db627bd47f012", "tree": "00cdf68f481bc818962367b6fa3255bd8040843e", "parents": [ "aa182ae2621877e0c111922696c84c538b82ad14" ], "author": { "name": "Jonas Aaberg", "email": "jonas.aberg@stericsson.com", "time": "Mon Aug 09 12:08:34 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Sep 22 14:53:46 2010 -0700" }, "message": "DMAENGINE: ste_dma40: code clean-up\n\nThis patch includes non functional code clean up changes,\nfile header updates and a few magic numbers got defined.\n\nSigned-off-by: Jonas Aaberg \u003cjonas.aberg@stericsson.com\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "aa182ae2621877e0c111922696c84c538b82ad14", "tree": "25a9ad5a841b63c99aae9b80e58da5a9b44498da", "parents": [ "3ae0267fd569c2007235fb80cfe3b4a4c54c8f4b" ], "author": { "name": "Jonas Aaberg", "email": "jonas.aberg@stericsson.com", "time": "Mon Aug 09 12:08:26 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Sep 22 14:53:45 2010 -0700" }, "message": "DMAENGINE: ste_dma40: added support for link jobs in hw\n\nIf a new job is added on a physical channel that already has\na job, the new job is linked in hw to the old job instead of\nqueueing up the jobs.\n\nSigned-off-by: Jonas Aaberg \u003cjonas.aberg@stericsson.com\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "3ae0267fd569c2007235fb80cfe3b4a4c54c8f4b", "tree": "1d300eead20bff1737b3e79c48ee0bd0640ea0dd", "parents": [ "0246e77b4d374bb37aa08c3fcadad20012e85ea0" ], "author": { "name": "Jonas Aaberg", "email": "jonas.aberg@stericsson.com", "time": "Mon Aug 09 12:08:18 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Sep 22 14:53:45 2010 -0700" }, "message": "DMAENGINE: ste_dma40: removed a few magic numbers\n\nMake sure to extract the revision field explicitly and document\nwhat bits are being accessed here without magic numbers.\n\nSigned-off-by: Jonas Aaberg \u003cjonas.aberg@stericsson.com\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "0246e77b4d374bb37aa08c3fcadad20012e85ea0", "tree": "62b59fda3aca474abdec3c2385dc3fd00278ef34", "parents": [ "b55912c66a317d9aaf4749488ca43d510c8a8a87" ], "author": { "name": "Jonas Aaberg", "email": "jonas.aberg@stericsson.com", "time": "Mon Aug 09 12:08:10 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Sep 22 14:53:45 2010 -0700" }, "message": "DMAENGINE: ste_dma40: fix bug related to callback handling\n\nThe callback got called even when it was not supposed to. Also\nremoved some not needed interrupt trigger on/off code.\n\nSigned-off-by: Jonas Aaberg \u003cjonas.aberg@stericsson.com\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "b55912c66a317d9aaf4749488ca43d510c8a8a87", "tree": "ee040835dc1e5e4471bd50f167ee81880a9a9f5e", "parents": [ "1b00348d5d0b3423fe21f499bf30d40a4d1dc594" ], "author": { "name": "Jonas Aaberg", "email": "jonas.aberg@stericsson.com", "time": "Mon Aug 09 12:08:02 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Sep 22 14:53:45 2010 -0700" }, "message": "DMAENGINE: ste_dma40: Code clean-up and removed an unneeded suspend request\n\nThis patch cleans up some code and removes a suspend request that was pointless\nsince the hw was never configured nor running when it was called.\n\nSigned-off-by: Jonas Aaberg \u003cjonas.aberg@stericsson.com\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "1b00348d5d0b3423fe21f499bf30d40a4d1dc594", "tree": "6fb57150aaa04d582b860178572405492a7c3321", "parents": [ "be8cb7dfd92420b12dfd6831c2d638f4f46bdfdf" ], "author": { "name": "Jonas Aaberg", "email": "jonas.aberg@stericsson.com", "time": "Mon Aug 09 12:07:54 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Sep 22 14:53:45 2010 -0700" }, "message": "DMAENGINE: ste_dma40: No need reading, masking and setting a set register\n\nRemoves an unnecessary register read and a few lines of code.\n\nSigned-off-by: Jonas Aaberg \u003cjonas.aberg@stericsson.com\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "be8cb7dfd92420b12dfd6831c2d638f4f46bdfdf", "tree": "2a9fa34d9d37543653f86d523bcbd1b89c0a559a", "parents": [ "0747c7bae5c93377f4ea81b55d6851eaddc677fe" ], "author": { "name": "Jonas Aaberg", "email": "jonas.aberg@stericsson.com", "time": "Mon Aug 09 12:07:44 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Sep 22 14:53:44 2010 -0700" }, "message": "DMAENGINE: ste_dma40: Fix failed to restart logical channel bug\n\nA transfer that runs in the different direction on the same\nchannel will now be resumed when the other is suspend/stopped.\n\nSigned-off-by: Jonas Aaberg \u003cjonas.aberg@stericsson.com\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "0747c7bae5c93377f4ea81b55d6851eaddc677fe", "tree": "a41c0c974e2f15ba35b0e171cdfa1c817d8c9a92", "parents": [ "b30a3f6257ed2105259b404d419b4964e363928c" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@stericsson.com", "time": "Mon Aug 09 12:07:36 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Sep 22 14:53:44 2010 -0700" }, "message": "DMAENGINE: ste_dma40: config checks\n\nAdded various configuration checks.\n\nSigned-off-by: Jonas Aaberg \u003cjonas.aberg@stericsson.com\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "58d4ea65b98f154f3326b038eecda32f90b46ea8", "tree": "636aed413349dece12c08a4bd3d1fea0254976d8", "parents": [ "26f0cf91813bdc8e61595f8ad6660251e2ee9cf6", "fbe0f8348fd6c3d016a3f48756eb729b41a67c22" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Aug 12 09:11:31 2010 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Aug 12 09:11:31 2010 -0700" }, "message": "Merge branch \u0027next-devicetree\u0027 of git://git.secretlab.ca/git/linux-2.6\n\n* \u0027next-devicetree\u0027 of git://git.secretlab.ca/git/linux-2.6:\n mmc_spi: Fix unterminated of_match_table\n of/sparc: fix build regression from of_device changes\n of/device: Replace struct of_device with struct platform_device\n" }, { "commit": "0b019a41553a919965bb02d07d54e3e6c57a796d", "tree": "6e329b4159b440d2aac5200a5c07103fe261c096", "parents": [ "5f6878b0d22f9b93f9698f88c335007e2a3c3bbc", "054d5c9238f3c577ad51195c3ee7803613f322cc" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Aug 10 23:17:52 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Tue Aug 10 23:17:52 2010 +0100" }, "message": "Merge branches \u0027master\u0027 and \u0027devel\u0027 into for-linus\n\nConflicts:\n\tarch/arm/Kconfig\n\tarch/arm/mm/Kconfig\n" }, { "commit": "dcded10f6dce10411b16134ce9cc87bfdf75c13f", "tree": "da6d0face147072c9eadc8a01af4e49958769138", "parents": [ "9e0ba741aabdf129d561e62d207c75146adef5e8", "b0ebeb9c09cb5b84bb2f33927c84c7648845fcec" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Aug 09 21:00:07 2010 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Aug 09 21:00:07 2010 -0700" }, "message": "Merge branch \u0027next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx\n\n* \u0027next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: (30 commits)\n DMAENGINE: at_hdmac: locking fixlet\n DMAENGINE: pch_dma: kill another usage of __raw_{read|write}l\n dma: dmatest: fix potential sign bug\n ioat2: catch and recover from broken vtd configurations v6\n DMAENGINE: add runtime slave control to COH 901 318 v3\n DMAENGINE: add runtime slave config to DMA40 v3\n DMAENGINE: generic slave channel control v3\n dmaengine: Driver for Topcliff PCH DMA controller\n intel_mid: Add Mrst \u0026 Mfld DMA Drivers\n drivers/dma: Eliminate a NULL pointer dereference\n dma/timb_dma: compile warning on 32 bit\n DMAENGINE: ste_dma40: support older silicon\n DMAENGINE: ste_dma40: support disabling physical channels\n DMAENGINE: ste_dma40: no disabled phy channels on ux500\n DMAENGINE: ste_dma40: fix suspend bug\n DMAENGINE: ste_dma40: add DB8500 memcpy channels\n DMAENGINE: ste_dma40: no flow control on memcpy\n DMAENGINE: ste_dma40: arch updates for LCLA and LCPA\n DMAENGINE: ste_dma40: allocate LCLA dynamically\n DMAENGINE: ste_dma40: no premature stop\n ...\n\nFix up trivial conflicts in arch/arm/mach-ux500/devices-db8500.c\n" }, { "commit": "500b9fc922cbec572f4fd1436533bfaed5011262", "tree": "aac4b7de0871e66740aeaf3510f7a59280026592", "parents": [ "f165eb77f49cb6f6e86e2f2f09183904b2965d19", "beccb12f6fbcc73339f127ff1f00638f076c933f" ], "author": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Aug 06 18:13:19 2010 +0100" }, "committer": { "name": "Russell King", "email": "rmk+kernel@arm.linux.org.uk", "time": "Fri Aug 06 18:13:19 2010 +0100" }, "message": "Merge master.kernel.org:/pub/scm/linux/kernel/git/lethal/genesis-2.6 into devel-stable\n\nConflicts:\n\tdrivers/net/irda/sh_irda.c\n" }, { "commit": "2dc11581376829303b98eadb2de253bee065a56a", "tree": "dbce62559c822cd720d1819a50c488bfecdfa945", "parents": [ "fc1caf6eafb30ea185720e29f7f5eccca61ecd60" ], "author": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Fri Aug 06 09:25:50 2010 -0600" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Fri Aug 06 09:25:50 2010 -0600" }, "message": "of/device: Replace struct of_device with struct platform_device\n\nof_device is just an alias for platform_device, so remove it entirely. Also\nreplace to_of_device() with to_platform_device() and update comment blocks.\n\nThis patch was initially generated from the following semantic patch, and then\nedited by hand to pick up the bits that coccinelle didn\u0027t catch.\n\n@@\n@@\n-struct of_device\n+struct platform_device\n\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\nReviewed-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "b0ebeb9c09cb5b84bb2f33927c84c7648845fcec", "tree": "3ebb434421ef49abe2bda85840db2834391fcbba", "parents": [ "61cd2203769a2bf35d41f8682f6ef865fe2d23ff" ], "author": { "name": "Yong Wang", "email": "yong.y.wang@linux.intel.com", "time": "Thu Aug 05 10:40:08 2010 +0800" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Aug 04 22:09:17 2010 -0700" }, "message": "DMAENGINE: at_hdmac: locking fixlet\n\natc_chain_complete shall be called with atchan-\u003elock held\nand bh disabled.\n\nSigned-off-by: Yong Wang \u003cyong.y.wang@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "61cd2203769a2bf35d41f8682f6ef865fe2d23ff", "tree": "5d2e886f7f9b20098c8ffee4fbd749ddfb09a530", "parents": [ "b9033e682e86f3c6a66763f9b6a3935c5c64e145" ], "author": { "name": "Yong Wang", "email": "yong.y.wang@linux.intel.com", "time": "Thu Aug 05 10:38:43 2010 +0800" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Aug 04 22:08:45 2010 -0700" }, "message": "DMAENGINE: pch_dma: kill another usage of __raw_{read|write}l\n\nUse {read|write}l instead of __raw_{read|write}l since PCH DMA\ncontroller is PCI device.\n\nSigned-off-by: Yong Wang \u003cyong.y.wang@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "b9033e682e86f3c6a66763f9b6a3935c5c64e145", "tree": "8aeeb08aeae97b12f0c6cb7338d8cbcf15e6f8ac", "parents": [ "556ab45f9a775bfa4762bacc0a4afb5b44b067bc" ], "author": { "name": "Kulikov Vasiliy", "email": "segooon@gmail.com", "time": "Sat Jul 17 19:19:48 2010 +0400" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Aug 04 14:27:47 2010 -0700" }, "message": "dma: dmatest: fix potential sign bug\n\n\u0027cnt\u0027 is unsigned, so this code may become wrong in future as\ndmatest_add_threads() can return error code:\n\n\tcnt \u003d dmatest_add_threads(dtc, DMA_MEMCPY);\n\tthread_count +\u003d cnt \u003e 0 ? cnt : 0;\n\t\t ^^^^^^^\n\nNow it can return only -EINVAL if and only if second argument of\ndmatest_add_threads() is not one of DMA_MEMCPY, DMA_XOR, DMA_PQ.\nSo, now it is not wrong but may become wrong in future.\n\nThe semantic patch that finds this problem (many false-positive results):\n(http://coccinelle.lip6.fr/)\n\n// \u003csmpl\u003e\n@ r1 @\nidentifier f;\n@@\nint f(...) { ... }\n\n@@\nidentifier r1.f;\ntype T;\nunsigned T x;\n@@\n\n*x \u003d f(...)\n ...\n*x \u003e 0\n\nSigned-off-by: Kulikov Vasiliy \u003csegooon@gmail.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "556ab45f9a775bfa4762bacc0a4afb5b44b067bc", "tree": "6caf3f7c72617d50d78c4197b872fd0a22b18c99", "parents": [ "128f904ac87cb6e63921e80f378fdf9ba532c0f6" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Jul 23 15:47:56 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Aug 04 14:18:17 2010 -0700" }, "message": "ioat2: catch and recover from broken vtd configurations v6\n\nOn some platforms (MacPro3,1) the BIOS assigns the ioatdma device to the\nincorrect iommu causing faults when the driver initializes. Add a quirk\nto catch this misconfiguration and try falling back to untranslated\noperation (which works in the MacPro3,1 case).\n\nAssuming there are other platforms with misconfigured iommus teach the\nioatdma driver to treat initialization failures as non-fatal (just fail\nthe driver load and emit a warning instead of triggering a BUG_ON).\n\nThis can be classified as a boot regression since 2.6.32 on affected\nplatforms since the ioatdma module did not autoload prior to that\nkernel.\n\nCc: \u003cstable@kernel.org\u003e\nAcked-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\nReported-by: Chris Li \u003clkml@chrisli.org\u003e\nTested-by: Chris Li \u003clkml@chrisli.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "128f904ac87cb6e63921e80f378fdf9ba532c0f6", "tree": "381d7ad3151865b774a9b24a4063910dacfc9f2b", "parents": [ "95e1400fa1317e566b316ff4af947bd5341332c8" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@stericsson.com", "time": "Wed Aug 04 13:37:53 2010 +0200" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Aug 04 14:15:44 2010 -0700" }, "message": "DMAENGINE: add runtime slave control to COH 901 318 v3\n\nThis extends the DMA engine driver for the COH 901 318 used in the\nU300 platform with the generic runtime slave control command.\n\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "95e1400fa1317e566b316ff4af947bd5341332c8", "tree": "a2bdcd9729209f75eca11bc5b49b1b681a66c150", "parents": [ "c156d0a5b0c667999e06d0bb52e3d1376faec8bf" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@stericsson.com", "time": "Wed Aug 04 13:37:45 2010 +0200" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Aug 04 14:14:05 2010 -0700" }, "message": "DMAENGINE: add runtime slave config to DMA40 v3\n\nThis extends the DMA engine driver for the DMA40 used in the\nU8500 platform with the generic runtime slave configuration\ninterface.\n\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "0c42bd0e425e9c8ddb7019fc446f7d915e36c5f6", "tree": "8d89f7b5907bed52847451ab37619e9516ed7c3c", "parents": [ "b3c567e474b5ba4447b6e16063a3b0cffc22d205" ], "author": { "name": "Yong Wang", "email": "yong.y.wang@linux.intel.com", "time": "Fri Jul 30 16:23:03 2010 +0800" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Wed Aug 04 14:12:05 2010 -0700" }, "message": "dmaengine: Driver for Topcliff PCH DMA controller\n\nTopcliff PCH is the platform controller hub that is going to\nbe used in Intel\u0027s upcoming general embedded platforms. This\nadds the driver for Topcliff PCH DMA controller. The DMA\nchannels are strictly for device to host or host to device\ntransfers and cannot be used for generic memcpy.\n\nSigned-off-by: Yong Wang \u003cyong.y.wang@intel.com\u003e\n[kill GFP_ATOMIC, kill __raw_{read|write}l, locking fixlet]\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "d790d4d583aeaed9fc6f8a9f4d9f8ce6b1c15c7f", "tree": "854ab394486288d40fa8179cbfaf66e8bdc44b0f", "parents": [ "73b2c7165b76b20eb1290e7efebc33cfd21db1ca", "3a09b1be53d23df780a0cd0e4087a05e2ca4a00c" ], "author": { "name": "Jiri Kosina", "email": "jkosina@suse.cz", "time": "Wed Aug 04 15:14:38 2010 +0200" }, "committer": { "name": "Jiri Kosina", "email": "jkosina@suse.cz", "time": "Wed Aug 04 15:14:38 2010 +0200" }, "message": "Merge branch \u0027master\u0027 into for-next\n" }, { "commit": "c2e07b3a9ced33dd92597201be3931be8ea57ed6", "tree": "636de2e08a4ebbe7136d9ae16625f0297562ece9", "parents": [ "f4d01439515acd5d9a09de1d1e02ca40403dda49" ], "author": { "name": "Stefan Weil", "email": "weil@mail.berlios.de", "time": "Tue Aug 03 19:44:52 2010 +0200" }, "committer": { "name": "Jiri Kosina", "email": "jkosina@suse.cz", "time": "Wed Aug 04 15:05:43 2010 +0200" }, "message": "Fix spelling contorller -\u003e controller in comments\n\nCc: Jiri Kosina \u003ctrivial@kernel.org\u003e\nCc: linux-kernel@vger.kernel.org\nSigned-off-by: Stefan Weil \u003cweil@mail.berlios.de\u003e\nSigned-off-by: Jiri Kosina \u003cjkosina@suse.cz\u003e\n" }, { "commit": "b3c567e474b5ba4447b6e16063a3b0cffc22d205", "tree": "fa5f4f72fcf12dc53a5e58b5359038864595fe3e", "parents": [ "084a2ab9c258fb1efbb009f1bb1c6976da1f73f4" ], "author": { "name": "Vinod Koul", "email": "vinod.koul@intel.com", "time": "Wed Jul 21 13:28:10 2010 +0530" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jul 27 23:32:57 2010 -0700" }, "message": "intel_mid: Add Mrst \u0026 Mfld DMA Drivers\n\nThis patch add DMA drivers for DMA controllers in Langwell chipset\nof Intel(R) Moorestown platform and DMA controllers in Penwell of\nIntel(R) Medfield platfrom\n\nThis patch adds support for Moorestown DMAC1 and DMAC2 controllers.\nIt also add support for Medfiled GP DMA and DMAC1 controllers.\nThese controllers supports memory to peripheral and peripheral to\nmemory transfers. It support only single block transfers.\n\nThis driver is based on Kernel DMA engine\nAnyone who wishes to use this controller should use DMA engine APIs\n\nThis controller exposes DMA_SLAVE capabilities and notifies the client drivers\nof DMA transaction completion\n\nConfig option required to be enabled CONFIG_INTEL_MID_DMAC\u003dy\n\nSigned-off-by: Vinod Koul \u003cvinod.koul@intel.com\u003e\nSigned-off-by: Alan Cox \u003calan@linux.intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "285eba57db7bd7d7c3c5929fb8621fdcaaea1b00", "tree": "a9e7f0563cef296b24c53b20dbb388ec5c210172", "parents": [ "1c14e6cecb1811543b1016f27e5d308fbea8c08a", "815c4163b6c8ebf8152f42b0a5fd015cfdcedc78" ], "author": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Mon Jul 05 15:46:08 2010 +0900" }, "committer": { "name": "Paul Mundt", "email": "lethal@linux-sh.org", "time": "Mon Jul 05 15:46:08 2010 +0900" }, "message": "Merge branch \u0027master\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6\n\nConflicts:\n\tinclude/linux/serial_sci.h\n\nSigned-off-by: Paul Mundt \u003clethal@linux-sh.org\u003e\n" }, { "commit": "3e6b02d9f5a9715f7d4ff9e0978e5f9cef53d31f", "tree": "0e08d7cdff6856b7df8ec6a93f05787debb0f04c", "parents": [ "123f94f22e3d283dfe68742b269c245b0501ad82" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Fri Jul 02 15:46:17 2010 -0600" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Fri Jul 02 15:46:17 2010 -0600" }, "message": "of/dma: fix build breakage in ppc4xx adma driver\n\nConvert ppc4xx adma driver to use new node pointer location\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nAcked-by: Anatolij Gustschin \u003cagust@denx.de\u003e\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n" }, { "commit": "084a2ab9c258fb1efbb009f1bb1c6976da1f73f4", "tree": "4690ac23b3d9043dd26e84197d954c1813a71a0d", "parents": [ "f41855929c9fdc3b4f2863ada9df3e0cf4231b5b", "485680050166dc8c6ac976346430ab1f453c228b" ], "author": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Jul 01 02:29:19 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Jul 01 02:29:19 2010 -0700" }, "message": "Merge branch \u0027timb\u0027 into dmaengine\n" }, { "commit": "485680050166dc8c6ac976346430ab1f453c228b", "tree": "ee1400398cb1f88dcb975715e16dfa525db9cecf", "parents": [ "efcc28981745bc6aca88acb2d4d37d87f090a80a" ], "author": { "name": "Julia Lawall", "email": "julia@diku.dk", "time": "Thu May 27 14:33:17 2010 +0200" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Jul 01 02:27:35 2010 -0700" }, "message": "drivers/dma: Eliminate a NULL pointer dereference\n\nIf td_desc is NULL, just skip both kfrees.\n\nA simplified version of the semantic match that finds this problem is as\nfollows: (http://coccinelle.lip6.fr/)\n\n// \u003csmpl\u003e\n@r exists@\nexpression E,E1;\nidentifier f;\nstatement S1,S2,S3;\n@@\n\nif ((E \u003d\u003d NULL \u0026\u0026 ...) || ...)\n{\n ... when !\u003d if (...) S1 else S2\n when !\u003d E \u003d E1\n* E-\u003ef\n ... when any\n return ...;\n}\nelse S3\n// \u003c/smpl\u003e\n\nSigned-off-by: Julia Lawall \u003cjulia@diku.dk\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "efcc28981745bc6aca88acb2d4d37d87f090a80a", "tree": "16885dd51e2e10841dd8b011ff782dec7a8e54b8", "parents": [ "7e27d6e778cd87b6f2415515d7127eba53fe5d02" ], "author": { "name": "Dan Carpenter", "email": "error27@gmail.com", "time": "Tue May 25 11:55:06 2010 +0200" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Thu Jul 01 02:27:31 2010 -0700" }, "message": "dma/timb_dma: compile warning on 32 bit\n\nThis silences a compile warning on 32 bit systems:\ndrivers/dma/timb_dma.c:203: warning: cast to pointer from integer of different size\n\nSigned-off-by: Dan Carpenter \u003cerror27@gmail.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "f41855929c9fdc3b4f2863ada9df3e0cf4231b5b", "tree": "4a31c0bd50af7c13664352e929edcdd2bd5bbf26", "parents": [ "6b7acd84426235c63a3c0f0b230a95064f97b0d4" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@stericsson.com", "time": "Tue Jun 22 18:06:42 2010 -0700" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jun 22 18:06:42 2010 -0700" }, "message": "DMAENGINE: ste_dma40: support older silicon\n\nThis makes sure the DMA40 driver will also work on the oldest\nsilicon revisions that have the on-chip memory on another location\nin the DB8500 and also requires explicit suspend before starting\nor resuming a logical channel.\n\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\n[added parenthesis to the definition of U8500_DMA_LCPA_BASE_ED]\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "6b7acd84426235c63a3c0f0b230a95064f97b0d4", "tree": "e3b6e605493c387b3d522f05eb7cac0e6f5fda9d", "parents": [ "595167253a20167efae704ff2a8f6e2ee66cf25f" ], "author": { "name": "Jonas Aaberg", "email": "jonas.aberg@stericsson.com", "time": "Sun Jun 20 21:26:59 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jun 22 18:01:57 2010 -0700" }, "message": "DMAENGINE: ste_dma40: support disabling physical channels\n\nThis makes it possible to disable physical channels.\n\nSigned-off-by: Jonas Aaberg \u003cjonas.aberg@stericsson.com\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "d181b3a8cb2fc1732ad1826a5e6fdccab03e6a51", "tree": "421df4b6411a9b3acea2467237ad3b0e2fc20b4c", "parents": [ "8bc68fa51d7ed520cd4c69f74fb37add60b6ea47" ], "author": { "name": "Jonas Aaberg", "email": "jonas.aberg@stericsson.com", "time": "Sun Jun 20 21:26:38 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jun 22 18:01:56 2010 -0700" }, "message": "DMAENGINE: ste_dma40: fix suspend bug\n\nThis fixes a bug when suspending channels: first make the checks,\nthen suspend the channel, not the other way around.\n\nSigned-off-by: Jonas Aaberg \u003cjonas.aberg@stericsson.com\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "508849ade23c1167bfbdf557259398adfe7044b9", "tree": "e494544350342ea83a8c1a7b3fd8d4c4056e3057", "parents": [ "1d392a7ba43300b0bde877de15121b261d7a6ce2" ], "author": { "name": "Linus Walleij", "email": "linus.walleij@stericsson.com", "time": "Sun Jun 20 21:26:07 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jun 22 18:01:55 2010 -0700" }, "message": "DMAENGINE: ste_dma40: allocate LCLA dynamically\n\nSwitch to allocating LCLA in memory instead of having a fixed\naddress.\n\nSigned-off-by: Jonas Aaberg \u003cjonas.aberg@stericsson.com\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "1d392a7ba43300b0bde877de15121b261d7a6ce2", "tree": "2e45005cfbe64623117c764d791b9e98c75ebd52", "parents": [ "2123a61e174074b849fce2277412836b1b897942" ], "author": { "name": "Jonas Aaberg", "email": "jonas.aberg@stericsson.com", "time": "Sun Jun 20 21:26:01 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jun 22 18:01:55 2010 -0700" }, "message": "DMAENGINE: ste_dma40: no premature stop\n\nCorrect bug that could cause paused channels to stop.\n\nSigned-off-by: Jonas Aaberg \u003cjonas.aberg@stericsson.com\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" }, { "commit": "2123a61e174074b849fce2277412836b1b897942", "tree": "4f96e988dba2dcb3689cbb5c31a32ef2100e33b8", "parents": [ "0c32269d813c148194524fc8272f7ec1f7c90e6a" ], "author": { "name": "Jonas Aaberg", "email": "jonas.aberg@stericsson.com", "time": "Sun Jun 20 21:25:54 2010 +0000" }, "committer": { "name": "Dan Williams", "email": "dan.j.williams@intel.com", "time": "Tue Jun 22 18:01:55 2010 -0700" }, "message": "DMAENGINE: ste_dma40: interrupts only on dst\n\nWe don\u0027t want interrupts when the source is done, only when\nthe destination is done and everything is complete at the\nrecieveing end of a transfer.\n\nSigned-off-by: Jonas Aaberg \u003cjonas.aberg@stericsson.com\u003e\nSigned-off-by: Linus Walleij \u003clinus.walleij@stericsson.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n" } ], "next": "0c32269d813c148194524fc8272f7ec1f7c90e6a" }