)]}'
{
  "log": [
    {
      "commit": "4b01fef89a10cedbae9857e76283616af3f177cd",
      "tree": "3b75b60a12240a4e4c0bb379fcc327379f7d1971",
      "parents": [
        "cf840147d48626d5d86d617cbc5b7cddc1bcae14"
      ],
      "author": {
        "name": "Joe Perches",
        "email": "joe@perches.com",
        "time": "Sun Mar 23 01:03:10 2008 -0700"
      },
      "committer": {
        "name": "Ingo Molnar",
        "email": "mingo@elte.hu",
        "time": "Thu Apr 17 17:41:26 2008 +0200"
      },
      "message": "include/asm-x86/pgtable-3level.h: checkpatch cleanups - formatting only\n\nSigned-off-by: Joe Perches \u003cjoe@perches.com\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n"
    },
    {
      "commit": "f5430f93257d336346a9018c915e879ce43f5f89",
      "tree": "77f896b31b405801c6869694fb6c1eccc4b680c1",
      "parents": [
        "edd6bcd8209c31b91e1fbc112a756475091c483d"
      ],
      "author": {
        "name": "Jeremy Fitzhardinge",
        "email": "jeremy@goop.org",
        "time": "Mon Feb 04 16:48:02 2008 +0100"
      },
      "committer": {
        "name": "Ingo Molnar",
        "email": "mingo@elte.hu",
        "time": "Mon Feb 04 16:48:02 2008 +0100"
      },
      "message": "x86: update reference for PAE tlb flushing\n\nRemove bogus reference to \"Pentium-II erratum A13\" and point to the\nactual canonical source of information about what requirements x86\nprocessors have for PAE pagetable updates.\n\nSigned-off-by: Jeremy Fitzhardinge \u003cjeremy@xensource.com\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n"
    },
    {
      "commit": "edd6bcd8209c31b91e1fbc112a756475091c483d",
      "tree": "00495abdaa8343e34d8a6dfbd7825b10e85fd053",
      "parents": [
        "a67ad9c9f82342a9b320fdad204a490727ef4a18"
      ],
      "author": {
        "name": "Jeremy Fitzhardinge",
        "email": "jeremy@goop.org",
        "time": "Mon Feb 04 16:48:02 2008 +0100"
      },
      "committer": {
        "name": "Ingo Molnar",
        "email": "mingo@elte.hu",
        "time": "Mon Feb 04 16:48:02 2008 +0100"
      },
      "message": "x86: pud_clear: only reload cr3 if necessary\n\nRather than unconditionally reloading cr3, only do so if the pud we\u0027re\nupdating is within the active pgd.\n\nThis eliminates TLB flushes most of the time.  The\nperformance-critical uses of pud_clear are during execve and exit, but\nin those cases cr3 is referring to some other pagetable.  The only\nother use of pud_clear is during a large (1Gbyte+) munmap, and those\nare sufficiently rare that a couple of cr3 reloads won\u0027t hurt.\n\nSigned-off-by: Jeremy Fitzhardinge \u003cjeremy@xensource.com\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n"
    },
    {
      "commit": "a67ad9c9f82342a9b320fdad204a490727ef4a18",
      "tree": "47117746d64a3255e35fda69e8127d64e35fe122",
      "parents": [
        "e618c9579c745742c422b7c3de1f802aa67e6110"
      ],
      "author": {
        "name": "Jeremy Fitzhardinge",
        "email": "jeremy@goop.org",
        "time": "Mon Feb 04 16:48:02 2008 +0100"
      },
      "committer": {
        "name": "Ingo Molnar",
        "email": "mingo@elte.hu",
        "time": "Mon Feb 04 16:48:02 2008 +0100"
      },
      "message": "x86: revert \"defer cr3 reload when doing pud_clear()\"\n\nRevert \"defer cr3 reload when doing pud_clear()\" since I\u0027m going to\nreplace it.\n\nSigned-off-by: Jeremy Fitzhardinge \u003cjeremy@xensource.com\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n"
    },
    {
      "commit": "fa28ba21cec24d3fa1279bcae7e5d5ff6224635a",
      "tree": "dda47a7faa85428753691a50f49b0404f78ea0ec",
      "parents": [
        "f212ec4b7b4d84290f12c9c0416cdea283bf5f40"
      ],
      "author": {
        "name": "Jeremy Fitzhardinge",
        "email": "jeremy@goop.org",
        "time": "Wed Jan 30 13:34:11 2008 +0100"
      },
      "committer": {
        "name": "Ingo Molnar",
        "email": "mingo@elte.hu",
        "time": "Wed Jan 30 13:34:11 2008 +0100"
      },
      "message": "x86: defer cr3 reload when doing pud_clear()\n\nPAE mode requires that we reload cr3 in order to guarantee that\nchanges to the pgd will be noticed by the processor.  This means that\nin principle pud_clear needs to reload cr3 every time.  However,\nbecause reloading cr3 implies a tlb flush, we want to avoid it where\npossible.\n\npud_clear() is only used in a couple of places:\n - in free_pmd_range(), when pulling down a range of process address space, and\n - huge_pmd_unshare()\n\nIn both cases, the calling code will do a a tlb flush anyway, so\nthere\u0027s no need to do it within pud_clear().\n\nIn free_pmd_range(), the pud_clear is immediately followed by\npmd_free_tlb(); we can hook that to make the mmu_gather do an\nunconditional full flush to make sure cr3 gets reloaded.\n\nIn huge_pmd_unshare, it is followed by flush_tlb_range, which always\nresults in a full cr3-reload tlb flush.\n\nSigned-off-by: Jeremy Fitzhardinge \u003cjeremy@xensource.com\u003e\nCc: Andi Kleen \u003cak@suse.de\u003e\nCc: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\nCc: H. Peter Anvin \u003chpa@zytor.com\u003e\nCc: William Irwin \u003cwli@holomorphy.com\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n"
    },
    {
      "commit": "6194ba6ff6ccf8d5c54c857600843c67aa82c407",
      "tree": "657dd9f452b252260fcf59959c0586920b8fe4c3",
      "parents": [
        "fd40d6e3188b12c59696d6cb4a6f26333814d66f"
      ],
      "author": {
        "name": "Jeremy Fitzhardinge",
        "email": "jeremy@goop.org",
        "time": "Wed Jan 30 13:34:11 2008 +0100"
      },
      "committer": {
        "name": "Ingo Molnar",
        "email": "mingo@elte.hu",
        "time": "Wed Jan 30 13:34:11 2008 +0100"
      },
      "message": "x86: don\u0027t special-case pmd allocations as much\n\nIn x86 PAE mode, stop treating pmds as a special case.  Previously\nthey were always allocated and freed with the pgd.  The modifies the\ncode to be the same as 64-bit mode, where they are allocated on\ndemand.\n\nThis is a step on the way to unifying 32/64-bit pagetable allocation\nas much as possible.\n\nThere is a complicating wart, however.  When you install a new\nreference to a pmd in the pgd, the processor isn\u0027t guaranteed to see\nit unless you reload cr3.  Since reloading cr3 also has the\nside-effect of flushing the tlb, this is an expense that we want to\navoid whereever possible.\n\nThis patch simply avoids reloading cr3 unless the update is to the\ncurrent pagetable.  Later patches will optimise this further.\n\nSigned-off-by: Jeremy Fitzhardinge \u003cjeremy@xensource.com\u003e\nCc: Andi Kleen \u003cak@suse.de\u003e\nCc: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\nCc: H. Peter Anvin \u003chpa@zytor.com\u003e\nCc: William Irwin \u003cwli@holomorphy.com\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n"
    },
    {
      "commit": "4c3c4b4513a361cc6ac5ee8677695260c4f0f25f",
      "tree": "3a56ada5131a85fff2bb37841d822d098b92f68c",
      "parents": [
        "e66a95127dc4273d3573eb03657991f7bbd5dca3"
      ],
      "author": {
        "name": "Andi Kleen",
        "email": "ak@suse.de",
        "time": "Wed Jan 30 13:33:42 2008 +0100"
      },
      "committer": {
        "name": "Ingo Molnar",
        "email": "mingo@elte.hu",
        "time": "Wed Jan 30 13:33:42 2008 +0100"
      },
      "message": "x86: clean up pte_exec\n\n- Rename it to pte_exec() from pte_exec_kernel(). There is nothing\nkernel specific in there.\n- Move it into the common file because _PAGE_NX is 0 on !PAE and then\npte_exec() will be always evaluate to true.\n\nSigned-off-by: Andi Kleen \u003cak@suse.de\u003e\nSigned-off-by: Harvey Harrison \u003charvey.harrison@gmail.com\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n"
    },
    {
      "commit": "a5a19c63f4e55e32dc0bc3d936d7f94793d8b380",
      "tree": "3aaf621cd79889ed2658de2c30fa2fea42c86cf5",
      "parents": [
        "6c435456dc91ace468b4e9d72ad0e13dafa22a45"
      ],
      "author": {
        "name": "Jeremy Fitzhardinge",
        "email": "jeremy@goop.org",
        "time": "Wed Jan 30 13:33:39 2008 +0100"
      },
      "committer": {
        "name": "Ingo Molnar",
        "email": "mingo@elte.hu",
        "time": "Wed Jan 30 13:33:39 2008 +0100"
      },
      "message": "x86: demacro asm-x86/pgalloc_32.h\n\nConvert macros into inline functions, for better type-checking.\n\nThis patch required a little bit of fiddling with headers in order to\nmake __(pte|pmd)_free_tlb inline rather than macros.\nasm-generic/tlb.h includes asm/pgalloc.h, though it doesn\u0027t directly\nuse any pgalloc definitions.  I removed this include to avoid an\ninclude cycle, but it may cause secondary compile failures by things\ndepending on the indirect inclusion; arch/x86/mm/hugetlbpage.c was one\nsuch place; there may be others.\n\nSigned-off-by: Jeremy Fitzhardinge \u003cjeremy@xensource.com\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n"
    },
    {
      "commit": "4891645e764d2e181b834509a689fcd12e890c10",
      "tree": "f347227c2d5a5b112bca8fe76b149ccc5157ef84",
      "parents": [
        "8405b122ad0dd75354b3bfed4de9a96514fd40cb"
      ],
      "author": {
        "name": "Jeremy Fitzhardinge",
        "email": "jeremy@goop.org",
        "time": "Wed Jan 30 13:32:58 2008 +0100"
      },
      "committer": {
        "name": "Ingo Molnar",
        "email": "mingo@elte.hu",
        "time": "Wed Jan 30 13:32:58 2008 +0100"
      },
      "message": "x86: unify paravirt pagetable accessors\n\nPut all the defines for mapping pagetable operations to their native\nversions (for the non-paravirt case) into one place.  Make the\ncorresponding changes to paravirt.h.\n\nThe tricky part here is that when a pagetable entry can\u0027t be updated\natomically (ie, 32-bit PAE), we need special handlers for pte_clear,\nset_pte_atomic and set_pte_present.  However, the other two modes\ndon\u0027t need special handling for these, and can use a common\nset_pte(_at) path.\n\n[ mingo@elte.hu: fixes ]\n\nSigned-off-by: Jeremy Fitzhardinge \u003cjeremy@xensource.com\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n"
    },
    {
      "commit": "195466dc4b9b8a4cc89d37ea1211746f3afbc941",
      "tree": "38a4dc9e105d54cf285cdcbc141b424a2fc16f41",
      "parents": [
        "e33287013585e96180c575288bf1db22bee47b52"
      ],
      "author": {
        "name": "Jeremy Fitzhardinge",
        "email": "jeremy@goop.org",
        "time": "Wed Jan 30 13:32:58 2008 +0100"
      },
      "committer": {
        "name": "Ingo Molnar",
        "email": "mingo@elte.hu",
        "time": "Wed Jan 30 13:32:58 2008 +0100"
      },
      "message": "x86: pgtable: unify pte accessors\n\nMake various pte accessors common.\n\nSigned-off-by: Jeremy Fitzhardinge \u003cjeremy@xensource.com\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n"
    },
    {
      "commit": "c8e5393ab38564d2f45b560a2f95bc8f9ff6f823",
      "tree": "2976d59bb412786712bddec0eedf82e1db58401d",
      "parents": [
        "b7fff536d0ad45c4810f9b99845c707ceadc3afc"
      ],
      "author": {
        "name": "Jeremy Fitzhardinge",
        "email": "jeremy@goop.org",
        "time": "Wed Jan 30 13:32:57 2008 +0100"
      },
      "committer": {
        "name": "Ingo Molnar",
        "email": "mingo@elte.hu",
        "time": "Wed Jan 30 13:32:57 2008 +0100"
      },
      "message": "x86: page.h: make pte_t a union to always include\n\nMake sure pte_t, whatever its definition, has a pte element with type\npteval_t.  This allows common code to access it without needing to be\nspecifically parameterised on what pagetable mode we\u0027re compiling for.\nFor 32-bit, this means that pte_t becomes a union with \"pte\" and \"{\npte_low, pte_high }\" (PAE) or just \"pte_low\" (non-PAE).\n\nSigned-off-by: Jeremy Fitzhardinge \u003cjeremy@xensource.com\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n"
    },
    {
      "commit": "6fdc05d4794056e0b98901646c4b68c60a01d5eb",
      "tree": "a6cfb308becd6fe47c549084b29c3e9db3a07f68",
      "parents": [
        "c3bcfb57e1e64b9b2f8b2d90564826637e21c5ea"
      ],
      "author": {
        "name": "Jeremy Fitzhardinge",
        "email": "jeremy@goop.org",
        "time": "Wed Jan 30 13:32:57 2008 +0100"
      },
      "committer": {
        "name": "Ingo Molnar",
        "email": "mingo@elte.hu",
        "time": "Wed Jan 30 13:32:57 2008 +0100"
      },
      "message": "x86: unify pgtable accessors which use\n\nMake users of supported_pte_mask common.  This has the side-effect of\nintroducing the variable for 32-bit non-PAE, but I think its a pretty\nsmall cost to simplify the code.\n\nSigned-off-by: Jeremy Fitzhardinge \u003cjeremy@xensource.com\u003e\n\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n"
    },
    {
      "commit": "c3bcfb57e1e64b9b2f8b2d90564826637e21c5ea",
      "tree": "04f6a09f1b4fe9072d7f9539ce7832eeeab07dca",
      "parents": [
        "4614139c6a74fe02c85f702ba9c0e57f8e38647e"
      ],
      "author": {
        "name": "Jeremy Fitzhardinge",
        "email": "jeremy@goop.org",
        "time": "Wed Jan 30 13:32:57 2008 +0100"
      },
      "committer": {
        "name": "Ingo Molnar",
        "email": "mingo@elte.hu",
        "time": "Wed Jan 30 13:32:57 2008 +0100"
      },
      "message": "x86: mask NX from pte_pfn\n\nIn 32-bit PAE, mask NX from pte_pfn, since it isn\u0027t part of the PFN.\nThis code is due for unification anyway, but this fixes a latent bug.\n\nSigned-off-by: Jeremy Fitzhardinge \u003cjeremy@xensource.com\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n"
    },
    {
      "commit": "96a388de5dc53a8b234b3fd41f3ae2cedc9ffd42",
      "tree": "d947a467aa2da3140279617bc4b9b101640d7bf4",
      "parents": [
        "27bd0c955648646abf2a353a8371d28c37bcd982"
      ],
      "author": {
        "name": "Thomas Gleixner",
        "email": "tglx@linutronix.de",
        "time": "Thu Oct 11 11:20:03 2007 +0200"
      },
      "committer": {
        "name": "Thomas Gleixner",
        "email": "tglx@linutronix.de",
        "time": "Thu Oct 11 11:20:03 2007 +0200"
      },
      "message": "i386/x86_64: move headers to include/asm-x86\n\nMove the headers to include/asm-x86 and fixup the\nheader install make rules\n\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n"
    },
    {
      "commit": "45e98cdb6d365b34b7a2d849e4d8bdc264d8e6e4",
      "tree": "172a959293a2c31691a162eca6af131e3ac89da2",
      "parents": [
        "98011f569e2ae1e4ae394f6e23faa16676d50de4"
      ],
      "author": {
        "name": "Jan Beulich",
        "email": "jbeulich@novell.com",
        "time": "Sun Jul 15 23:38:17 2007 -0700"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@woody.linux-foundation.org",
        "time": "Mon Jul 16 09:05:36 2007 -0700"
      },
      "message": "page table handling cleanup\n\nKill pte_rdprotect(), pte_exprotect(), pte_mkread(), pte_mkexec(), pte_read(),\npte_exec(), and pte_user() except where arch-specific code is making use of\nthem.\n\nSigned-off-by: Jan Beulich \u003cjbeulich@novell.com\u003e\nCc: Andi Kleen \u003candi@firstfloor.org\u003e\nCc: Christoph Hellwig \u003chch@infradead.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n"
    },
    {
      "commit": "9e5e3162b2d5e4466187ecd63c9eec2de33cb7bc",
      "tree": "e0d9231574833f17b509bc2ca1971af90f657eb2",
      "parents": [
        "142dd975911fdd82b1b6f6617cd20ac90a8ccf00"
      ],
      "author": {
        "name": "Zachary Amsden",
        "email": "zach@vmware.com",
        "time": "Wed May 02 19:27:19 2007 +0200"
      },
      "committer": {
        "name": "Andi Kleen",
        "email": "andi@basil.nowhere.org",
        "time": "Wed May 02 19:27:19 2007 +0200"
      },
      "message": "[PATCH] i386: pte simplify ops\n\nAdd comment and condense code to make use of native_local_ptep_get_and_clear\nfunction.  Also, it turns out the 2-level and 3-level paging definitions were\nidentical, so move the common definition into pgtable.h\n\nSigned-off-by: Zachary Amsden \u003czach@vmware.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Andi Kleen \u003cak@suse.de\u003e\n"
    },
    {
      "commit": "142dd975911fdd82b1b6f6617cd20ac90a8ccf00",
      "tree": "1e72e96bce64d9301d3305b4dd0b30675c8676b0",
      "parents": [
        "c2c1accd4b2f9c82fb89d40611c7f581948db255"
      ],
      "author": {
        "name": "Zachary Amsden",
        "email": "zach@vmware.com",
        "time": "Wed May 02 19:27:19 2007 +0200"
      },
      "committer": {
        "name": "Andi Kleen",
        "email": "andi@basil.nowhere.org",
        "time": "Wed May 02 19:27:19 2007 +0200"
      },
      "message": "[PATCH] i386: pte xchg optimization\n\nIn situations where page table updates need only be made locally, and there is\nno cross-processor A/D bit races involved, we need not use the heavyweight\nxchg instruction to atomically fetch and clear page table entries.  Instead,\nwe can just read and clear them directly.\n\nThis introduces a neat optimization for non-SMP kernels; drop the atomic xchg\noperations from page table updates.\n\nThanks to Michel Lespinasse for noting this potential optimization.\n\nSigned-off-by: Zachary Amsden \u003czach@vmware.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Andi Kleen \u003cak@suse.de\u003e\n"
    },
    {
      "commit": "5311ab62cdc7788784971ed816ce85e926f3e994",
      "tree": "08ceda3c1bbdc6c403107f5329d775c772b752ce",
      "parents": [
        "90caccb9758e88db68a69553689baee38254287b"
      ],
      "author": {
        "name": "Jeremy Fitzhardinge",
        "email": "jeremy@goop.org",
        "time": "Wed May 02 19:27:13 2007 +0200"
      },
      "committer": {
        "name": "Andi Kleen",
        "email": "andi@basil.nowhere.org",
        "time": "Wed May 02 19:27:13 2007 +0200"
      },
      "message": "[PATCH] i386: PARAVIRT: Allow paravirt backend to choose kernel PMD sharing\n\nNormally when running in PAE mode, the 4th PMD maps the kernel address space,\nwhich can be shared among all processes (since they all need the same kernel\nmappings).\n\nXen, however, does not allow guests to have the kernel pmd shared between page\ntables, so parameterize pgtable.c to allow both modes of operation.\n\nThere are several side-effects of this.  One is that vmalloc will update the\nkernel address space mappings, and those updates need to be propagated into\nall processes if the kernel mappings are not intrinsically shared.  In the\nnon-PAE case, this is done by maintaining a pgd_list of all processes; this\nlist is used when all process pagetables must be updated.  pgd_list is\nthreaded via otherwise unused entries in the page structure for the pgd, which\nmeans that the pgd must be page-sized for this to work.\n\nNormally the PAE pgd is only 4x64 byte entries large, but Xen requires the PAE\npgd to page aligned anyway, so this patch forces the pgd to be page\naligned+sized when the kernel pmd is unshared, to accomodate both these\nrequirements.\n\nAlso, since there may be several distinct kernel pmds (if the user/kernel\nsplit is below 3G), there\u0027s no point in allocating them from a slab cache;\nthey\u0027re just allocated with get_free_page and initialized appropriately.  (Of\ncourse the could be cached if there is just a single kernel pmd - which is the\ndefault with a 3G user/kernel split - but it doesn\u0027t seem worthwhile to add\nyet another case into this code).\n\n[ Many thanks to wli for review comments. ]\n\nSigned-off-by: Jeremy Fitzhardinge \u003cjeremy@xensource.com\u003e\nSigned-off-by: William Lee Irwin III \u003cwli@holomorphy.com\u003e\nSigned-off-by: Andi Kleen \u003cak@suse.de\u003e\nCc: Zachary Amsden \u003czach@vmware.com\u003e\nCc: Christoph Lameter \u003cclameter@sgi.com\u003e\nAcked-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\n"
    },
    {
      "commit": "3dc494e86d1c93afd4c66385f270899dbfae483d",
      "tree": "6583b57492dc91ef7cc6c23a233f7d5bb95bb5f6",
      "parents": [
        "45876233605c268e929a7875081e129debe34bdc"
      ],
      "author": {
        "name": "Jeremy Fitzhardinge",
        "email": "jeremy@goop.org",
        "time": "Wed May 02 19:27:13 2007 +0200"
      },
      "committer": {
        "name": "Andi Kleen",
        "email": "andi@basil.nowhere.org",
        "time": "Wed May 02 19:27:13 2007 +0200"
      },
      "message": "[PATCH] i386: PARAVIRT: Add pagetable accessors to pack and unpack pagetable entries\n\nAdd a set of accessors to pack, unpack and modify page table entries\n(at all levels).  This allows a paravirt implementation to control the\ncontents of pgd/pmd/pte entries.  For example, Xen uses this to\nconvert the (pseudo-)physical address into a machine address when\npopulating a pagetable entry, and converting back to pphys address\nwhen an entry is read.\n\nSigned-off-by: Jeremy Fitzhardinge \u003cjeremy@xensource.com\u003e\nSigned-off-by: Andi Kleen \u003cak@suse.de\u003e\nAcked-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n"
    },
    {
      "commit": "8ecb8950695e907ed25acffec9e98c6806e311c8",
      "tree": "dfa4a6cf29b1f6fe173a0d6998b3f3fb55b5422f",
      "parents": [
        "dfbea0ad50e08c52539bddce977b07f77a762ba4"
      ],
      "author": {
        "name": "Zachary Amsden",
        "email": "zach@vmware.com",
        "time": "Thu Dec 07 02:14:09 2006 +0100"
      },
      "committer": {
        "name": "Andi Kleen",
        "email": "andi@basil.nowhere.org",
        "time": "Thu Dec 07 02:14:09 2006 +0100"
      },
      "message": "[PATCH] paravirt: fix missing pte update\n\nThe function ptep_get_and_clear uses an atomic instruction sequence to get and\nclear an active pte.  Rather than add such an atomic operator to all virtual\nmachine implementations in paravirt-ops, it is easier to support the raw\natomic sequence and use either a trapping writable pagetable approach, or a\npost-update notification.  For the post update notification, we require the\npte_update function to be called after the access.  Combine the 2-level and\n3-level paging operators into one common function which does the post-update\nnotification, and rename the actual atomic sequences to raw_ptep_xxx\noperators.\n\nSigned-off-by: Zachary Amsden \u003czach@vmware.com\u003e\nSigned-off-by: Andi Kleen \u003cak@suse.de\u003e\nCc: Andi Kleen \u003cak@muc.de\u003e\nCc: Jeremy Fitzhardinge \u003cjeremy@goop.org\u003e\nCc: Chris Wright \u003cchrisw@sous-sol.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\n"
    },
    {
      "commit": "a2952d8949bb0b37c1be92a89c4f180c74292857",
      "tree": "b2a872efdcac997695661c2578679aef70d26afb",
      "parents": [
        "bd472c794bbf6771c3fc1c58f188bc16c393d2fe"
      ],
      "author": {
        "name": "Zachary Amsden",
        "email": "zach@vmware.com",
        "time": "Thu Dec 07 02:14:08 2006 +0100"
      },
      "committer": {
        "name": "Andi Kleen",
        "email": "andi@basil.nowhere.org",
        "time": "Thu Dec 07 02:14:08 2006 +0100"
      },
      "message": "[PATCH] paravirt: Preparatory mmu header movement\n\nMove header includes for the nopud / nopmd types to the location of the actual\npte / pgd type definitions.  This allows generic 4-level page type code to be\nwritten before the split 2/3 level page table headers are included.\n\nSigned-off-by: Zachary Amsden \u003czach@vmware.com\u003e\nSigned-off-by: Andi Kleen \u003cak@suse.de\u003e\nCc: Andi Kleen \u003cak@muc.de\u003e\nCc: Jeremy Fitzhardinge \u003cjeremy@goop.org\u003e\nCc: Chris Wright \u003cchrisw@sous-sol.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\n"
    },
    {
      "commit": "da181a8b3916aa7f2e3c5775d2bd2fe3454cf82d",
      "tree": "c5be6c957d57563b9854732df1210aad97027b03",
      "parents": [
        "13623d79309dd82e1964458fa017979d16f33fa8"
      ],
      "author": {
        "name": "Rusty Russell",
        "email": "rusty@rustcorp.com.au",
        "time": "Thu Dec 07 02:14:08 2006 +0100"
      },
      "committer": {
        "name": "Andi Kleen",
        "email": "andi@basil.nowhere.org",
        "time": "Thu Dec 07 02:14:08 2006 +0100"
      },
      "message": "[PATCH] paravirt: Add MMU virtualization to paravirt_ops\n\nAdd the three bare TLB accessor functions to paravirt-ops.  Most amusingly,\nflush_tlb is redefined on SMP, so I can\u0027t call the paravirt op flush_tlb.\nInstead, I chose to indicate the actual flush type, kernel (global) vs. user\n(non-global).  Global in this sense means using the global bit in the page\ntable entry, which makes TLB entries persistent across CR3 reloads, not\nglobal as in the SMP sense of invoking remote shootdowns, so the term is\nconfusingly overloaded.\n\nAK: folded in fix from Zach for PAE compilation\n\nSigned-off-by: Zachary Amsden \u003czach@vmware.com\u003e\nSigned-off-by: Chris Wright \u003cchrisw@sous-sol.org\u003e\nSigned-off-by: Andi Kleen \u003cak@suse.de\u003e\nCc: Rusty Russell \u003crusty@rustcorp.com.au\u003e\nCc: Jeremy Fitzhardinge \u003cjeremy@goop.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\n"
    },
    {
      "commit": "a93cb055a23f3172c1e6a22ac1dc4f1c07929b08",
      "tree": "b2118140583912c78d42a3ba950be39815addc14",
      "parents": [
        "d6d861e3c963b4077c83e078e3e300c4b81f93e7"
      ],
      "author": {
        "name": "Zachary Amsden",
        "email": "zach@vmware.com",
        "time": "Sat Sep 30 23:29:37 2006 -0700"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@g5.osdl.org",
        "time": "Sun Oct 01 00:39:34 2006 -0700"
      },
      "message": "[PATCH] paravirt: remove set pte atomic\n\nNow that ptep_establish has a definition in PAE i386 3-level paging code, the\nonly paging model which is insane enough to have multi-word hardware PTEs\nwhich are not efficient to set atomically, we can remove the ghost of\nset_pte_atomic from other architectures which falesly duplicated it, and\nremove all knowledge of it from the generic pgtable code.\n\nset_pte_atomic is now a private pte operator which is specific to i386\n\nSigned-off-by: Zachary Amsden \u003czach@vmware.com\u003e\nCc: Rusty Russell \u003crusty@rustcorp.com.au\u003e\nCc: Jeremy Fitzhardinge \u003cjeremy@xensource.com\u003e\nCc: Andi Kleen \u003cak@suse.de\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n"
    },
    {
      "commit": "d6d861e3c963b4077c83e078e3e300c4b81f93e7",
      "tree": "842071ac905575aa0ea8bedd3a1ac5db29416bcf",
      "parents": [
        "23002d88be309a7c78db69363c9d933a29a3b0bb"
      ],
      "author": {
        "name": "Zachary Amsden",
        "email": "zach@vmware.com",
        "time": "Sat Sep 30 23:29:36 2006 -0700"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@g5.osdl.org",
        "time": "Sun Oct 01 00:39:34 2006 -0700"
      },
      "message": "[PATCH] paravirt: optimize ptep establish for pae\n\nThe ptep_establish macro is only used on user-level PTEs, for P-\u003eP mapping\nchanges.  Since these always happen under protection of the pagetable lock,\nthe strong synchronization of a 64-bit cmpxchg is not needed, in fact, not\neven a lock prefix needs to be used.  We can simply instead clear the P-bit,\nfollowed by a normal set.  The write ordering is still important to avoid the\npossibility of the TLB snooping a partially written PTE and getting a bad\nmapping installed.\n\nSigned-off-by: Zachary Amsden \u003czach@vmware.com\u003e\nCc: Rusty Russell \u003crusty@rustcorp.com.au\u003e\nCc: Jeremy Fitzhardinge \u003cjeremy@xensource.com\u003e\nCc: Andi Kleen \u003cak@suse.de\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n"
    },
    {
      "commit": "6049742dbcecf170e903638a029f4dc280b9d53d",
      "tree": "1712d4116a622336f793dc4591b1e2ac85e0aa2e",
      "parents": [
        "673eae8230a192f07b8715b872d6925521e9738d"
      ],
      "author": {
        "name": "Rusty Russell",
        "email": "rusty@rustcorp.com.au",
        "time": "Mon Sep 25 23:32:30 2006 -0700"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@g5.osdl.org",
        "time": "Tue Sep 26 08:48:56 2006 -0700"
      },
      "message": "[PATCH] x86: trivial move of __HAVE macros in i386 pagetable headers\n\nMove the __HAVE_ARCH_PTEP defines to accompany the function definitions.\nAnything else is just a complete nightmare to track through the 2/3-level\npaging code, and this caused duplicate definitions to be needed (pte_same),\nwhich could have easily been taken care of with the asm-generic pgtable\nfunctions.\n\nSigned-off-by: Zachary Amsden \u003czach@vmware.com\u003e\nSigned-off-by: Rusty Russell \u003crusty@rustcorp.com.au\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n"
    },
    {
      "commit": "46a82b2d5591335277ed2930611f6acb4ce654ed",
      "tree": "e90bc1843701af2012bae92564f7109027a8244f",
      "parents": [
        "d2e7b7d0aa021847c59f882b066e7d3812902870"
      ],
      "author": {
        "name": "Dave McCracken",
        "email": "dmccr@us.ibm.com",
        "time": "Mon Sep 25 23:31:48 2006 -0700"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@g5.osdl.org",
        "time": "Tue Sep 26 08:48:51 2006 -0700"
      },
      "message": "[PATCH] Standardize pxx_page macros\n\nOne of the changes necessary for shared page tables is to standardize the\npxx_page macros.  pte_page and pmd_page have always returned the struct\npage associated with their entry, while pte_page_kernel and pmd_page_kernel\nhave returned the kernel virtual address.  pud_page and pgd_page, on the\nother hand, return the kernel virtual address.\n\nShared page tables needs pud_page and pgd_page to return the actual page\nstructures.  There are very few actual users of these functions, so it is\nsimple to standardize their usage.\n\nSince this is basic cleanup, I am submitting these changes as a standalone\npatch.  Per Hugh Dickins\u0027 comments about it, I am also changing the\npxx_page_kernel macros to pxx_page_vaddr to clarify their meaning.\n\nSigned-off-by: Dave McCracken \u003cdmccr@us.ibm.com\u003e\nCc: Hugh Dickins \u003chugh@veritas.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n"
    },
    {
      "commit": "6e5882cfa24e1456702e463f6920fc0ca3c3d2b8",
      "tree": "636800c0619ec3551f9a8a7da707d913937cf43d",
      "parents": [
        "2be4d50295e2b6f62c07b614e1b103e280dddb84"
      ],
      "author": {
        "name": "Zachary Amsden",
        "email": "zach@vmware.com",
        "time": "Thu Apr 27 11:32:29 2006 -0700"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@g5.osdl.org",
        "time": "Thu Apr 27 12:00:59 2006 -0700"
      },
      "message": "[PATCH] x86/PAE: Fix pte_clear for the \u003e4GB RAM case\n\nProposed fix for ptep_get_and_clear_full PAE bug.  Pte_clear had the same bug,\nso use the same fix for both.  Turns out pmd_clear had it as well, but pgds\nare not affected.\n\nThe problem is rather intricate.  Page table entries in PAE mode are 64-bits\nwide, but the only atomic 8-byte write operation available in 32-bit mode is\ncmpxchg8b, which is expensive (at least on P4), and thus avoided.  But it can\nhappen that the processor may prefetch entries into the TLB in the middle of an\noperation which clears a page table entry.  So one must always clear the P-bit\nin the low word of the page table entry first when clearing it.\n\nSince the sequence *ptep \u003d __pte(0) leaves the order of the write dependent on\nthe compiler, it must be coded explicitly as a clear of the low word followed\nby a clear of the high word.  Further, there must be a write memory barrier\nhere to enforce proper ordering by the compiler (and, in the future, by the\nprocessor as well).\n\nOn \u003e 4GB memory machines, the implementation of pte_clear for PAE was clearly\ndeficient, as it could leave virtual mappings of physical memory above 4GB\naliased to memory below 4GB in the TLB.  The implementation of\nptep_get_and_clear_full has a similar bug, although not nearly as likely to\noccur, since the mappings being cleared are in the process of being destroyed,\nand should never be dereferenced again.\n\nBut, as luck would have it, it is possible to trigger bugs even without ever\ndereferencing these bogus TLB mappings, even if the clear is followed fairly\nsoon after with a TLB flush or invalidation.  The problem is that memory above\n4GB may now be aliased into the first 4GB of memory, and in fact, may hit a\nregion of memory with non-memory semantics.  These regions include AGP and PCI\nspace.  As such, these memory regions are not cached by the processor.  This\nintroduces the bug.\n\nThe processor can speculate memory operations, including memory writes, as long\nas they are committed with the proper ordering.  Speculating a memory write to\na linear address that has a bogus TLB mapping is possible.  Normally, the\nspeculation is harmless.  But for cached memory, it does leave the falsely\nspeculated cacheline unmodified, but in a dirty state.  This cache line will be\neventually written back.  If this cacheline happens to intersect a region of\nmemory that is not protected by the cache coherency protocol, it can corrupt\ndata in I/O memory, which is generally a very bad thing to do, and can cause\ntotal system failure or just plain undefined behavior.\n\nThese bugs are extremely unlikely, but the severity is of such magnitude, and\nthe fix so simple that I think fixing them immediately is justified.  Also,\nthey are nearly impossible to debug.\n\nSigned-off-by: Zachary Amsden \u003czach@vmware.com\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n"
    },
    {
      "commit": "101f12af16fb12f8da8100899a13ee1b1b576a0a",
      "tree": "0bea73d2702ba438e8e82bc8000b498aa50aee6e",
      "parents": [
        "44fd22992cb76dc51c52cf4b8aff1bc7899bb23c"
      ],
      "author": {
        "name": "Jan Beulich",
        "email": "jbeulich@novell.com",
        "time": "Thu Mar 23 02:59:45 2006 -0800"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@g5.osdl.org",
        "time": "Thu Mar 23 07:38:05 2006 -0800"
      },
      "message": "[PATCH] i386: actively synchronize vmalloc area when registering certain callbacks\n\nRegistering a callback handler through register_die_notifier() is obviously\nprimarily intended for use by modules.  However, the way these currently\nget called it is basically impossible for them to actually be used by\nmodules, as there is, on non-PAE configurationes, a good chance (the larger\nthe module, the better) for the system to crash as a result.\n\nThis is because the callback gets invoked\n\n(a) in the page fault path before the top level page table propagation\n    gets carried out (hence a fault to propagate the top level page table\n    entry/entries mapping to module\u0027s code/data would nest infinitly) and\n\n(b) in the NMI path, where nested faults must absolutely not happen,\n    since otherwise the IRET from the nested fault re-enables NMIs,\n    potentially resulting in nested NMI occurences.\n\nBesides the modular aspect, similar problems would even arise for in-\nkernel consumers of the API if they touched ioremap()ed or vmalloc()ed\nmemory inside their handlers.\n\nSigned-off-by: Jan Beulich \u003cjbeulich@novell.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n"
    },
    {
      "commit": "ca140fdadbe4c031a20a970f46163908d09a116b",
      "tree": "5dff340fd0bb88751604d7d7ffdcb0fe55144005",
      "parents": [
        "d16aafff2570abb557a5cb18c98027aabd602e22"
      ],
      "author": {
        "name": "Paolo \u0027Blaisorblade\u0027 Giarrusso",
        "email": "blaisorblade@yahoo.it",
        "time": "Sun Oct 30 14:59:31 2005 -0800"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@g5.osdl.org",
        "time": "Sun Oct 30 17:37:12 2005 -0800"
      },
      "message": "[PATCH] i386: little pgtable.h consolidation vs 2/3level\n\nJoin together some common functions (pmd_page{,_kernel}) over 2level and\n3level pages.\n\nSigned-off-by: Paolo \u0027Blaisorblade\u0027 Giarrusso \u003cblaisorblade@yahoo.it\u003e\nAcked-by: Hugh Dickins \u003chugh@veritas.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n"
    },
    {
      "commit": "c9b02a24130e3ff14a553d966a79f46cf806b037",
      "tree": "1c496ef13e8d2d991f5197ec1c1eb34282beddf0",
      "parents": [
        "e7a2ff593c0e48b130434dee4d2fd3452a850e6f"
      ],
      "author": {
        "name": "Zachary Amsden",
        "email": "zach@vmware.com",
        "time": "Sat Sep 03 15:56:40 2005 -0700"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@evo.osdl.org",
        "time": "Mon Sep 05 00:06:12 2005 -0700"
      },
      "message": "[PATCH] i386: use set_pte macros in a couple places where they were missing\n\nAlso, setting PDPEs in PAE mode does not require atomic operations, since the\nPDPEs are cached by the processor, and only reloaded on an explicit or\nimplicit reload of CR3.\n\nSince the four PDPEs must always be present in an active root, and the kernel\nPDPE is never updated, we are safe even from SMIs and interrupts / NMIs using\ntask gates (which reload CR3).  Actually, much of this is moot, since the user\nPDPEs are never updated either, and the only usage of task gates is by the\ndoublefault handler.  It appears the only place PGDs get updated in PAE mode\nis in init_low_mappings() / zap_low_mapping() for initial page table creation\nand recovery from ACPI sleep state, and these sites are safe by inspection.\nGetting rid of the cmpxchg8b saves code space and 720 cycles in pgd_alloc on\nP4.\n\nSigned-off-by: Zachary Amsden \u003czach@vmware.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n"
    },
    {
      "commit": "1da177e4c3f41524e886b7f1b8a0c1fc7321cac2",
      "tree": "0bba044c4ce775e45a88a51686b5d9f90697ea9d",
      "parents": [],
      "author": {
        "name": "Linus Torvalds",
        "email": "torvalds@ppc970.osdl.org",
        "time": "Sat Apr 16 15:20:36 2005 -0700"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@ppc970.osdl.org",
        "time": "Sat Apr 16 15:20:36 2005 -0700"
      },
      "message": "Linux-2.6.12-rc2\n\nInitial git repository build. I\u0027m not bothering with the full history,\neven though we have it. We can create a separate \"historical\" git\narchive of that later if we want to, and in the meantime it\u0027s about\n3.2GB when imported into git - space that would just make the early\ngit days unnecessarily complicated, when we don\u0027t have a lot of good\ninfrastructure for it.\n\nLet it rip!\n"
    }
  ]
}