)]}'
{
  "log": [
    {
      "commit": "3f65ce4d141e435e54c20ed2379d983d362a2cb5",
      "tree": "1e86807b3f215d90d9cf57aa609f73f856515b30",
      "parents": [
        "249ac17e96811acc3c6402317dd5d5c89d2cbf68"
      ],
      "author": {
        "name": "Chris Zankel",
        "email": "czankel@tensilica.com",
        "time": "Thu Jun 23 22:01:24 2005 -0700"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@ppc970.osdl.org",
        "time": "Fri Jun 24 00:05:22 2005 -0700"
      },
      "message": "[PATCH] xtensa: Architecture support for Tensilica Xtensa Part 5\n\nThe attached patches provides part 5 of an architecture implementation for the\nTensilica Xtensa CPU series.\n\nSigned-off-by: Chris Zankel \u003cchris@zankel.net\u003e\nSigned-off-by: Andrew Morton \u003cakpm@osdl.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n"
    }
  ]
}