)]}' { "log": [ { "commit": "166c0eaedfc3157dc1394c27e827add19f05fb27", "tree": "fd4fa4fc8064dbe54ee18bf75da37ca18ea863ba", "parents": [ "7123a6cab02ebc5dca61d0e341267578b245f2f3" ], "author": { "name": "Mark Salter", "email": "msalter@redhat.com", "time": "Sun Jan 08 13:25:56 2012 -0500" }, "committer": { "name": "Mark Salter", "email": "msalter@redhat.com", "time": "Sun Jan 08 15:13:16 2012 -0500" }, "message": "C6X: replace tick_nohz_stop/restart_sched_tick calls\n\nThe following commits replaced the tick_nohz_{stop,restart}_sched_tick\nAPI with separate tick and rcu calls:\n\n 280f06774afedf849f0b34248ed6aff57d0f6908\n 2bbb6817c0ac1b5f2a68d720f364f98eeb1ac4fd\n 1268fbc746ea1cd279886a740dcbad4ba5232225\n\nThis patch replaces the C6X use of the old API with the newer interfaces.\n\nSigned-off-by: Mark Salter \u003cmsalter@redhat.com\u003e\n" }, { "commit": "7123a6cab02ebc5dca61d0e341267578b245f2f3", "tree": "1f65b1733438c47730250413297db7f81f3d63ff", "parents": [ "d5981a5f16ed8d648b7f44e4aa19cd25733518a3" ], "author": { "name": "Mark Salter", "email": "msalter@redhat.com", "time": "Sun Jan 08 13:19:38 2012 -0500" }, "committer": { "name": "Mark Salter", "email": "msalter@redhat.com", "time": "Sun Jan 08 15:13:10 2012 -0500" }, "message": "C6X: add register_cpu call\n\nCommit ccbc60d3e19a1b6ae66ca0d89b3da02dde62088b requires CPU\ntopology information even in !SMP cases. This requires C6X to\nadd a call tp register_cpu() in order to avoid a panic at\nboot time.\n\nSigned-off-by: Mark Salter \u003cmsalter@redhat.com\u003e\n" }, { "commit": "d5981a5f16ed8d648b7f44e4aa19cd25733518a3", "tree": "62afc89db8128512abb6bf053207b61218950e9a", "parents": [ "25b48ff852e2e71b0d44d8ee6f69c9b704bd5070" ], "author": { "name": "Mark Salter", "email": "msalter@redhat.com", "time": "Sun Jan 08 12:31:28 2012 -0500" }, "committer": { "name": "Mark Salter", "email": "msalter@redhat.com", "time": "Sun Jan 08 15:12:44 2012 -0500" }, "message": "C6X: deal with memblock API changes\n\nRecent memblock related commits require the following C6X changes:\n\n * commit 24aa07882b672fff2da2f5c955759f0bd13d32d5\n asm/memblock.h no longer required\n\n * commit 1440c4e2c918532f39131c3330fe2226e16be7b6\n memblock_analyze() no longer needed to update total size\n\n * commit fe091c208a40299fba40e62292a610fb91e44b4e\n memblock_init() no longer needed\n\nSigned-off-by: Mark Salter \u003cmsalter@redhat.com\u003e\n" }, { "commit": "25b48ff852e2e71b0d44d8ee6f69c9b704bd5070", "tree": "ee48a9e41d4cdeffcbb68b50261576887357e7a2", "parents": [ "4a059ff3a9a8bd4ee78e3b89721b698ddb43d385" ], "author": { "name": "Mark Salter", "email": "msalter@redhat.com", "time": "Sat Nov 05 10:57:40 2011 -0400" }, "committer": { "name": "Mark Salter", "email": "msalter@redhat.com", "time": "Sun Jan 08 15:12:17 2012 -0500" }, "message": "C6X: fix timer64 initialization\n\nSome SoCs have a timer block enable controlled through the DSCR registers.\nThere is a problem in the timer64 driver initialization where the code\naccesses a timer register to get the divisor used to calculate timer clock\nrate. If the timer block has not been enabled when this register read takes\nplace, an exception is generated. This patch makes sure that the timer block\nis enabled before accessing the registers.\n\nSigned-off-by: Mark Salter \u003cmsalter@redhat.com\u003e\n" }, { "commit": "4a059ff3a9a8bd4ee78e3b89721b698ddb43d385", "tree": "a7b8c0a4f9e15063ff3cefbb1cfdaa2cf6eb1449", "parents": [ "2141355fcd4d2c95132226434d38f1c6ffff4105" ], "author": { "name": "Mark Salter", "email": "msalter@redhat.com", "time": "Sat Nov 05 10:57:21 2011 -0400" }, "committer": { "name": "Mark Salter", "email": "msalter@redhat.com", "time": "Sun Jan 08 15:12:09 2012 -0500" }, "message": "C6X: fix layout of EMIFA registers\n\nSigned-off-by: Mark Salter \u003cmsalter@redhat.com\u003e\n" }, { "commit": "9de98fb4ec4c91597feedc521120c16fca54a5b6", "tree": "bb956a3946cf547d82edf854bdfc960126f31c4b", "parents": [ "6bbfd8975cf3b78aadd1513a25bf7b5c04866a6f" ], "author": { "name": "Mark Salter", "email": "msalter@redhat.com", "time": "Tue Oct 04 11:20:28 2011 -0400" }, "committer": { "name": "Mark Salter", "email": "msalter@redhat.com", "time": "Thu Oct 06 19:48:36 2011 -0400" }, "message": "C6X: DSCR - Device State Configuration Registers\n\nAll SoCs provide an area of device configuration registers called the DSCR. The\nlocation of specific registers as well as their use varies considerably from\nimplementation to implementation. Rather than having to rely on additional\nSoC-specific DSCR code for each new supported SoC, this code generalize things\nas much as possible using device tree properties. Initialization must take\nplace early on (setup_arch time) in case the event timer device needs to be\nenable via the DSCR.\n\nSigned-off-by: Mark Salter \u003cmsalter@redhat.com\u003e\nSigned-off-by: Aurelien Jacquiot \u003ca-jacquiot@ti.com\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n" }, { "commit": "6bbfd8975cf3b78aadd1513a25bf7b5c04866a6f", "tree": "7fbf3046fac7494dd7b0675b623cf6161aaefc17", "parents": [ "69910a284cee7864c9bf96e13505a4ab35ab8dce" ], "author": { "name": "Mark Salter", "email": "msalter@redhat.com", "time": "Tue Oct 04 11:18:46 2011 -0400" }, "committer": { "name": "Mark Salter", "email": "msalter@redhat.com", "time": "Thu Oct 06 19:48:29 2011 -0400" }, "message": "C6X: EMIF - External Memory Interface\n\nSeveral SoC parts provide a simple bridge to support external memory mapped\ndevices. This code probes the device tree for an EMIF node and sets up the\nbridge registers if such a node is found. Beyond initial set up, there is no\nfurther need to access the bridge control registers. External devices on the\nbus are accessed through their MMIO registers using suitable drivers. The\nbridge hardware does provide for timeout and other error interrupts, but these\nare not yet supported.\n\nSigned-off-by: Mark Salter \u003cmsalter@redhat.com\u003e\nSigned-off-by: Aurelien Jacquiot \u003ca-jacquiot@ti.com\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n" }, { "commit": "69910a284cee7864c9bf96e13505a4ab35ab8dce", "tree": "8610fa7cbd9055c3c639cf9058a5a8ae15244a38", "parents": [ "09831ca73443bd819ad7993db5409b19c899ba33" ], "author": { "name": "Mark Salter", "email": "msalter@redhat.com", "time": "Tue Oct 04 11:17:47 2011 -0400" }, "committer": { "name": "Mark Salter", "email": "msalter@redhat.com", "time": "Thu Oct 06 19:48:26 2011 -0400" }, "message": "C6X: general SoC support\n\nThis patch provides a soc_ops struct which provides hooks for SoC functionality\nwhich doesn\u0027t fit well into other places.\n\nSigned-off-by: Mark Salter \u003cmsalter@redhat.com\u003e\nSigned-off-by: Aurelien Jacquiot \u003ca-jacquiot@ti.com\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n" }, { "commit": "09831ca73443bd819ad7993db5409b19c899ba33", "tree": "4558fb0a5e0e1fcd8582be2155cd9c7498e429db", "parents": [ "a7f626c1948ab6178d2338831c5ffea7385e9f7f" ], "author": { "name": "Aurelien Jacquiot", "email": "a-jacquiot@ti.com", "time": "Tue Oct 04 11:15:51 2011 -0400" }, "committer": { "name": "Mark Salter", "email": "msalter@redhat.com", "time": "Thu Oct 06 19:48:23 2011 -0400" }, "message": "C6X: library code\n\nOriginal port to early 2.6 kernel using TI COFF toolchain.\nBrought up to date by Mark Salter \u003cmsalter@redhat.com\u003e\n\nSigned-off-by: Aurelien Jacquiot \u003ca-jacquiot@ti.com\u003e\nSigned-off-by: Mark Salter \u003cmsalter@redhat.com\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n" }, { "commit": "a7f626c1948ab6178d2338831c5ffea7385e9f7f", "tree": "03eaee71023fa633c24a3d28a30da57b454293ae", "parents": [ "52679b2d735492bce02503bafb333da87fae22c2" ], "author": { "name": "Aurelien Jacquiot", "email": "a-jacquiot@ti.com", "time": "Tue Oct 04 11:14:47 2011 -0400" }, "committer": { "name": "Mark Salter", "email": "msalter@redhat.com", "time": "Thu Oct 06 19:48:20 2011 -0400" }, "message": "C6X: headers\n\nOriginal port to early 2.6 kernel using TI COFF toolchain.\nBrought up to date by Mark Salter \u003cmsalter@redhat.com\u003e\n\nSigned-off-by: Aurelien Jacquiot \u003ca-jacquiot@ti.com\u003e\nSigned-off-by: Mark Salter \u003cmsalter@redhat.com\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n" }, { "commit": "52679b2d735492bce02503bafb333da87fae22c2", "tree": "62675c1cf17721a70ffb39ffb186a9ef92f7d0f0", "parents": [ "64236ac1444eecca4b7b51270879d58bd291c8c2" ], "author": { "name": "Aurelien Jacquiot", "email": "a-jacquiot@ti.com", "time": "Tue Oct 04 11:13:21 2011 -0400" }, "committer": { "name": "Mark Salter", "email": "msalter@redhat.com", "time": "Thu Oct 06 19:48:17 2011 -0400" }, "message": "C6X: ptrace support\n\nOriginal port to early 2.6 kernel using TI COFF toolchain.\nBrought up to date by Mark Salter \u003cmsalter@redhat.com\u003e\n\nSigned-off-by: Aurelien Jacquiot \u003ca-jacquiot@ti.com\u003e\nSigned-off-by: Mark Salter \u003cmsalter@redhat.com\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n" }, { "commit": "64236ac1444eecca4b7b51270879d58bd291c8c2", "tree": "581a78b7095e2b86d32c5da0972eae766f64323f", "parents": [ "784bdcd0aa1d8ce38025bcfaa321146762738fe0" ], "author": { "name": "Aurelien Jacquiot", "email": "a-jacquiot@ti.com", "time": "Tue Oct 04 11:12:27 2011 -0400" }, "committer": { "name": "Mark Salter", "email": "msalter@redhat.com", "time": "Thu Oct 06 19:48:13 2011 -0400" }, "message": "C6X: loadable module support\n\nOriginal port to early 2.6 kernel using TI COFF toolchain.\nBrought up to date by Mark Salter \u003cmsalter@redhat.com\u003e\n\nSigned-off-by: Aurelien Jacquiot \u003ca-jacquiot@ti.com\u003e\nSigned-off-by: Mark Salter \u003cmsalter@redhat.com\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n" }, { "commit": "784bdcd0aa1d8ce38025bcfaa321146762738fe0", "tree": "1b1bda6b0c573d39aaa6615b6ec2dc9e206378ff", "parents": [ "81ec98898188639ac53413605681b3e3bb0a2ff1" ], "author": { "name": "Aurelien Jacquiot", "email": "a-jacquiot@ti.com", "time": "Tue Oct 04 11:11:35 2011 -0400" }, "committer": { "name": "Mark Salter", "email": "msalter@redhat.com", "time": "Thu Oct 06 19:48:10 2011 -0400" }, "message": "C6X: cache control\n\nOriginal port to early 2.6 kernel using TI COFF toolchain.\nBrought up to date by Mark Salter \u003cmsalter@redhat.com\u003e\n\nSigned-off-by: Aurelien Jacquiot \u003ca-jacquiot@ti.com\u003e\nSigned-off-by: Mark Salter \u003cmsalter@redhat.com\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n" }, { "commit": "81ec98898188639ac53413605681b3e3bb0a2ff1", "tree": "ba8a4c16120f0e9c2fd2fe5c9e5f7acc0a56e652", "parents": [ "e94e668251ab31b17ef6dcd16ba7fe05ffc1917a" ], "author": { "name": "Mark Salter", "email": "msalter@redhat.com", "time": "Tue Oct 04 11:10:50 2011 -0400" }, "committer": { "name": "Mark Salter", "email": "msalter@redhat.com", "time": "Thu Oct 06 19:48:07 2011 -0400" }, "message": "C6X: clocks\n\nThe C6X SoCs contain several PLL controllers each with up to 16 clock outputs\nfeeding into the cores or peripheral clock domains. The hardware is very similar\nto arm/mach-davinci clocks. This is still a work in progress which needs to be\nupdated once device tree clock binding changes shake out.\n\nSigned-off-by: Mark Salter \u003cmsalter@redhat.com\u003e\nSigned-off-by: Aurelien Jacquiot \u003ca-jacquiot@ti.com\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n" }, { "commit": "e94e668251ab31b17ef6dcd16ba7fe05ffc1917a", "tree": "b0024e31bb2a321ccea190d66be4d91f4bc39d29", "parents": [ "8a0c9e0348479f1b85c640da4795bdd775970bf3" ], "author": { "name": "Aurelien Jacquiot", "email": "a-jacquiot@ti.com", "time": "Tue Oct 04 11:10:02 2011 -0400" }, "committer": { "name": "Mark Salter", "email": "msalter@redhat.com", "time": "Thu Oct 06 19:48:02 2011 -0400" }, "message": "C6X: build infrastructure\n\nOriginal port to early 2.6 kernel using TI COFF toolchain.\nBrought up to date by Mark Salter \u003cmsalter@redhat.com\u003e\n\nSigned-off-by: Aurelien Jacquiot \u003ca-jacquiot@ti.com\u003e\nSigned-off-by: Mark Salter \u003cmsalter@redhat.com\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n" }, { "commit": "8a0c9e0348479f1b85c640da4795bdd775970bf3", "tree": "1d0f9b2d279b40d42ebd79fa1e99becaaa9f225e", "parents": [ "ec500af3059b474df35418c41c684c1cde830c81" ], "author": { "name": "Aurelien Jacquiot", "email": "a-jacquiot@ti.com", "time": "Tue Oct 04 12:21:06 2011 -0400" }, "committer": { "name": "Mark Salter", "email": "msalter@redhat.com", "time": "Thu Oct 06 19:47:58 2011 -0400" }, "message": "C6X: syscalls\n\nOriginal port to early 2.6 kernel using TI COFF toolchain.\nBrought up to date by Mark Salter \u003cmsalter@redhat.com\u003e\n\nSigned-off-by: Aurelien Jacquiot \u003ca-jacquiot@ti.com\u003e\nSigned-off-by: Mark Salter \u003cmsalter@redhat.com\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n[msalter@redhat.com: add include of linux/module.h to sys_c6x.c]\nSigned-off-by: Mark Salter \u003cmsalter@redhat.com\u003e\n" }, { "commit": "ec500af3059b474df35418c41c684c1cde830c81", "tree": "fca5ee52137efe4fc9d9c07ddce4f4e4ea52ba16", "parents": [ "546a39546c64ad7e73796c5508ef5487af42cae2" ], "author": { "name": "Aurelien Jacquiot", "email": "a-jacquiot@ti.com", "time": "Tue Oct 04 11:06:27 2011 -0400" }, "committer": { "name": "Mark Salter", "email": "msalter@redhat.com", "time": "Thu Oct 06 19:47:54 2011 -0400" }, "message": "C6X: interrupt handling\n\nOriginal port to early 2.6 kernel using TI COFF toolchain.\nBrought up to date by Mark Salter \u003cmsalter@redhat.com\u003e\n\nSigned-off-by: Aurelien Jacquiot \u003ca-jacquiot@ti.com\u003e\nSigned-off-by: Mark Salter \u003cmsalter@redhat.com\u003e\nReviewed-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n" }, { "commit": "546a39546c64ad7e73796c5508ef5487af42cae2", "tree": "9ab7fb5512ac1a99ab29267482469dcd8a8252ff", "parents": [ "03a347558749caaab482f34410ae5d27e893db89" ], "author": { "name": "Aurelien Jacquiot", "email": "a-jacquiot@ti.com", "time": "Tue Oct 04 11:05:33 2011 -0400" }, "committer": { "name": "Mark Salter", "email": "msalter@redhat.com", "time": "Thu Oct 06 19:47:51 2011 -0400" }, "message": "C6X: time management\n\nOriginal port to early 2.6 kernel using TI COFF toolchain.\nBrought up to date by Mark Salter \u003cmsalter@redhat.com\u003e\n\nSigned-off-by: Aurelien Jacquiot \u003ca-jacquiot@ti.com\u003e\nSigned-off-by: Mark Salter \u003cmsalter@redhat.com\u003e\nReviewed-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n" }, { "commit": "03a347558749caaab482f34410ae5d27e893db89", "tree": "4a6e2017f0afb5b82eb31d05ce2a2b539f453827", "parents": [ "687b12baecae2aa3af9df05c12b90d8e9ef21fa7" ], "author": { "name": "Aurelien Jacquiot", "email": "a-jacquiot@ti.com", "time": "Tue Oct 04 11:04:34 2011 -0400" }, "committer": { "name": "Mark Salter", "email": "msalter@redhat.com", "time": "Thu Oct 06 19:47:46 2011 -0400" }, "message": "C6X: signal management\n\nOriginal port to early 2.6 kernel using TI COFF toolchain.\nBrought up to date by Mark Salter \u003cmsalter@redhat.com\u003e\n\nSigned-off-by: Aurelien Jacquiot \u003ca-jacquiot@ti.com\u003e\nSigned-off-by: Mark Salter \u003cmsalter@redhat.com\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n" }, { "commit": "687b12baecae2aa3af9df05c12b90d8e9ef21fa7", "tree": "0d73b753a7dd541d987a06fd7b69d7958170a5dd", "parents": [ "14aa7e8bf6d84c9a42c48e7f93472d830f694b1e" ], "author": { "name": "Aurelien Jacquiot", "email": "a-jacquiot@ti.com", "time": "Tue Oct 04 11:03:44 2011 -0400" }, "committer": { "name": "Mark Salter", "email": "msalter@redhat.com", "time": "Thu Oct 06 19:47:40 2011 -0400" }, "message": "C6X: process management\n\nOriginal port to early 2.6 kernel using TI COFF toolchain.\nBrought up to date by Mark Salter \u003cmsalter@redhat.com\u003e\n\nSigned-off-by: Aurelien Jacquiot \u003ca-jacquiot@ti.com\u003e\nSigned-off-by: Mark Salter \u003cmsalter@redhat.com\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n" }, { "commit": "14aa7e8bf6d84c9a42c48e7f93472d830f694b1e", "tree": "6e7ee17817537ea8454d3e3793a37017139bfcf9", "parents": [ "041cadca7008f08fb4785f2288c8127c16faa529" ], "author": { "name": "Aurelien Jacquiot", "email": "a-jacquiot@ti.com", "time": "Tue Oct 04 12:17:19 2011 -0400" }, "committer": { "name": "Mark Salter", "email": "msalter@redhat.com", "time": "Thu Oct 06 19:47:37 2011 -0400" }, "message": "C6X: memory management and DMA support\n\nOriginal port to early 2.6 kernel using TI COFF toolchain.\nBrought up to date by Mark Salter \u003cmsalter@redhat.com\u003e\n\nThe C6X architecture currently lacks an MMU so memory management is relatively\nsimple. There is no bus snooping between L2 and main memory but coherent DMA\nmemory is supported by making regions of main memory uncached. If such a region\nis desired, it can be specified on the commandline with a \"memdma\u003d\" argument.\n\nSigned-off-by: Aurelien Jacquiot \u003ca-jacquiot@ti.com\u003e\nSigned-off-by: Mark Salter \u003cmsalter@redhat.com\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n" }, { "commit": "041cadca7008f08fb4785f2288c8127c16faa529", "tree": "19008ae2e32faf489f85e00838a571a5295c79f4", "parents": [ "c1a144d77a6ca3a14ba3c0fec30bc4fd20b3d817" ], "author": { "name": "Mark Salter", "email": "msalter@redhat.com", "time": "Tue Oct 04 12:12:20 2011 -0400" }, "committer": { "name": "Mark Salter", "email": "msalter@redhat.com", "time": "Thu Oct 06 19:47:33 2011 -0400" }, "message": "C6X: devicetree support\n\nThis is the basic devicetree support for C6X. Currently, four boards are\nsupported. Each one uses a different SoC part. Two of the four supported\nSoCs are multicore. One with 3 cores and the other with 6 cores. There is\nno coherency between the core-level caches, so SMP is not an option. It is\npossible to run separate kernel instances on the various cores. There is\ncurrently no C6X bootloader support for device trees so we build in the DTB\nfor now.\n\nThere are some interesting twists to the hardware which are of note for device\ntree support. Each core has its own interrupt controller which is controlled\nby special purpose core registers. This core controller provides 12 general\npurpose prioritized interrupt sources. Each core is contained within a\nhardware \"module\" which provides L1 and L2 caches, power control, and another\ninterrupt controller which cascades into the core interrupt controller. These\ncore module functions are controlled by memory mapped registers. The addresses\nfor these registers are the same for each core. That is, when coreN accesses\na module-level MMIO register at a given address, it accesses the register for\ncoreN even though other cores would use the same address to access the register\nin the module containing those cores. Other hardware modules (timers, enet, etc)\nwhich are memory mapped can be accessed by all cores.\n\nThe timers need some further explanation for multicore SoCs. Even though all\ntimer control registers are visible to all cores, interrupt routing or other\nconsiderations may make a given timer more suitable for use by a core than\nsome other timer. Because of this and the desire to have the same image run\non more than one core, the timer nodes have a \"ti,core-mask\" property which\nis used by the driver to scan for a suitable timer to use.\n\nSigned-off-by: Mark Salter \u003cmsalter@redhat.com\u003e\nSigned-off-by: Aurelien Jacquiot \u003ca-jacquiot@ti.com\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n" }, { "commit": "c1a144d77a6ca3a14ba3c0fec30bc4fd20b3d817", "tree": "e5a761211a22a90ca2eb1c933d2b3539c6888831", "parents": [ "c278400c52c14203894c5dc0d63cf385239d8329" ], "author": { "name": "Aurelien Jacquiot", "email": "a-jacquiot@ti.com", "time": "Tue Oct 04 11:00:02 2011 -0400" }, "committer": { "name": "Mark Salter", "email": "msalter@redhat.com", "time": "Thu Oct 06 19:47:28 2011 -0400" }, "message": "C6X: early boot code\n\nOriginal port to early 2.6 kernel using TI COFF toolchain.\nBrought up to date by Mark Salter \u003cmsalter@redhat.com\u003e\n\nThis patch provides the early boot code for C6X architecture. There is a\n16 entry vector table which is used to direct reset and interrupt events. The\nvector table entries contain a small amount of code (maximum of 8 opcodes)\nwhich simply branches to the actual event handling code.\n\nThe head.S code simply clears BSS, setups up a few control registers, and calls\nmachine_init followed by start_kernel. The machine_init code in setup.c does\nthe early flat tree parsing (memory, commandline, etc). At setup_arch time, the\ncode does the usual memory setup and minimally scans the devicetree for any\nneeded information.\n\nSigned-off-by: Aurelien Jacquiot \u003ca-jacquiot@ti.com\u003e\nSigned-off-by: Mark Salter \u003cmsalter@redhat.com\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n" }, { "commit": "c278400c52c14203894c5dc0d63cf385239d8329", "tree": "a3f82945b3ebb49b058e99cefdafca65732b041a", "parents": [ "e66d3c490c7a45daa49c1ae9cc5fe0687d14b823" ], "author": { "name": "Aurelien Jacquiot", "email": "a-jacquiot@ti.com", "time": "Tue Oct 04 10:54:51 2011 -0400" }, "committer": { "name": "Mark Salter", "email": "msalter@redhat.com", "time": "Thu Oct 06 19:47:25 2011 -0400" }, "message": "C6X: build infrastructure\n\nOriginal port to early 2.6 kernel using TI COFF toolchain.\nBrought up to date by Mark Salter \u003cmsalter@redhat.com\u003e\n\nSigned-off-by: Aurelien Jacquiot \u003ca-jacquiot@ti.com\u003e\nSigned-off-by: Mark Salter \u003cmsalter@redhat.com\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n" } ] }