)]}' { "log": [ { "commit": "5d7e8af3c5727626b9e7f909c778b9ac9b4a1809", "tree": "13d51e31ee070113538a6d26d9a52503ba4a3cd0", "parents": [ "aa891f6b3f440402c6879ad1ecf332d318137422", "79aa18d557bef02171da42ee928c23509e6ef4f7" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Jan 18 14:28:48 2011 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Tue Jan 18 14:28:48 2011 -0800" }, "message": "Merge branch \u0027upstream\u0027 of git://git.linux-mips.org/pub/scm/upstream-linus\n\n* \u0027upstream\u0027 of git://git.linux-mips.org/pub/scm/upstream-linus: (26 commits)\n MIPS: Malta: enable Cirrus FB console\n MIPS: add CONFIG_VIRTUALIZATION for virtio support\n MIPS: Implement __read_mostly\n MIPS: ath79: add common WMAC device for AR913X based boards\n MIPS: ath79: Add initial support for the Atheros AP81 reference board\n MIPS: ath79: add common SPI controller device\n SPI: Add SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs\n MIPS: ath79: add common GPIO buttons device\n MIPS: ath79: add common watchdog device\n MIPS: ath79: add common GPIO LEDs device\n MIPS: ath79: add initial support for the Atheros PB44 reference board\n MIPS: ath79: utilize the MIPS multi-machine support\n MIPS: ath79: add GPIOLIB support\n MIPS: Add initial support for the Atheros AR71XX/AR724X/AR931X SoCs\n MIPS: jump label: Add MIPS support.\n MIPS: Use WARN() in uasm for better diagnostics.\n MIPS: Optimize TLB handlers for Octeon CPUs\n MIPS: Add LDX and LWX instructions to uasm.\n MIPS: Use BBIT instructions in TLB handlers\n MIPS: Declare uasm bbit0 and bbit1 functions.\n ...\n" }, { "commit": "79aa18d557bef02171da42ee928c23509e6ef4f7", "tree": "a79d9d5be4a03b2c6051bc0dece1cc70e690aa83", "parents": [ "92e88b4e903dc6de7a82b76fd241e2ac6f87aa9e" ], "author": { "name": "Aurelien Jarno", "email": "aurelien@aurel32.net", "time": "Tue Jan 18 12:20:45 2011 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Jan 18 19:30:29 2011 +0100" }, "message": "MIPS: Malta: enable Cirrus FB console\n\nWhile most users of a physical Malta board are using the serial port\nas the console, a lot of QEMU users would prefer to interact with a\ngraphical console. Enable the Cirrus FB support in the Malta default\nconfiguration to make that possible. Note that the default console will\nstill be the serial port, users have to pass \"console\u003dtty0\" to the\nkernel to use the Cirrus FB.\n\nSigned-off-by: Aurelien Jarno \u003caurelien@aurel32.net\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/2001/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "92e88b4e903dc6de7a82b76fd241e2ac6f87aa9e", "tree": "56718f34ff36abcc7c9dccb2ba9af022d0f92e3a", "parents": [ "1befdd5536e1500371f7f884d0f0ae528a519333" ], "author": { "name": "Aurelien Jarno", "email": "aurelien@aurel32.net", "time": "Tue Jan 18 12:20:44 2011 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Jan 18 19:30:28 2011 +0100" }, "message": "MIPS: add CONFIG_VIRTUALIZATION for virtio support\n\nAdd CONFIG_VIRTUALIZATION to the MIPS architecture and include the\nthe virtio code there. Used to enable the virtio drivers under QEMU.\n\nSigned-off-by: Aurelien Jarno \u003caurelien@aurel32.net\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/2002/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "1befdd5536e1500371f7f884d0f0ae528a519333", "tree": "0c189a3c6686381f1393f9ea5cb161c36e08738f", "parents": [ "f5b35d0b16a08e6c1e7c8a41fa87ad10cf9aefa4" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Thu Oct 14 12:36:49 2010 -0700" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Jan 18 19:30:28 2011 +0100" }, "message": "MIPS: Implement __read_mostly\n\nJust do what everyone else is doing by placing __read_mostly things in\nthe .data.read_mostly section.\n\nmips_io_port_base can not be read-only (const) and writable\n(__read_mostly) at the same time. One of them has to go, so I chose\nto eliminate the __read_mostly. It will still get stuck in a portion\nof memory that is not adjacent to things that are written, and thus\nnot be on a dirty cache line, for whatever that is worth.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: http://patchwork.linux-mips.org/patch/1702/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "f5b35d0b16a08e6c1e7c8a41fa87ad10cf9aefa4", "tree": "fd4991f97b52aa714f5aebe955a2b897dbca0ecc", "parents": [ "aa6695ec8b51da7aaa245310073ddd39a306a77f" ], "author": { "name": "Gabor Juhos", "email": "juhosg@openwrt.org", "time": "Tue Jan 04 21:28:29 2011 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Jan 18 19:30:28 2011 +0100" }, "message": "MIPS: ath79: add common WMAC device for AR913X based boards\n\nAdd common platform_device and helper code to make the registration\nof the built-in wireless MAC easier on the Atheros AR9130/AR9132\nbased boards. Also register the WMAC device on the AR81 board.\n\nSigned-off-by: Gabor Juhos \u003cjuhosg@openwrt.org\u003e\nCc: linux-mips@linux-mips.org\nCc: Imre Kaloz \u003ckaloz@openwrt.org\u003e,\nCc: Luis R. Rodriguez \u003clrodriguez@atheros.com\u003e\nCc: Cliff Holden \u003cCliff.Holden@Atheros.com\u003e\nCc: Kathy Giori \u003cKathy.Giori@Atheros.com\u003e\nPatchwork: https://patchwork.linux-mips.org/patch/1962/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "aa6695ec8b51da7aaa245310073ddd39a306a77f", "tree": "760da11acabf41da8a66b8777788a58cbaf6d89c", "parents": [ "68a1d3163678a42ad2d0a9013672083c4fb613be" ], "author": { "name": "Gabor Juhos", "email": "juhosg@openwrt.org", "time": "Tue Jan 04 21:28:28 2011 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Jan 18 19:30:27 2011 +0100" }, "message": "MIPS: ath79: Add initial support for the Atheros AP81 reference board\n\nSigned-off-by: Gabor Juhos \u003cjuhosg@openwrt.org\u003e\nSigned-off-by: Imre Kaloz \u003ckaloz@openwrt.org\u003e\nCc: linux-mips@linux-mips.org\nCc: Luis R. Rodriguez \u003clrodriguez@atheros.com\u003e\nCc: Cliff Holden \u003cCliff.Holden@Atheros.com\u003e\nCc: Kathy Giori \u003cKathy.Giori@Atheros.com\u003e\nPatchwork: https://patchwork.linux-mips.org/patch/1952/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "68a1d3163678a42ad2d0a9013672083c4fb613be", "tree": "ac653355ea8030195c4edd606fa1b31c7f4a8a75", "parents": [ "8efaef4dc842a8a050d10aef30e26220b8995fc3" ], "author": { "name": "Gabor Juhos", "email": "juhosg@openwrt.org", "time": "Tue Jan 04 21:28:23 2011 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Jan 18 19:30:27 2011 +0100" }, "message": "MIPS: ath79: add common SPI controller device\n\nSeveral boards are using the built-in SPI controller of the\nAR71XX/AR724X/AR913X SoCs. This patch adds common platform_device\nand helper code to register it. Additionally, the patch registers\nthe SPI bus on the PB44 board.\n\nSigned-off-by: Gabor Juhos \u003cjuhosg@openwrt.org\u003e\nCc: linux-mips@linux-mips.org\nCc: Imre Kaloz \u003ckaloz@openwrt.org\u003e\nCc: Luis R. Rodriguez \u003clrodriguez@atheros.com\u003e\nCc: Cliff Holden \u003cCliff.Holden@Atheros.com\u003e\nCc: Kathy Giori \u003cKathy.Giori@Atheros.com\u003e\nPatchwork: https://patchwork.linux-mips.org/patch/1956/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "8efaef4dc842a8a050d10aef30e26220b8995fc3", "tree": "0ec022e5baa25f6397df0273bc8362aa6d85c8ea", "parents": [ "3f348c5d1aaa0b8b2563f50d2d9a0c64e7d649fb" ], "author": { "name": "Gabor Juhos", "email": "juhosg@openwrt.org", "time": "Tue Jan 04 21:28:22 2011 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Jan 18 19:30:27 2011 +0100" }, "message": "SPI: Add SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs\n\nThe Atheros AR71XX/AR724X/AR913X SoCs have a built-in SPI controller. This\npatch implements a driver for that.\n\nSigned-off-by: Gabor Juhos \u003cjuhosg@openwrt.org\u003e\nCc: David Brownell \u003cdbrownell@users.sourceforge.net\u003e\nCc: spi-devel-general@lists.sourceforge.net\nAcked-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\nCc: linux-mips@linux-mips.org\nCc: Imre Kaloz \u003ckaloz@openwrt.org\u003e\nCc: Luis R. Rodriguez \u003clrodriguez@atheros.com\u003e\nCc: Cliff Holden \u003cCliff.Holden@Atheros.com\u003e\nCc: Kathy Giori \u003cKathy.Giori@Atheros.com\u003e\nPatchwork: https://patchwork.linux-mips.org/patch/1960/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "3f348c5d1aaa0b8b2563f50d2d9a0c64e7d649fb", "tree": "cdd531781d22fe64c5c3cce0a56de153bf9cc397", "parents": [ "858f763c1cc37ecc6ab39dec60bb3a46606dcac4" ], "author": { "name": "Gabor Juhos", "email": "juhosg@openwrt.org", "time": "Tue Jan 04 21:28:21 2011 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Jan 18 19:30:27 2011 +0100" }, "message": "MIPS: ath79: add common GPIO buttons device\n\nAlmost all boards have one or more push buttons connected to GPIO lines.\nThis patch adds common code to register a platform_device for them.\n\nThe patch also adds support for the buttons on the PB44 board.\n\nSigned-off-by: Gabor Juhos \u003cjuhosg@openwrt.org\u003e\nSigned-off-by: Imre Kaloz \u003ckaloz@openwrt.org\u003e\nCc: linux-mips@linux-mips.org\nCc: Luis R. Rodriguez \u003clrodriguez@atheros.com\u003e\nCc: Cliff Holden \u003cCliff.Holden@Atheros.com\u003e\nCc: Kathy Giori \u003cKathy.Giori@Atheros.com\u003e\nPatchwork: https://patchwork.linux-mips.org/patch/1954/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "858f763c1cc37ecc6ab39dec60bb3a46606dcac4", "tree": "0b0d834212fa05e53de9988ba5ea83c224302a1f", "parents": [ "d8fec1fc80cd8639449e2b5012688f5be109eeaf" ], "author": { "name": "Gabor Juhos", "email": "juhosg@openwrt.org", "time": "Tue Jan 04 21:28:20 2011 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Jan 18 19:30:26 2011 +0100" }, "message": "MIPS: ath79: add common watchdog device\n\nAll supported SoCs have a built-in hardware watchdog driver. This patch\nregisters a platform_device for that to make it usable.\n\nSigned-off-by: Gabor Juhos \u003cjuhosg@openwrt.org\u003e\nSigned-off-by: Imre Kaloz \u003ckaloz@openwrt.org\u003e\nCc: linux-mips@linux-mips.org\nCc: Luis R. Rodriguez \u003clrodriguez@atheros.com\u003e\nCc: Cliff Holden \u003cCliff.Holden@Atheros.com\u003e\nCc: Kathy Giori \u003cKathy.Giori@Atheros.com\u003e\nPatchwork: https://patchwork.linux-mips.org/patch/1955/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "d8fec1fc80cd8639449e2b5012688f5be109eeaf", "tree": "57882250166f98d561b126bf664f5abaef3a0a22", "parents": [ "0cde72284c9c7d4b348ece9e1fe136f787185cd7" ], "author": { "name": "Gabor Juhos", "email": "juhosg@openwrt.org", "time": "Tue Jan 04 21:28:18 2011 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Jan 18 19:30:26 2011 +0100" }, "message": "MIPS: ath79: add common GPIO LEDs device\n\nAlmost all boards have one or more LEDs connected to GPIO lines. This\npatch adds common code to register a platform_device for them.\n\nThe patch also adds support for the LEDs on the PB44 board.\n\nSigned-off-by: Gabor Juhos \u003cjuhosg@openwrt.org\u003e\nSigned-off-by: Imre Kaloz \u003ckaloz@openwrt.org\u003e\nCc: linux-mips@linux-mips.org\nCc: Luis R. Rodriguez \u003clrodriguez@atheros.com\u003e\nCc: Cliff Holden \u003cCliff.Holden@Atheros.com\u003e\nCc: Kathy Giori \u003cKathy.Giori@Atheros.com\u003e\nPatchwork: https://patchwork.linux-mips.org/patch/1953/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "0cde72284c9c7d4b348ece9e1fe136f787185cd7", "tree": "af4131bf897fc1daeb6e711e3f0c417c53d52c08", "parents": [ "0aabf1a4d9b6b2d2371f641ec19fb7551cea4a90" ], "author": { "name": "Gabor Juhos", "email": "juhosg@openwrt.org", "time": "Tue Jan 04 21:28:17 2011 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Jan 18 19:30:26 2011 +0100" }, "message": "MIPS: ath79: add initial support for the Atheros PB44 reference board\n\nSigned-off-by: Gabor Juhos \u003cjuhosg@openwrt.org\u003e\nCc: Imre Kaloz \u003ckaloz@openwrt.org\u003e\nCc: linux-mips@linux-mips.org\nCc: Luis R. Rodriguez \u003clrodriguez@atheros.com\u003e\nCc: Cliff Holden \u003cCliff.Holden@Atheros.com\u003e\nCc: Kathy Giori \u003cKathy.Giori@Atheros.com\u003e\nPatchwork: https://patchwork.linux-mips.org/patch/1950/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "0aabf1a4d9b6b2d2371f641ec19fb7551cea4a90", "tree": "9bb5ece8310ce78c19652058f5a00816e6fc5d2d", "parents": [ "6eae43c57ee92de91f6cc7c391cea97c43295da0" ], "author": { "name": "Gabor Juhos", "email": "juhosg@openwrt.org", "time": "Tue Jan 04 21:28:16 2011 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Jan 18 19:30:25 2011 +0100" }, "message": "MIPS: ath79: utilize the MIPS multi-machine support\n\nSigned-off-by: Gabor Juhos \u003cjuhosg@openwrt.org\u003e\nCc: Imre Kaloz \u003ckaloz@openwrt.org\u003e\nCc: linux-mips@linux-mips.org\nCc: Luis R. Rodriguez \u003clrodriguez@atheros.com\u003e\nCc: Cliff Holden \u003cCliff.Holden@Atheros.com\u003e\nCc: Kathy Giori \u003cKathy.Giori@Atheros.com\u003e\nPatchwork: https://patchwork.linux-mips.org/patch/1949/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "6eae43c57ee92de91f6cc7c391cea97c43295da0", "tree": "5ac5521d28527e6218faea0f31cc888df65dbc9f", "parents": [ "d4a67d9dc8a5a80c4ec1814791af8c0252c158b8" ], "author": { "name": "Gabor Juhos", "email": "juhosg@openwrt.org", "time": "Tue Jan 04 21:28:15 2011 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Jan 18 19:30:25 2011 +0100" }, "message": "MIPS: ath79: add GPIOLIB support\n\nThis patch implements generic GPIO routines for the built-in\nGPIO controllers of the Atheros AR71XX/AR724X/AR913X SoCs.\n\nSigned-off-by: Gabor Juhos \u003cjuhosg@openwrt.org\u003e\nSigned-off-by: Imre Kaloz \u003ckaloz@openwrt.org\u003e\nCc: David Brownell \u003cdbrownell@users.sourceforge.net\u003e\nCc: linux-mips@linux-mips.org\nCc: Luis R. Rodriguez \u003clrodriguez@atheros.com\u003e\nCc: Cliff Holden \u003cCliff.Holden@Atheros.com\u003e\nCc: Kathy Giori \u003cKathy.Giori@Atheros.com\u003e\nPatchwork: https://patchwork.linux-mips.org/patch/1948/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "d4a67d9dc8a5a80c4ec1814791af8c0252c158b8", "tree": "28c9797f2ec5bf46325e1d5dd7db675ac0ac6713", "parents": [ "94bb0c1ab293c298a8852e4f10c4215bad6daa9b" ], "author": { "name": "Gabor Juhos", "email": "juhosg@openwrt.org", "time": "Tue Jan 04 21:28:14 2011 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Jan 18 19:30:24 2011 +0100" }, "message": "MIPS: Add initial support for the Atheros AR71XX/AR724X/AR931X SoCs\n\nThis patch adds initial support for various Atheros SoCs based on the\nMIPS 24Kc core. The following models are supported at the moment:\n\n - AR7130\n - AR7141\n - AR7161\n - AR9130\n - AR9132\n - AR7240\n - AR7241\n - AR7242\n\nThe current patch contains minimal support only, but the resulting\nkernel can boot into user-space with using of an initramfs image on\nvarious boards which are using these SoCs. Support for more built-in\ndevices and individual boards will be implemented in further patches.\n\nSigned-off-by: Gabor Juhos \u003cjuhosg@openwrt.org\u003e\nSigned-off-by: Imre Kaloz \u003ckaloz@openwrt.org\u003e\nCc: linux-mips@linux-mips.org\nCc: Luis R. Rodriguez \u003clrodriguez@atheros.com\u003e\nCc: Cliff Holden \u003cCliff.Holden@Atheros.com\u003e\nCc: Kathy Giori \u003cKathy.Giori@Atheros.com\u003e\nPatchwork: https://patchwork.linux-mips.org/patch/1947/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "94bb0c1ab293c298a8852e4f10c4215bad6daa9b", "tree": "e4e7dfa18bf2ffd832a97d7ab67863b1b363c6fe", "parents": [ "8d662c8d34a05e8e47deaa9e22fe770dc557c2d3" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Tue Dec 28 13:26:23 2010 -0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Jan 18 19:30:24 2011 +0100" }, "message": "MIPS: jump label: Add MIPS support.\n\nIn order not to be left behind, we add jump label support for MIPS.\n\nTested on 64-bit big endian (Octeon), and 32-bit little endian\n(malta/qemu).\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nTo: linux-mips@linux-mips.org\nCc: Steven Rostedt \u003crostedt@goodmis.org\u003e\nCc: Jason Baron \u003cjbaron@redhat.com\u003e\nPatchwork: https://patchwork.linux-mips.org/patch/1923/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "8d662c8d34a05e8e47deaa9e22fe770dc557c2d3", "tree": "96f8ee1bcbda6aded36a9f551f4df8179e33782c", "parents": [ "2c8c53e28f178577dfdf3a69731b998b7e3df8ae" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Mon Dec 27 18:18:29 2010 -0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Jan 18 19:30:24 2011 +0100" }, "message": "MIPS: Use WARN() in uasm for better diagnostics.\n\nOn the off chance that uasm ever warns about overflow, there is no way\nto know what the offending instruction is.\n\nChange the printks to WARNs, so we can get a nice stack trace. It has\nthe added benefit of being much more noticeable than the short single\nline warning message, so is less likely to be ignored.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/1905/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "2c8c53e28f178577dfdf3a69731b998b7e3df8ae", "tree": "0b65ff7fa0ac67795698be7a50559d77d3bc72db", "parents": [ "bb3d68c30a00918d4c9fa02a5c17a5aacf597977" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Mon Dec 27 18:07:57 2010 -0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Jan 18 19:30:23 2011 +0100" }, "message": "MIPS: Optimize TLB handlers for Octeon CPUs\n\nOcteon can use scratch registers in the TLB handlers. Octeon II can\nuse LDX instructions.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/1904/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "bb3d68c30a00918d4c9fa02a5c17a5aacf597977", "tree": "6d6db066452de4a2ec28f24bc7b0c287eabd9967", "parents": [ "cc33ae437975416a1b78f99e2715e91ab643526a" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Mon Dec 27 18:07:56 2010 -0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Jan 18 19:30:23 2011 +0100" }, "message": "MIPS: Add LDX and LWX instructions to uasm.\n\nNeeded by Octeon II optimized TLB handlers.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nTo: linux-mips@linux-mips.org\nPachwork: https://patchwork.linux-mips.org/patch/1903/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "cc33ae437975416a1b78f99e2715e91ab643526a", "tree": "958e4165ddcd45bf6ba9c498fa8f736dcbcbe770", "parents": [ "afc7c9864a2d1b0c398425aac84b8a095c8dfa7c" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Mon Dec 20 15:54:50 2010 -0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Jan 18 19:30:23 2011 +0100" }, "message": "MIPS: Use BBIT instructions in TLB handlers\n\nIf the CPU supports BBIT0 and BBIT1, use them in TLB handlers as they\nare more efficient than an AND followed by an branch and then\nrestoring the clobbered register.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/1873/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "afc7c9864a2d1b0c398425aac84b8a095c8dfa7c", "tree": "172187ab42563fa097809b46a3470d901c8e3fb4", "parents": [ "3d8bfdd0307223de678962f1c1907a7cec549136" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Mon Dec 20 15:54:49 2010 -0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Jan 18 19:30:22 2011 +0100" }, "message": "MIPS: Declare uasm bbit0 and bbit1 functions.\n\nthese are already defined, but declaring them allow them to be used\noutside of uasm.c.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/1872/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "3d8bfdd0307223de678962f1c1907a7cec549136", "tree": "007146d1452d054e5e676b5a930d48292b0ae4b6", "parents": [ "c42aef0947d717849f31965ecc0778707839bfe0" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Tue Dec 21 14:19:11 2010 -0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Jan 18 19:30:22 2011 +0100" }, "message": "MIPS: Use C0_KScratch (if present) to hold PGD pointer.\n\nDecide at runtime to use either Context or KScratch to hold the PGD\npointer.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/1876/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "c42aef0947d717849f31965ecc0778707839bfe0", "tree": "7ce30dcb07e85b2af44045bb9be3e4da99074ae8", "parents": [ "e77c32fe284a4da1b4e0994890a4d3527812eb61" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Tue Dec 21 14:19:10 2010 -0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Jan 18 19:30:22 2011 +0100" }, "message": "MIPS: Add DINSM to uasm.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/1875/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "e77c32fe284a4da1b4e0994890a4d3527812eb61", "tree": "8bff97f0aeb8ce4ba0bf4af92f798e06b66f6e9f", "parents": [ "487d70d0b8bd1c70d099a7526077ffefee412050" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Tue Dec 21 14:19:09 2010 -0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Jan 18 19:30:22 2011 +0100" }, "message": "MIPS: Probe for presence of KScratch registers.\n\nProbe c0_config4 for KScratch registers and report them in /proc/cpuinfo.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/1877/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "487d70d0b8bd1c70d099a7526077ffefee412050", "tree": "e8ea4a5830fa88dca0a903b6bdf1f14e3ee119eb", "parents": [ "0bec405e8ee390067e63265b3002aaac49d4eea8" ], "author": { "name": "Gabor Juhos", "email": "juhosg@openwrt.org", "time": "Tue Nov 23 16:06:25 2010 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Jan 18 19:30:21 2011 +0100" }, "message": "MIPS: Add generic support for multiple machines within a single kernel\n\nThis patch adds a generic solution to support multiple machines based on\na given SoC within a single kernel image. It is implemented already for\nseveral other architectures but MIPS has no generic support for that yet.\n\n[Ralf: This competes with DT but DT is a much more complex solution and this\ncode has been used by OpenWRT for a long time so for now DT is a bad reason\nto stop the merge but longer term this should be migrated to DT.]\n\nSigned-off-by: Gabor Juhos \u003cjuhosg@openwrt.org\u003e\nCc: linux-mips@linux-mips.org\nCc: kaloz@openwrt.org\nCc: Luis R. Rodriguez \u003clrodriguez@atheros.com\u003e\nCc: Cliff Holden \u003cCliff.Holden@Atheros.com\u003e\nPatchwork: https://patchwork.linux-mips.org/patch/1814/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "0bec405e8ee390067e63265b3002aaac49d4eea8", "tree": "4f556448cd28294d736e65ac00ef5d6e22a00310", "parents": [ "a1181caac965c660be2bd350a9deb763e6f4b738" ], "author": { "name": "Joe Perches", "email": "joe@perches.com", "time": "Fri Nov 12 13:37:52 2010 -0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Jan 18 19:30:21 2011 +0100" }, "message": "MIPS: Use printf extension %pR for struct resource\n\nUsing %pR standardizes the struct resource output.\n\nSigned-off-by: Joe Perches \u003cjoe@perches.com\u003e\nTo: Jiri Kosina \u003ctrivial@kernel.org\u003e\nCc: linux-mips@linux-mips.org\nCc: linux-kernel@vger.kernel.org\nPatchwork: https://patchwork.linux-mips.org/patch/1772/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "a1181caac965c660be2bd350a9deb763e6f4b738", "tree": "bd6ff9ba19cfbc46faa80b96ae7a7b6300cfb8f5", "parents": [ "1b59be2a6cdcb5a12e18d8315c07c94a624de48f" ], "author": { "name": "Joe Perches", "email": "joe@perches.com", "time": "Thu Nov 04 20:07:26 2010 -0700" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Jan 18 19:30:21 2011 +0100" }, "message": "MIPS: Sibyte: Use vzalloc in sbbus profiler\n\nSigned-off-by: Joe Perches \u003cjoe@perches.com\u003e\nTo: Jiri Kosina \u003ctrivial@kernel.org\u003e\nCc: linux-mips@linux-mips.org\nCc: linux-kernel@vger.kernel.org\nPatchwork: https://patchwork.linux-mips.org/patch/1756/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "672c54466d24994eb9633f993862c89539504a42", "tree": "e08f17e5fa260676912eb9b7d2263d47d667fdec", "parents": [ "1b59be2a6cdcb5a12e18d8315c07c94a624de48f" ], "author": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Thu Jan 13 15:36:09 2011 -0700" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Sat Jan 15 22:01:58 2011 -0700" }, "message": "dt/flattree: Return virtual address from early_init_dt_alloc_memory_arch()\n\nThe physical address is never used by the device tree code when\nallocating memory for unflattening. Change the architecture\u0027s alloc\nhook to return the virutal address instead.\n\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n" }, { "commit": "1ddd6db43a08cba56c7ee920800980862086f1c3", "tree": "696b6d3c44832b08a55de8724b8539dacd96bd4c", "parents": [ "37c2ac7872a9387542616f658d20ac25f5bdb32e" ], "author": { "name": "Andrea Arcangeli", "email": "aarcange@redhat.com", "time": "Thu Jan 13 15:47:17 2011 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Jan 13 17:32:47 2011 -0800" }, "message": "thp: mm: define MADV_NOHUGEPAGE\n\nDefine MADV_NOHUGEPAGE.\n\nSigned-off-by: Andrea Arcangeli \u003caarcange@redhat.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "a826e422420b461a6247137c292ff83c4800354a", "tree": "803e3aeb39606e2fe58daa238c454b335aa25cbc", "parents": [ "1c9bf22c09ae14d65225d9b9619b2eb357350cd7" ], "author": { "name": "Andrea Arcangeli", "email": "aarcange@redhat.com", "time": "Thu Jan 13 15:46:31 2011 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Jan 13 17:32:38 2011 -0800" }, "message": "thp: mm: define MADV_HUGEPAGE\n\nDefine MADV_HUGEPAGE.\n\nSigned-off-by: Andrea Arcangeli \u003caarcange@redhat.com\u003e\nAcked-by: Rik van Riel \u003criel@redhat.com\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\nAcked-by: Mel Gorman \u003cmel@csn.ul.ie\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "d0a21265dfb5fa8ae54e90d0fb6d1c215b10a28a", "tree": "a3bf2c96ad8e180f32a52e208667a40bb972275b", "parents": [ "ec3f64fc9c196a304c4b7db3e1ff56d640628509" ], "author": { "name": "David Rientjes", "email": "rientjes@google.com", "time": "Thu Jan 13 15:46:02 2011 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Jan 13 17:32:34 2011 -0800" }, "message": "mm: unify module_alloc code for vmalloc\n\nFour architectures (arm, mips, sparc, x86) use __vmalloc_area() for\nmodule_init(). Much of the code is duplicated and can be generalized in a\nglobally accessible function, __vmalloc_node_range().\n\n__vmalloc_node() now calls into __vmalloc_node_range() with a range of\n[VMALLOC_START, VMALLOC_END) for functionally equivalent behavior.\n\nEach architecture may then use __vmalloc_node_range() directly to remove\nthe duplication of code.\n\nSigned-off-by: David Rientjes \u003crientjes@google.com\u003e\nCc: Christoph Lameter \u003ccl@linux.com\u003e\nCc: Russell King \u003clinux@arm.linux.org.uk\u003e\nCc: Ralf Baechle \u003cralf@linux-mips.org\u003e\nCc: \"David S. Miller\" \u003cdavem@davemloft.net\u003e\nCc: Ingo Molnar \u003cmingo@redhat.com\u003e\nCc: \"H. Peter Anvin\" \u003chpa@zytor.com\u003e\nCc: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "008d23e4852d78bb2618f2035f8b2110b6a6b968", "tree": "81c88f744f6f3fc84132527c1ddc0b4da410c5e2", "parents": [ "8f685fbda43deccd130d192c9fcef1444649eaca", "bfc672dcf323877228682aff79dff8ecd9f30ff8" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Jan 13 10:05:56 2011 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Jan 13 10:05:56 2011 -0800" }, "message": "Merge branch \u0027for-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial\n\n* \u0027for-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: (43 commits)\n Documentation/trace/events.txt: Remove obsolete sched_signal_send.\n writeback: fix global_dirty_limits comment runtime -\u003e real-time\n ppc: fix comment typo singal -\u003e signal\n drivers: fix comment typo diable -\u003e disable.\n m68k: fix comment typo diable -\u003e disable.\n wireless: comment typo fix diable -\u003e disable.\n media: comment typo fix diable -\u003e disable.\n remove doc for obsolete dynamic-printk kernel-parameter\n remove extraneous \u0027is\u0027 from Documentation/iostats.txt\n Fix spelling milisec -\u003e ms in snd_ps3 module parameter description\n Fix spelling mistakes in comments\n Revert conflicting V4L changes\n i7core_edac: fix typos in comments\n mm/rmap.c: fix comment\n sound, ca0106: Fix assignment to \u0027channel\u0027.\n hrtimer: fix a typo in comment\n init/Kconfig: fix typo\n anon_inodes: fix wrong function name in comment\n fix comment typos concerning \"consistent\"\n poll: fix a typo in comment\n ...\n\nFix up trivial conflicts in:\n - drivers/net/wireless/iwlwifi/iwl-core.c (moved to iwl-legacy.c)\n - fs/ext4/ext4.h\n\nAlso fix missed \u0027diabled\u0027 typo in drivers/net/bnx2x/bnx2x.h while at it.\n" }, { "commit": "3e5c12409c54c30f1d1b16bba5d4d24e35aa283c", "tree": "1582983eda70a025eabe6c459a5ee8d1d94a5e16", "parents": [ "04c6862c055fb687c90d9652f32c11a063df15cf" ], "author": { "name": "Stephen Hemminger", "email": "shemminger@vyatta.com", "time": "Wed Jan 12 16:59:31 2011 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Thu Jan 13 08:03:07 2011 -0800" }, "message": "set_rtc_mmss: show warning message only once\n\nOccasionally the system gets into a state where the CMOS clock has gotten\nslightly ahead of current time and the periodic update of RTC fails. The\nmessage is a nuisance and repeats spamming the log.\n\n See: http://www.ntp.org/ntpfaq/NTP-s-trbl-spec.htm#Q-LINUX-SET-RTC-MMSS\n\nRather than just removing the message, make it show only once and reduce\nseverity since it indicates a normal and non urgent condition.\n\nSigned-off-by: Stephen Hemminger \u003cshemminger@vyatta.com\u003e\nCc: Richard Henderson \u003crth@twiddle.net\u003e\nCc: Ivan Kokshaysky \u003cink@jurassic.park.msu.ru\u003e\nCc: Matt Turner \u003cmattst88@gmail.com\u003e\nCc: Ralf Baechle \u003cralf@linux-mips.org\u003e\nCc: David Howells \u003cdhowells@redhat.com\u003e\nCc: Paul Mundt \u003clethal@linux-sh.org\u003e\nCc: Ingo Molnar \u003cmingo@elte.hu\u003e\nCc: \"H. Peter Anvin\" \u003chpa@zytor.com\u003e\nCc: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "0bd2cbcdfaff9cb22267d66fc843fa4f73f0c281", "tree": "7d9732bcf5f2f646cb0c2c529c48b454b15d4ae2", "parents": [ "57cc7215b70856dc6bae8e55b00ecd7b1d7429b1", "a081748735c5feb96b1365e78a5ff0fb6ca7e3a4" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Jan 10 08:57:03 2011 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Jan 10 08:57:03 2011 -0800" }, "message": "Merge branch \u0027next-devicetree\u0027 of git://git.secretlab.ca/git/linux-2.6\n\n* \u0027next-devicetree\u0027 of git://git.secretlab.ca/git/linux-2.6: (29 commits)\n of/flattree: forward declare struct device_node in of_fdt.h\n ipmi: explicitly include of_address.h and of_irq.h\n sparc: explicitly cast negative phandle checks to s32\n powerpc/405: Fix missing #{address,size}-cells in i2c node\n powerpc/5200: dts: refactor dts files\n powerpc/5200: dts: Change combatible strings on localbus\n powerpc/5200: dts: remove unused properties\n powerpc/5200: dts: rename nodes to prepare for refactoring dts files\n of/flattree: Update dtc to current mainline.\n of/device: Don\u0027t register disabled devices\n powerpc/dts: fix syntax bugs in bluestone.dts\n of: Fixes for OF probing on little endian systems\n of: make drivers depend on CONFIG_OF instead of CONFIG_PPC_OF\n of/flattree: Add of_flat_dt_match() helper function\n of_serial: explicitly include of_irq.h\n of/flattree: Refactor unflatten_device_tree and add fdt_unflatten_tree\n of/flattree: Reorder unflatten_dt_node\n of/flattree: Refactor unflatten_dt_node\n of/flattree: Add non-boottime device tree functions\n of/flattree: Add Kconfig for EARLY_FLATTREE\n ...\n\nFix up trivial conflict in arch/sparc/prom/tree_32.c as per Grant.\n" }, { "commit": "56b85f32d530d09d6805488ad00775d4e0e3baab", "tree": "e7fbe69e338ef775d3b2dd822aa915d259b4bc94", "parents": [ "3e5b08cbbf78bedd316904ab0cf3b27119433ee5", "568389c257fa7d74ce36c2f78bad31965fded4cf" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Jan 07 14:39:20 2011 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Jan 07 14:39:20 2011 -0800" }, "message": "Merge branch \u0027tty-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty-2.6\n\n* \u0027tty-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty-2.6: (36 commits)\n serial: apbuart: Fixup apbuart_console_init()\n TTY: Add tty ioctl to figure device node of the system console.\n tty: add \u0027active\u0027 sysfs attribute to tty0 and console device\n drivers: serial: apbuart: Handle OF failures gracefully\n Serial: Avoid unbalanced IRQ wake disable during resume\n tty: fix typos/errors in tty_driver.h comments\n pch_uart : fix warnings for 64bit compile\n 8250: fix uninitialized FIFOs\n ip2: fix compiler warning on ip2main_pci_tbl\n specialix: fix compiler warning on specialix_pci_tbl\n rocket: fix compiler warning on rocket_pci_ids\n 8250: add a UPIO_DWAPB32 for 32 bit accesses\n 8250: use container_of() instead of casting\n serial: omap-serial: Add support for kernel debugger\n serial: fix pch_uart kconfig \u0026 build\n drivers: char: hvc: add arm JTAG DCC console support\n RS485 documentation: add 16C950 UART description\n serial: ifx6x60: fix memory leak\n serial: ifx6x60: free IRQ on error\n Serial: EG20T: add PCH_UART driver\n ...\n\nFixed up conflicts in drivers/serial/apbuart.c with evil merge that\nmakes the code look fairly sane (unlike either side).\n" }, { "commit": "e6ce1324e4f08b0d984340201a125806dae0e9a6", "tree": "fe7e203f2e5d73b555a6fcb713948cf4fe5f7715", "parents": [ "55271024a735d0c3234e6ca7e0914b05aab7fbac" ], "author": { "name": "Stephen Neuendorffer", "email": "stephen.neuendorffer@xilinx.com", "time": "Thu Nov 18 15:54:56 2010 -0800" }, "committer": { "name": "Grant Likely", "email": "grant.likely@secretlab.ca", "time": "Wed Dec 29 16:08:18 2010 -0700" }, "message": "of/flattree: Add Kconfig for EARLY_FLATTREE\n\nThe device tree code is now in two pieces: some which can be used generically\non any platform which selects CONFIG_OF_FLATTREE, and some early which is used\nat boot time on only a few architectures. This patch segregates the early\ncode so that only those architectures which care about it need compile it.\nThis also means that some of the requirements in the early code (such as\na cmd_line variable) that most architectures (e.g. X86) don\u0027t provide\ncan be ignored.\n\nSigned-off-by: Stephen Neuendorffer \u003cstephen.neuendorffer@xilinx.com\u003e\n[grant.likely@secretlab.ca: remove extra blank line addition]\n[grant.likely@secretlab.ca: fixed incorrect #ifdef CONFIG_EARLY_FLATTREE check]\n[grant.likely@secretlab.ca: Made OF_EARLY_FLATTREE select instead of depend\n on OF_FLATTREE]\nSigned-off-by: Grant Likely \u003cgrant.likely@secretlab.ca\u003e\n" }, { "commit": "4b7bd364700d9ac8372eff48832062b936d0793b", "tree": "0dbf78c95456a0b02d07fcd473281f04a87e266d", "parents": [ "c0d8768af260e2cbb4bf659ae6094a262c86b085", "90a8a73c06cc32b609a880d48449d7083327e11a" ], "author": { "name": "Jiri Kosina", "email": "jkosina@suse.cz", "time": "Wed Dec 22 18:57:02 2010 +0100" }, "committer": { "name": "Jiri Kosina", "email": "jkosina@suse.cz", "time": "Wed Dec 22 18:57:02 2010 +0100" }, "message": "Merge branch \u0027master\u0027 into for-next\n\nConflicts:\n\tMAINTAINERS\n\tarch/arm/mach-omap2/pm24xx.c\n\tdrivers/scsi/bfa/bfa_fcpim.c\n\nNeeded to update to apply fixes for which the old branch was too\noutdated.\n" }, { "commit": "6c529a266bdc590a870ee2d2092ff6527eff427b", "tree": "7be65fa2578820a1258b5a1e8e063a509a5d6176", "parents": [ "7639dae0ca11038286bbbcda05f2bef601c1eb8d", "90a8a73c06cc32b609a880d48449d7083327e11a" ], "author": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Wed Dec 22 11:53:20 2010 +0100" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Wed Dec 22 11:53:23 2010 +0100" }, "message": "Merge commit \u0027v2.6.37-rc7\u0027 into perf/core\n\nMerge reason: Pick up the latest -rc.\n\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "081d835fa4ce70ad1e42ac76de850a49e23a1557", "tree": "8d76d9a5276d3eb8f6fc4a0ab3555f3234a48022", "parents": [ "c15524a40a1603dc56a8691c4f50172fb86c23d8" ], "author": { "name": "Kevin Cernekee", "email": "cernekee@gmail.com", "time": "Tue Nov 02 22:28:01 2010 -0700" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Dec 17 19:44:35 2010 +0000" }, "message": "MIPS: Fix build errors in sc-mips.c\n\nSeen with malta_defconfig on Linus\u0027 tree:\n\n CC arch/mips/mm/sc-mips.o\narch/mips/mm/sc-mips.c: In function \u0027mips_sc_is_activated\u0027:\narch/mips/mm/sc-mips.c:77: error: \u0027config2\u0027 undeclared (first use in this function)\narch/mips/mm/sc-mips.c:77: error: (Each undeclared identifier is reported only once\narch/mips/mm/sc-mips.c:77: error: for each function it appears in.)\narch/mips/mm/sc-mips.c:81: error: \u0027tmp\u0027 undeclared (first use in this function)\nmake[2]: *** [arch/mips/mm/sc-mips.o] Error 1\nmake[1]: *** [arch/mips/mm] Error 2\nmake: *** [arch/mips] Error 2\n\n[Ralf: Cosmetic changes to minimize the number of arguments passed to\nmips_sc_is_activated]\n\nSigned-off-by: Kevin Cernekee \u003ccernekee@gmail.com\u003e\nPatchwork: https://patchwork.linux-mips.org/patch/1752/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "b7b8de087384cc1954a8cd075af3f9e5977caa2e", "tree": "e362fe2c886c610caa9bd45fead9c4ae4789529e", "parents": [ "fbc92a3455577ab17615cbcb91826399061bd789" ], "author": { "name": "Werner Fink", "email": "werner@suse.de", "time": "Fri Dec 03 12:48:23 2010 +0100" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Thu Dec 16 16:18:28 2010 -0800" }, "message": "TTY: Add tty ioctl to figure device node of the system console.\n\nThis has been in the SuSE kernels for a very long time.\n\nSigned-off-by: Werner Fink \u003cwerner@suse.de\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n" }, { "commit": "c9bace7ca1e2aeb95754ebc92c8f88a9f215691d", "tree": "a42a86dee05efba73770434d5020abaae7750a72", "parents": [ "82b89152f00f7ad17844d5614d5011e8d7944ac9" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Mon Oct 11 14:52:45 2010 -0700" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 16 18:11:02 2010 +0000" }, "message": "MIPS: Add a CONFIG_FORCE_MAX_ZONEORDER Kconfig option.\n\nFor huge page support with base page size of 16K or 32K, we have to\nincrease the MAX_ORDER so that huge pages can be allocated.\n\n[Ralf: I don\u0027t think a user should have to configure obscure constants like\nthis but for the time being this will have to suffice.]\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/1685/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "82b89152f00f7ad17844d5614d5011e8d7944ac9", "tree": "227e754f4d3bdc62225eb2d918db382b6135d77f", "parents": [ "cf745a39dcb10ef80c4a2ff38448f57b69d4c4eb" ], "author": { "name": "Maciej W. Rozycki", "email": "macro@linux-mips.org", "time": "Sun Oct 10 10:42:12 2010 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 16 18:11:01 2010 +0000" }, "message": "MIPS: LD/SD o32 macro GAS fix update\n\nI am about to commit:\n\nhttp://sourceware.org/ml/binutils/2010-10/msg00033.html\n\nthat fixes a problem with the LD/SD macro currently implemented by GAS for\nthe o32 ABI in an inconsistent way. This is best illustrated with a\nsimple program, which I\u0027m copying here from the message above for easier\nreference:\n\n$ cat ld.s\n\tld\t$5,32767($4)\n\tld\t$5,32768($4)\n\nThis gets assebled into the following output:\n\n$ mips-linux-as -32 -mips3 -o ld.o ld.s\n$ mips-linux-objdump -d ld.o\n\nld.o: file format elf32-tradbigmips\n\nDisassembly of section .text:\n\n00000000 \u003c.text\u003e:\n 0:\tdc857fff \tld\ta1,32767(a0)\n 4:\t3c010001 \tlui\tat,0x1\n 8:\t00810821 \taddu\tat,a0,at\n c:\t8c258000 \tlw\ta1,-32768(at)\n 10:\t8c268004 \tlw\ta2,-32764(at)\n\t...\n\nOops!\n\n The GAS fix makes the macro behave in a consistent way and pairs of LW/SW\ninstructions to be output as appropriate regardless of the size of the\noffset associated with the address used. The machine instruction is still\navailable, but to reach it macros have to be disabled first. This has a\nside effect of requiring the use of a machine-addressable memory operand.\n\n As some platforms require 64-bit operations for accesses to some I/O\nregisters LD/SD instructions are used in a couple of places in Linux\nregardless of the ABI selected. Here\u0027s a fix for some pieces of code\naffected I\u0027ve been able to track down. The fix should be backwards\ncompatible with all supported binutils releases in existence and can be\nused as a reference for any other places or off-tree code. The use of the\n\"R\" constraint guarantees a machine-addressable operand.\n\nSigned-off-by: Maciej W. Rozycki \u003cmacro@linux-mips.org\u003e\nCc: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/1680/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "cf745a39dcb10ef80c4a2ff38448f57b69d4c4eb", "tree": "34ef17bc6ffa257551692d38b878dde2969fc33c", "parents": [ "a3aad4aaf871045ab1dd9c99be6c1ace881d8eb0" ], "author": { "name": "Manuel Lauss", "email": "manuel.lauss@googlemail.com", "time": "Mon Oct 25 18:44:11 2010 +0200" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 16 18:11:01 2010 +0000" }, "message": "MIPS: Alchemy: fix build with SERIAL_8250\u003dn\n\nIn commit 7d172bfe (\"Alchemy: Add UART PM methods\") I introduced\nplatform PM methods which call a function of the 8250 driver;\nthis patch works around link failures when the kernel is built\nwithout 8250 support.\n\nSigned-off-by: Manuel Lauss \u003cmanuel.lauss@googlemail.com\u003e\nTo: Linux-MIPS \u003clinux-mips@linux-mips.org\u003e\nPatchwork: https://patchwork.linux-mips.org/patch/1737/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "a3aad4aaf871045ab1dd9c99be6c1ace881d8eb0", "tree": "17fa5ace3d47ef500b0c8e1e1fc2d5adcf02ba03", "parents": [ "d002aaadf84c081623a0a8502c122d1492fbd47c" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 09 19:14:09 2010 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 16 18:11:01 2010 +0000" }, "message": "MIPS: Rename mips_dma_cache_sync back to dma_cache_sync\n\nThis fixes IP22 and IP28 build errors.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "d002aaadf84c081623a0a8502c122d1492fbd47c", "tree": "fe793d0fd1a69b1689788139a7adaf4bbe5c366c", "parents": [ "3f84622d7c7818077f5e6cf4b8a0d1b10dc65147" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Wed Dec 01 17:33:17 2010 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 16 18:11:00 2010 +0000" }, "message": "MIPS: MT: Fix typo in comment.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "1690a7f9ab83f5c823f3044275a4a771a059d5bb", "tree": "adc9521bcf964830a478890d97e250ae5e16a6b5", "parents": [ "59833fcf48ee7b7c8a01e590aa7b7212305c3077" ], "author": { "name": "Hauke Mehrtens", "email": "hauke@hauke-m.de", "time": "Sat Nov 27 17:46:01 2010 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 16 18:11:00 2010 +0000" }, "message": "MIPS: BCM47xx: Swap serial console if ttyS1 was specified.\n\nSome devices like the Netgear WGT634U are using ttyS1 for default console\noutput. We should switch to that console if it was given in the kernel_args\nparameters.\n\nSigned-off-by: Hauke Mehrtens \u003chauke@hauke-m.de\u003e\nTo: linux-mips@linux-mips.org\nCc: Hauke Mehrtens \u003chauke@hauke-m.de\u003e\nPatchwork: https://patchwork.linux-mips.org/patch/1848/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "59833fcf48ee7b7c8a01e590aa7b7212305c3077", "tree": "47e21a465253b2c65073ff5136454e76a883ff2b", "parents": [ "2aa088d6fd8a6c6e6020ea46b70141f0b7ccf5d2" ], "author": { "name": "Hauke Mehrtens", "email": "hauke@hauke-m.de", "time": "Sat Nov 27 17:46:00 2010 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 16 18:10:59 2010 +0000" }, "message": "MIPS: BCM47xx: Use sscanf for parsing mac address\n\nInstead of writing own function for parsing the mac address we now\nuse sscanf.\n\nSigned-off-by: Hauke Mehrtens \u003chauke@hauke-m.de\u003e\nTo: linux-mips@linux-mips.org\nCc: Hauke Mehrtens \u003chauke@hauke-m.de\u003e\nPatchwork: https://patchwork.linux-mips.org/patch/1847/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "2aa088d6fd8a6c6e6020ea46b70141f0b7ccf5d2", "tree": "756cabc4f7cd4007f2b8f94f4a8f35e56d111554", "parents": [ "825710843640dd173bc4b2ea99f1296923e4aa06" ], "author": { "name": "Hauke Mehrtens", "email": "hauke@hauke-m.de", "time": "Sat Nov 27 17:45:59 2010 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 16 18:10:59 2010 +0000" }, "message": "MIPS: BCM47xx: Fill values for b43 into SSB sprom\n\nFill the sprom with all available values from the nvram. Most of these\nnew values are needed for the b43 or b43legacy driver.\n\nParts of this patch have been in OpenWRT for a long time and were written\nby Michael Buesch.\n\nSigned-off-by: Hauke Mehrtens \u003chauke@hauke-m.de\u003e\nTo: linux-mips@linux-mips.org\nCc: Hauke Mehrtens \u003chauke@hauke-m.de\u003e\nPatchwork: https://patchwork.linux-mips.org/patch/1846/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "825710843640dd173bc4b2ea99f1296923e4aa06", "tree": "fb4a5d02940bd74590e7bfbd00c4efe0423f10a5", "parents": [ "e31fee7c3a197d88d1d0ced0e8600386da27fec4" ], "author": { "name": "Hauke Mehrtens", "email": "hauke@hauke-m.de", "time": "Sat Nov 27 17:45:58 2010 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 16 18:10:59 2010 +0000" }, "message": "MIPS: BCM47xx: Do not read config from CFE\n\nThe config options read out here are not stored in CFE but only in NVRAM on\nthe devices. Remove reading from CFE and only access the NVRAM. Reading out\nCFE does not harm but is useless here.\n\nSigned-off-by: Hauke Mehrtens \u003chauke@hauke-m.de\u003e\nTo: linux-mips@linux-mips.org\nCc: Hauke Mehrtens \u003chauke@hauke-m.de\u003e\nPatchwork: https://patchwork.linux-mips.org/patch/1845/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "e31fee7c3a197d88d1d0ced0e8600386da27fec4", "tree": "c18649da51706088339ba3426d6da32d61431450", "parents": [ "5878fc936aebf592cca418ca50773cd578f7daf4" ], "author": { "name": "Thomas Chou", "email": "thomas@wytron.com.tw", "time": "Wed Nov 24 15:35:48 2010 +0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 16 18:10:58 2010 +0000" }, "message": "MIPS: FDT size is a be32\n\nThe totalsize field was be32. And the reserve bootmem would cause failure.\n\nSigned-off-by: Thomas Chou \u003cthomas@wytron.com.tw\u003e\nTo: devicetree-discuss@lists.ozlabs.org\nCc: linux-kernel@vger.kernel.org\nCc: linux-mips@linux-mips.org\nCc: grant.likely@secretlab.ca\nCc: David Daney \u003cddaney@caviumnetworks.com\u003e\nCc: Dezhong Diao \u003cdediao@cisco.com\u003e\nPatchwork: https://patchwork.linux-mips.org/patch/1838/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "5878fc936aebf592cca418ca50773cd578f7daf4", "tree": "ee9d8cec2235b737cfb2cd931e43ede7d9772a53", "parents": [ "190fca3e40a65303eac35ac4fbae4f1f1342431c" ], "author": { "name": "Kevin Cernekee", "email": "cernekee@gmail.com", "time": "Tue Nov 23 10:26:44 2010 -0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 16 18:10:58 2010 +0000" }, "message": "MIPS: Fix CP0 COUNTER clockevent race\n\nConsider the following test case:\n\nwrite_c0_compare(read_c0_count());\n\nEven if the counter doesn\u0027t increment during execution, this might not\ngenerate an interrupt until the counter wraps around. The CPU may\nperform the comparison each time CP0 COUNT increments, not when CP0\nCOMPARE is written.\n\nIf mips_next_event() is called with a very small delta, and CP0 COUNT\nincrements during the calculation of \"cnt +\u003d delta\", it is possible\nthat CP0 COMPARE will be written with the current value of CP0 COUNT.\nIf this is detected, the function should return -ETIME, to indicate\nthat the interrupt might not have actually gotten scheduled.\n\nSigned-off-by: Kevin Cernekee \u003ccernekee@gmail.com\u003e\nCc: linux-mips@linux-mips.org\nCc: linux-kernel@vger.kernel.org\nPatchwork: https://patchwork.linux-mips.org/patch/1836/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "190fca3e40a65303eac35ac4fbae4f1f1342431c", "tree": "682877863c0533cc1dcc4698ff1933a0b614adb2", "parents": [ "4afdea81821880d0fc35e6c7ff54eeed9ec0614d" ], "author": { "name": "Kevin Cernekee", "email": "cernekee@gmail.com", "time": "Tue Nov 23 10:26:45 2010 -0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 16 18:10:58 2010 +0000" }, "message": "MIPS: Fix regression on BCM4710 processor detection\n\nBCM4710 uses the BMIPS32 core (like BCM6345), not the MIPS 4Kc core as\nwas previously believed.\n\nSigned-off-by: Kevin Cernekee \u003ccernekee@gmail.com\u003e\nTested-by: Alexandros C. Couloumbis \u003calex@ozo.com\u003e\nPatchwork: https://patchwork.linux-mips.org/patch/1837/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "4afdea81821880d0fc35e6c7ff54eeed9ec0614d", "tree": "3cdb1cae26a1f42ad7bb0c53d6589c5214f79772", "parents": [ "e5674ad6ca9f1020c2bcc009a55becba3c30d8a3" ], "author": { "name": "Lars-Peter Clausen", "email": "lars@metafoo.de", "time": "Thu Nov 11 19:08:52 2010 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 16 18:10:57 2010 +0000" }, "message": "MIPS: JZ4740: Fix pcm device name\n\nAs part the ASoC multi-component patch (commit f0fba2ad) the jz4740 pcm\ndriver was renamed to \u0027jz4740-pcm-audio\u0027. Adjust the device name\naccordingly.\n\nSigned-off-by: Lars-Peter Clausen \u003clars@metafoo.de\u003e\nCc: linux-mips@linux-mips.org\nCc: linux-kernel@vger.kernel.org\nPatchwork: https://patchwork.linux-mips.org/patch/1770/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "e5674ad6ca9f1020c2bcc009a55becba3c30d8a3", "tree": "05d9d2854ca16e6d4b2f87ddffd17926aa21e9bd", "parents": [ "515b029d005b5694cf612a0a5ca6f861a7e45362" ], "author": { "name": "Tony Wu", "email": "tung7970@gmail.com", "time": "Wed Nov 10 21:48:15 2010 +0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 16 18:10:57 2010 +0000" }, "message": "MIPS: Separate two consecutive loads in memset.S\n\npartial_fixup is used in noreorder block.\n\nSeparating two consecutive loads can save one cycle on processors with\nGPR intrelock and can fix load-use on processors that need a load delay slot.\n\nAlso do so for fwd_fixup.\n\n[Ralf: Only R2000/R3000 class processors are lacking the the load-user\ninterlock and even some of those got it retrofitted. With R2000/R3000\nbeing fairly uncommon these days the impact of this bug should be minor.]\n\nSigned-off-by: Tony Wu \u003ctung7970@gmail.com\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/1768/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "515b029d005b5694cf612a0a5ca6f861a7e45362", "tree": "983f7fea48513cfae6c7f96d4d4036475d8130b1", "parents": [ "0bc6791707694c77b3543de39f77972a65de917a" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Thu Oct 21 16:32:26 2010 -0700" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 16 18:10:57 2010 +0000" }, "message": "MIPS: Send proper signal and siginfo on FP emulator faults.\n\nWe were unconditionally sending SIGBUS with an empty siginfo on FP\nemulator faults. This differs from what happens when real floating\npoint hardware would get a fault.\n\nFor most faults we need to send SIGSEGV with the faulting address\nfilled in in the struct siginfo.\n\nReported-by: Camm Maguire \u003ccamm@maguirefamily.org\u003e\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nTo: linux-mips@linux-mips.org\nCc: Camm Maguire \u003ccamm@maguirefamily.org\u003e\nPatchwork: https://patchwork.linux-mips.org/patch/1727/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "0bc6791707694c77b3543de39f77972a65de917a", "tree": "b3c0f870535093c701816abcde5cd617b1cbf46e", "parents": [ "ff42d62047e45075c54a5543bd4f110dfd032d11" ], "author": { "name": "Florian Fainelli", "email": "florian@openwrt.org", "time": "Sun Oct 31 23:49:58 2010 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 16 18:10:56 2010 +0000" }, "message": "MIPS: AR7: Fix loops per jiffies on TNETD7200 devices\n\nTNETD7200 run their CPU clock faster than the default CPU clock we assume.\nIn order to have the correct loops per jiffies settings, initialize clocks right\nbefore setting mips_hpt_frequency. As a side effect, we can no longer use\nmsleep in clocks.c which requires other parts of the kernel to be initialized,\nso replace these with mdelay.\n\nSigned-off-by: Florian Fainelli \u003cflorian@openwrt.org\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/1749/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "ff42d62047e45075c54a5543bd4f110dfd032d11", "tree": "0bf51029517efb60eeb2394fcadbadaf8893cdb3", "parents": [ "3bd27e329ca80f4946efdd12bf1f5a9bf0886e76" ], "author": { "name": "Florian Fainelli", "email": "florian@openwrt.org", "time": "Sun Oct 31 23:49:57 2010 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 16 18:10:56 2010 +0000" }, "message": "MIPS: AR7: Fix double ar7_gpio_init declaration\n\nSigned-off-by: Florian Fainelli \u003cflorian@openwrt.org\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/1748/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "3bd27e329ca80f4946efdd12bf1f5a9bf0886e76", "tree": "ede90a8794e5cb98370eadbc66a568f08f0a667d", "parents": [ "690ca2ce0c824e8d3da7b2e273c2c873ab96d1e6" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Fri Nov 05 15:12:48 2010 -0700" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 16 18:10:56 2010 +0000" }, "message": "MIPS: Rework GENERIC_HARDIRQS Kconfig.\n\nRecent changes to CONFIG_GENERIC_HARDIRQS have caused us to start getting:\n\nwarning: (SMP \u0026\u0026 SYS_SUPPORTS_SMP) selects IRQ_PER_CPU which has unmet direct dependencies (HAVE_GENERIC_HARDIRQS)\n\nRearranging our Kconfig quiets the message.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nTo: linux-mips@linux-mips.org\nCc: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nPatchwork: https://patchwork.linux-mips.org/patch/1757/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "690ca2ce0c824e8d3da7b2e273c2c873ab96d1e6", "tree": "0b896950262ace4b4ae2ff6edf2d2f0f352efba9", "parents": [ "ec79812580e360081b58c3e2e8b5b69b8080b5a0" ], "author": { "name": "Yoichi Yuasa", "email": "yuasa@linux-mips.org", "time": "Mon Nov 08 17:23:52 2010 +0900" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 16 18:10:55 2010 +0000" }, "message": "MIPS: Alchemy: Add return value check for strict_strtoul()\n\narch/mips/alchemy/devboards/prom.c: In function \u0027prom_init\u0027:\narch/mips/alchemy/devboards/prom.c:60: error: ignoring return value of\n\u0027strict_strtoul\u0027, declared with attribute warn_unused_result\n\nSigned-off-by: Yoichi Yuasa \u003cyuasa@linux-mips.org\u003e\nCc: linux-mips \u003clinux-mips@linux-mips.org\u003e\nPatchwork: https://patchwork.linux-mips.org/patch/1761/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "ec79812580e360081b58c3e2e8b5b69b8080b5a0", "tree": "96bb523800041989acf5a141d9398ec719ff25c0", "parents": [ "863abad4f644b6c12bc8176206b35fa7e7cfe1a9" ], "author": { "name": "Wu Zhangjin", "email": "wuzhangjin@gmail.com", "time": "Mon Nov 08 21:25:24 2010 +0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 16 18:10:55 2010 +0000" }, "message": "MIPS: Loongson: Add return value check for strict_strtoul()\n\ncc1: warnings being treated as errors\narch/mips/loongson/common/env.c: In function \u0027prom_init_env\u0027:\narch/mips/loongson/common/env.c:49: error: ignoring return value of \u0027strict_strtol\u0027, declared with attribute warn_unused_result\narch/mips/loongson/common/env.c:50: error: ignoring return value of \u0027strict_strtol\u0027, declared with attribute warn_unused_result\narch/mips/loongson/common/env.c:51: error: ignoring return value of \u0027strict_strtol\u0027, declared with attribute warn_unused_result\narch/mips/loongson/common/env.c:52: error: ignoring return value of \u0027strict_strtol\u0027, declared with attribute warn_unused_result\n\nSigned-off-by: Wu Zhangjin \u003cwuzhangjin@gmail.com\u003e\nCc: linux-mips \u003clinux-mips@linux-mips.org\u003e\nPatchwork: https://patchwork.linux-mips.org/patch/1762/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "863abad4f644b6c12bc8176206b35fa7e7cfe1a9", "tree": "cf6aacba2461f8d59b81bb03ca345f0d2270db39", "parents": [ "d62c9ced7ca783e64ff4d9d3d1340cfe2284d47b" ], "author": { "name": "Jesper Juhl", "email": "jj@chaosbits.net", "time": "Sat Oct 30 18:37:16 2010 +0200" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 16 18:10:54 2010 +0000" }, "message": "MIPS: VPE loader: Check vmalloc return value in vpe_open\n\nThe return value of the vmalloc() call in arch/mips/kernel/vpe.c::vpe_open()\nis not checked, so we potentially store a null pointer in v-\u003epbuffer. Add\na check for a null return and then return -ENOMEM in that case.\n\n[Ralf: The check added by Jesper\u0027s original patch is where it logically\nshould be. Adding it eleminated the need for the checks in a few other\nplaces, so I removed them. There still is a zillion of other things that\nneed to be fixed in this file / API.]\n\nSigned-off-by: Jesper Juhl \u003cjj@chaosbits.net\u003e\nCc: linux-mips@linux-mips.org\nCc: linux-kernel@vger.kernel.org\nPatchwork: https://patchwork.linux-mips.org/patch/1747/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "d62c9ced7ca783e64ff4d9d3d1340cfe2284d47b", "tree": "6485cecd4bcf8a010cb04198dc2b9bd1d3c8d2fc", "parents": [ "1c0d52b9b5e6ca277c13d6fece9c34ed3159423d" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Mon Nov 01 17:43:08 2010 -0700" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 16 18:10:54 2010 +0000" }, "message": "MIPS: compat: Don\u0027t clobber personality bits in 32-bit sys_personality().\n\nIf PER_LINUX32 has been set on a 32-bit kernel, only twiddle with the\nlow-order personality bits, let the upper bits pass through.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nTo: linux-mips@linux-mips.org\nCc: Camm Maguire \u003ccamm@maguirefamily.org\u003e\nPatchwork: https://patchwork.linux-mips.org/patch/1751/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "1c0d52b9b5e6ca277c13d6fece9c34ed3159423d", "tree": "81ffb96ca45de9cdeff0bae2759c1b220d87f1be", "parents": [ "1d210386f6ef9000b1cd723cf453c5eb0377e722" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Mon Nov 01 17:43:07 2010 -0700" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 16 18:10:54 2010 +0000" }, "message": "MIPS: Don\u0027t clobber personality high bits.\n\nThe high bits of current-\u003epersonality carry settings that we don\u0027t want to\nclobber on each exec. Only clobber them if the lower bits that indicate\neither PER_LINUX or PER_LINUX32 are invalid.\n\nThe clobbering prevents us from using useful bits like ADDR_NO_RANDOMIZE.\n\nReported-by: Camm Maguire \u003ccamm@maguirefamily.org\u003e\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nCc: Camm Maguire \u003ccamm@maguirefamily.org\u003e\nPatchwork: https://patchwork.linux-mips.org/patch/1750/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "1d210386f6ef9000b1cd723cf453c5eb0377e722", "tree": "49124ed4680d3ff0ada3e054e8dfe06939dadcee", "parents": [ "fe749aab1d21cbb4d87527a7df8799583c233496" ], "author": { "name": "Lars-Peter Clausen", "email": "lars@metafoo.de", "time": "Thu Nov 04 23:25:57 2010 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 16 18:10:53 2010 +0000" }, "message": "MIPS: jz4740: Fix section mismatch in prom.c\n\nThis patch fixes the following section mismatch:\n\n\tWARNING: arch/mips/built-in.o(.text+0xc): Section mismatch in reference from the\n\tfunction jz4740_init_cmdline() to the variable .init.data:arcs_cmdline\n\nWhile were at it, make jz4740_init_cmdline static as well.\n\nSigned-off-by: Lars-Peter Clausen \u003clars@metafoo.de\u003e\nCc: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/1755/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "fe749aab1d21cbb4d87527a7df8799583c233496", "tree": "84ce615d851126f7fa7f4724218e3f60cdb13de0", "parents": [ "a989ff898f9740651d00388c33bdf4f2a7914920" ], "author": { "name": "Lars-Peter Clausen", "email": "lars@metafoo.de", "time": "Thu Nov 04 23:25:56 2010 +0100" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 16 18:10:53 2010 +0000" }, "message": "MIPS: jz4740: qi_lb60: Fix gpio for the 6th row of the keyboard matrix\n\nThis patch fixes the gpio number for the 6th row of the keyboard matrix.\n\n(And fixes a typo in my name...)\n\nSigned-off-by: Lars-Peter Clausen \u003clars@metafoo.de\u003e\nCc: linux-mips@linux-mips.org\nCc: stable@kernel.org\nSigned-off-by: https://patchwork.linux-mips.org/patch/1754/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "a989ff898f9740651d00388c33bdf4f2a7914920", "tree": "9f8ca387b8773c19ca4f2556c509ef3381b86abd", "parents": [ "2b3e50234eafc40a04f5f4a2b7bb24b506fd7e87" ], "author": { "name": "Al Viro", "email": "viro@ZenIV.linux.org.uk", "time": "Thu Nov 04 11:13:59 2010 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 16 18:10:52 2010 +0000" }, "message": "MIPS: Don\u0027t stomp on caller\u0027s -\u003eregs[2] in copy_thread()\n\nWe never needed that (-\u003eregs[2] is overwritten on return from syscall paths\nwith return value of syscall, so storing it there early made no sense) and\nwith new restart logics since d27240bf7e61d2656de18e158ec910a902030847 it\nhas become really bad - we lose the original syscall number before the\nplace where we decide that we might need a syscall restart.\n\nNote that for child we do need the assignment to regs[2] - it won\u0027t go\nthrough the normal return from syscall path.\n\n[Ralf: Issue found and reported by Lluís; initial investigations by me;\nbug finally found and patch by Al; testing by me and Lluís.]\n\nSigned-off-by: Al Viro \u003cviro@zeniv.linux.org.uk\u003e\nTested-by: Lluís Batlle i Rossell \u003cviriketo@gmail.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "2b3e50234eafc40a04f5f4a2b7bb24b506fd7e87", "tree": "da0eb4b724a59fe6e60dea5b003c1e8e990c652b", "parents": [ "a4851d8f7d6351a395d36ae8fdcf41745a832d76" ], "author": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Tue Nov 02 19:38:53 2010 +0000" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Thu Dec 16 18:10:52 2010 +0000" }, "message": "MIPS: Swarm: Fix typo in symbol name: RTC_M4LT81 -\u003e RTC_M41T81\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "004417a6d468e24399e383645c068b498eed84ad", "tree": "ce3f4ea25186080faec7a7be6648b177e526c436", "parents": [ "5ef428c4b5950dddce7311e84321abb3aff7ebb0" ], "author": { "name": "Peter Zijlstra", "email": "a.p.zijlstra@chello.nl", "time": "Thu Nov 25 18:38:29 2010 +0100" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Fri Nov 26 15:14:56 2010 +0100" }, "message": "perf, arch: Cleanup perf-pmu init vs lockup-detector\n\nThe perf hardware pmu got initialized at various points in the boot,\nsome before early_initcall() some after (notably arch_initcall).\n\nThe problem is that the NMI lockup detector is ran from early_initcall()\nand expects the hardware pmu to be present.\n\nSanitize this by moving all architecture hardware pmu implementations to\ninitialize at early_initcall() and move the lockup detector to an explicit\ninitcall right after that.\n\nCc: paulus \u003cpaulus@samba.org\u003e\nCc: davem \u003cdavem@davemloft.net\u003e\nCc: Michael Cree \u003cmcree@orcon.net.nz\u003e\nCc: Deng-Cheng Zhu \u003cdengcheng.zhu@gmail.com\u003e\nAcked-by: Paul Mundt \u003clethal@linux-sh.org\u003e\nAcked-by: Will Deacon \u003cwill.deacon@arm.com\u003e\nSigned-off-by: Peter Zijlstra \u003ca.p.zijlstra@chello.nl\u003e\nLKML-Reference: \u003c1290707759.2145.119.camel@laptop\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "2f55ac072f5344519348c0c94b3d2f4cca46847b", "tree": "f3d544ab2812503b12a205b2515111a796638ffb", "parents": [ "acc2472ed33fc5e72482cc3b3b846077d97c2f8b" ], "author": { "name": "Lionel Debroux", "email": "lionel_debroux@yahoo.fr", "time": "Tue Nov 16 14:14:02 2010 +0100" }, "committer": { "name": "Jiri Kosina", "email": "jkosina@suse.cz", "time": "Tue Nov 16 14:14:02 2010 +0100" }, "message": "suspend: constify platform_suspend_ops\n\nWhile at it, fix two checkpatch errors.\nSeveral non-const struct instances constified by this patch were added after\nthe introduction of platform_suspend_ops in checkpatch.pl\u0027s list of \"should\nbe const\" structs (79404849e90a41ea2109bd0e2f7c7164b0c4ce73).\n\nPatch against mainline.\nInspired by hunks of the grsecurity patch, updated for newer kernels.\n\nSigned-off-by: Lionel Debroux \u003clionel_debroux@yahoo.fr\u003e\nAcked-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Jiri Kosina \u003cjkosina@suse.cz\u003e\n" }, { "commit": "b595076a180a56d1bb170e6eceda6eb9d76f4cd3", "tree": "bc01ec7283808013e0b8ce7713fd6fc40f810429", "parents": [ "6aaccece1c483f189f76f1282b3984ff4c7ecb0a" ], "author": { "name": "Uwe Kleine-König", "email": "u.kleine-koenig@pengutronix.de", "time": "Mon Nov 01 15:38:34 2010 -0400" }, "committer": { "name": "Jiri Kosina", "email": "jkosina@suse.cz", "time": "Mon Nov 01 15:38:34 2010 -0400" }, "message": "tree-wide: fix comment/printk typos\n\n\"gadget\", \"through\", \"command\", \"maintain\", \"maintain\", \"controller\", \"address\",\n\"between\", \"initiali[zs]e\", \"instead\", \"function\", \"select\", \"already\",\n\"equal\", \"access\", \"management\", \"hierarchy\", \"registration\", \"interest\",\n\"relative\", \"memory\", \"offset\", \"already\",\n\nSigned-off-by: Uwe Kleine-König \u003cu.kleine-koenig@pengutronix.de\u003e\nSigned-off-by: Jiri Kosina \u003cjkosina@suse.cz\u003e\n" }, { "commit": "79346507ad48895f41b438fa562b1965721f36b9", "tree": "5c115ce87f1fbc0b530f30db56cecf824e9f6e05", "parents": [ "706d4b12f8d7edd28d7e879a77235472da393edb", "40847437f15221b5822ba70550e8b9fcccfb9bb3" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sat Oct 30 08:31:35 2010 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sat Oct 30 08:31:35 2010 -0700" }, "message": "Merge git://git.infradead.org/mtd-2.6\n\n* git://git.infradead.org/mtd-2.6: (82 commits)\n mtd: fix build error in m25p80.c\n mtd: Remove redundant mutex from mtd_blkdevs.c\n MTD: Fix wrong check register_blkdev return value\n Revert \"mtd: cleanup Kconfig dependencies\"\n mtd: cfi_cmdset_0002: make sector erase command variable\n mtd: cfi_cmdset_0002: add CFI detection for SST 38VF640x chips\n mtd: cfi_util: add support for switching SST 39VF640xB chips into QRY mode\n mtd: cfi_cmdset_0001: use defined value of P_ID_INTEL_PERFORMANCE instead of hardcoded one\n block2mtd: dubious assignment\n P4080/mtd: Fix the freescale lbc issue with 36bit mode\n P4080/eLBC: Make Freescale elbc interrupt common to elbc devices\n mtd: phram: use KBUILD_MODNAME\n mtd: OneNAND: S5PC110: Fix double call suspend \u0026 resume function\n mtd: nand: fix MTD_MODE_RAW writes\n jffs2: use kmemdup\n mtd: sm_ftl: cosmetic, use bool when possible\n mtd: r852: remove useless pci powerup/down from suspend/resume routines\n mtd: blktrans: fix a race vs kthread_stop\n mtd: blktrans: kill BKL\n mtd: allow to unload the mtdtrans module if its block devices aren\u0027t open\n ...\n\nFix up trivial whitespace-introduced conflict in drivers/mtd/mtdchar.c\n" }, { "commit": "67577927e8d7a1f4b09b4992df640eadc6aacb36", "tree": "2e9efe6b5745965faf0dcc084d4613d9356263f9", "parents": [ "6fe4c590313133ebd5dadb769031489ff178ece1", "51f00a471ce8f359627dd99aeac322947a0e491b" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Oct 30 12:35:11 2010 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Oct 30 12:35:11 2010 +0100" }, "message": "Merge branch \u0027master\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git\n\nConflicts:\n\tdrivers/mtd/mtd_blkdevs.c\n\nMerge Grant\u0027s device-tree bits so that we can apply the subsequent fixes.\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "64575f918f3279d8487cf670dbefa956ce16a526", "tree": "eb870d0d7cb9adbfbb6c47ad77c0a58611d00947", "parents": [ "412910cd046c1f14f0fba9c0aec401d47e57dcd1" ], "author": { "name": "Wu Zhangjin", "email": "wuzhangjin@gmail.com", "time": "Wed Oct 27 18:59:09 2010 +0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Oct 29 19:08:56 2010 +0100" }, "message": "ftrace/MIPS: Enable C Version of recordmcount\n\nSelects HAVE_C_RECORDMCOUNT to use the C version of the recordmcount\nintead of the old Perl Version of recordmcount.\n\nSigned-off-by: Wu Zhangjin \u003cwuzhangjin@gmail.com\u003e\nLKML-Reference: \u003cbb99009a9ac79d3f55a8c8bf1c8bd2bc0e1f160e.1288176026.git.wuzhangjin@gmail.com\u003e\nSigned-off-by: Steven Rostedt \u003crostedt@goodmis.org\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "949e51bea342da838be5295628e4a7ada8bae833", "tree": "8967391768d4da3a99a2adf85e0834e0fa7a2009", "parents": [ "18d693b3598fdebdd5c65a613221793456a7ce45" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Thu Oct 14 11:32:33 2010 -0700" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Oct 29 19:08:53 2010 +0100" }, "message": "MIPS: Make TASK_SIZE reflect proper size for both 32 and 64 bit processes.\n\nThe TASK_SIZE macro should reflect the size of a user process virtual\naddress space. Previously for 64-bit kernels, this was not the case.\nThe immediate cause of pain was in\nhugetlbfs/inode.c:hugetlb_get_unmapped_area() where 32-bit processes\ntrying to mmap a huge page would be served a page with an address\noutside of the 32-bit address range. But there are other uses of\nTASK_SIZE in the kernel as well that would like an accurate value.\n\nThe new definition is nice because it now makes TASK_SIZE and\nTASK_SIZE_OF() yield the same value for any given process.\n\nFor 32-bit kernels there should be no change, although I did factor\nout some code in asm/processor.h that became identical for the 32-bit and\n64-bit cases.\n\n__UA_LIMIT is now set to ~((1 \u003c\u003c SEGBITS) - 1) for 64-bit kernels.\nThis should eliminate the possibility of getting a\nAddressErrorException in the kernel for addresses that pass the\naccess_ok() test.\n\nWith the patch applied, I can still run o32, n32 and n64 processes,\nand have an o32 shell fork/exec both n32 and n64 processes.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nTo: linux-mips@linux-mips.org\nPatchwork: https://patchwork.linux-mips.org/patch/1701/\n" }, { "commit": "18d693b3598fdebdd5c65a613221793456a7ce45", "tree": "bdec7d15eb2ba774292358b2a617965ab3ff4530", "parents": [ "ea31a6b203710c03d1fc025377a19572e620588a" ], "author": { "name": "Kevin Cernekee", "email": "cernekee@gmail.com", "time": "Sat Oct 16 14:22:38 2010 -0700" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Oct 29 19:08:53 2010 +0100" }, "message": "MIPS: Allow UserLocal on MIPS_R1 processors\n\nSome MIPS32R1 processors implement UserLocal (RDHWR $29) to accelerate\nprograms that make extensive use of thread-local storage. Therefore,\nsetting up the HWRENA register should not depend on cpu_has_mips_r2.\n\nSigned-off-by: Kevin Cernekee \u003ccernekee@gmail.com\u003e\nCc: linux-mips@linux-mips.org\nCc: linux-kernel@vger.kernel.org\n" }, { "commit": "ea31a6b203710c03d1fc025377a19572e620588a", "tree": "b9a39c79e7080b9790936618a704439d057cb78a", "parents": [ "af231172634b5c0923fa7484a043fadcc07e899e" ], "author": { "name": "Kevin Cernekee", "email": "cernekee@gmail.com", "time": "Wed Oct 20 20:05:42 2010 -0700" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Oct 29 19:08:52 2010 +0100" }, "message": "MIPS: Honor L2 bypass bit\n\nOn many of the newer MIPS32 cores, CP0 CONFIG2 bit 12 (L2B) indicates\nthat the L2 cache is disabled and therefore Linux should not attempt\nto use it.\n\n[Ralf: Moved the code added by Kevin\u0027s original patch into a separate\nfunction that can easily be replaced for platforms that need more a\ndifferent probe.]\n\nSigned-off-by: Kevin Cernekee \u003ccernekee@gmail.com\u003e\nCc: linux-mips@linux-mips.org\u003e\nCc: \u003clinux-kernel@vger.kernel.org\u003e\nPatchwork: https://patchwork.linux-mips.org/patch/1723/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "af231172634b5c0923fa7484a043fadcc07e899e", "tree": "61116cff04ff8a8657dca176b04ec35090eac14e", "parents": [ "c1c0c461c6e5f55add64012249cd6e2c8b3e62a9" ], "author": { "name": "Kevin Cernekee", "email": "cernekee@gmail.com", "time": "Sat Oct 16 14:22:32 2010 -0700" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Oct 29 19:08:52 2010 +0100" }, "message": "MIPS: Add BMIPS CP0 register definitions\n\nSigned-off-by: Kevin Cernekee \u003ccernekee@gmail.com\u003e\nCc: mbizon@freebox.fr\nCc: linux-mips@linux-mips.org\nCc: linux-kernel@vger.kernel.org\nTested-by: Florian Fainelli \u003cffainelli@freebox.fr\u003e\nPatchwork: https://patchwork.linux-mips.org/patch/1708/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\n" }, { "commit": "c1c0c461c6e5f55add64012249cd6e2c8b3e62a9", "tree": "03e5a608c038f8c86da8b69d9dfef4874ba379df", "parents": [ "602977b0d672687909b0cb0542ede134ed6ef858" ], "author": { "name": "Kevin Cernekee", "email": "cernekee@gmail.com", "time": "Sun Oct 17 10:56:53 2010 -0700" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Oct 29 19:08:51 2010 +0100" }, "message": "MIPS: Add BMIPS processor types to Kconfig\n\n[v2: add \"VIPER\" marketing name for BMIPS4350]\n\nAdd processor feature definitions for BMIPS3300, BMIPS4350, BMIPS4380,\nand BMIPS5000.\n\nSigned-off-by: Kevin Cernekee \u003ccernekee@gmail.com\u003e\nCc: mbizon@freebox.fr\nCc: linux-mips@linux-mips.org\nCc: linux-kernel@vger.kernel.org\nTested-by: Florian Fainelli \u003cffainelli@freebox.fr\u003e\nPatchwork: https://patchwork.linux-mips.org/patch/1716/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\n" }, { "commit": "602977b0d672687909b0cb0542ede134ed6ef858", "tree": "8f40b3cfbf2cc32a445a69a548837521fcdfd7d6", "parents": [ "3a9ab99e0341558e451327fbbfc39b0d3cff7e9a" ], "author": { "name": "Kevin Cernekee", "email": "cernekee@gmail.com", "time": "Sat Oct 16 14:22:30 2010 -0700" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Oct 29 19:08:50 2010 +0100" }, "message": "MIPS: Decouple BMIPS CPU support from bcm47xx/bcm63xx SoC code\n\nBMIPS processor cores are used in 50+ different chipsets spread across\n5+ product lines. In many cases the chipsets do not share the same\nperipheral register layouts, the same register blocks, the same\ninterrupt controllers, the same memory maps, or much of anything else.\n\nBut, across radically different SoCs that share nothing more than the\nsame BMIPS CPU, a few things are still mostly constant:\n\nSMP operations\nAccess to performance counters\nDMA cache coherency quirks\nCache and memory bus configuration\n\nSo, it makes sense to treat each BMIPS processor type as a generic\n\"building block,\" rather than tying it to a specific SoC. This makes it\neasier to support a large number of BMIPS-based chipsets without\nunnecessary duplication of code, and provides the infrastructure needed\nto support BMIPS-proprietary features.\n\nSigned-off-by: Kevin Cernekee \u003ccernekee@gmail.com\u003e\nCc: mbizon@freebox.fr\nCc: linux-mips@linux-mips.org\nCc: linux-kernel@vger.kernel.org\nTested-by: Florian Fainelli \u003cffainelli@freebox.fr\u003e\nPatchwork: https://patchwork.linux-mips.org/patch/1706/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\n" }, { "commit": "3a9ab99e0341558e451327fbbfc39b0d3cff7e9a", "tree": "95b25a87dac85f8633f0b31575f96c528815ddfb", "parents": [ "7e788d967c092343cca773542565c362991c87c0" ], "author": { "name": "Deng-Cheng Zhu", "email": "dengcheng.zhu@gmail.com", "time": "Tue Oct 12 19:37:24 2010 +0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Oct 29 19:08:49 2010 +0100" }, "message": "MIPS: Add support for hardware performance events (mipsxx)\n\nThis patch adds the mipsxx Perf-events support based on the skeleton.\nGeneric hardware events and cache events are now fully implemented for\nthe 24K/34K/74K/1004K cores. To support other cores in mipsxx (such as\nR10000/SB1), the generic hardware event tables and cache event tables\nneed to be filled out. To support other CPUs which have different PMU\nthan mipsxx, such as RM9000 and LOONGSON2, the additional files\nperf_event_$cpu.c need to be created.\n\nRaw event is an important part of Perf-events. It helps the user collect\nperformance data for events that are not listed as the generic hardware\nevents and cache events but ARE supported by the CPU\u0027s PMU.\n\nThis patch also adds this feature for mipsxx 24K/34K/74K/1004K. For how to\nuse it, please refer to processor core software user\u0027s manual and the\ncomments for mipsxx_pmu_map_raw_event() for more details.\n\nPlease note that this is a \"precise\" implementation, which means the\nkernel will check whether the requested raw events are supported by this\nCPU and which hardware counters can be assigned for them.\n\nTo test the functionality of Perf-event, you may want to compile the tool\n\"perf\" for your MIPS platform. You can refer to the following URL:\nhttp://www.linux-mips.org/archives/linux-mips/2010-10/msg00126.html\n\nYou also need to customize the CFLAGS and LDFLAGS in tools/perf/Makefile\nfor your libs, includes, etc.\n\nIn case you encounter the boot failure in SMVP kernel on multi-threading\nCPUs, you may take a look at:\nhttp://www.linux-mips.org/git?p\u003dlinux-mti.git;a\u003dcommitdiff;h\u003d5460815027d802697b879644c74f0e8365254020\n\nSigned-off-by: Deng-Cheng Zhu \u003cdengcheng.zhu@gmail.com\u003e\nTo: linux-mips@linux-mips.org\nCc: a.p.zijlstra@chello.nl\nCc: paulus@samba.org\nCc: mingo@elte.hu\nCc: acme@redhat.com\nCc: jamie.iles@picochip.com\nCc: ddaney@caviumnetworks.com\nCc: matt@console-pimps.org\nPatchwork: https://patchwork.linux-mips.org/patch/1689/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n\n create mode 100644 arch/mips/kernel/perf_event_mipsxx.c\n" }, { "commit": "7e788d967c092343cca773542565c362991c87c0", "tree": "88c3ef91aba02a7dae93ccc674f5bed461c16d0d", "parents": [ "14f7001284185bffeb796a181664906f7160f593" ], "author": { "name": "Deng-Cheng Zhu", "email": "dengcheng.zhu@gmail.com", "time": "Tue Oct 12 19:37:23 2010 +0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Oct 29 19:08:49 2010 +0100" }, "message": "MIPS: Perf-events: Add callchain support\n\nAdds callchain support for MIPS Perf-events. For more info on this feature,\nplease refer to tools/perf/Documentation/perf-report.txt and\ntools/perf/design.txt.\n\nCurrently userspace callchain data is not recorded, because we do not have\na safe way to do this.\n\nSigned-off-by: Deng-Cheng Zhu \u003cdengcheng.zhu@gmail.com\u003e\nAcked-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nTo: linux-mips@linux-mips.org\nCc: a.p.zijlstra@chello.nl\nCc: paulus@samba.org\nCc: mingo@elte.hu\nCc: acme@redhat.com\nCc: jamie.iles@picochip.com\nCc: matt@console-pimps.org\nPatchwork: https://patchwork.linux-mips.org/patch/1690/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "14f7001284185bffeb796a181664906f7160f593", "tree": "5524b4a8bfdee982b2d5db68053ae0a8dd599b57", "parents": [ "7f788d2d53085815d474559cd51ef1f38b0a9bb8" ], "author": { "name": "Deng-Cheng Zhu", "email": "dengcheng.zhu@gmail.com", "time": "Tue Oct 12 19:37:22 2010 +0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Oct 29 19:08:48 2010 +0100" }, "message": "MIPS: add support for hardware performance events (skeleton)\n\nThis patch provides the skeleton of the HW perf event support. To enable\nthis feature, we can not choose the SMTC kernel; Oprofile should be\ndisabled; kernel performance events be selected. Then we can enable it in\nKernel type menu.\n\nOprofile for MIPS platforms initializes irq at arch init time. Currently\nwe do not change this logic to allow PMU reservation.\n\nIf a platform has EIC, we can use the irq base and perf counter irq offset\ndefines for the interrupt controller in specific init_hw_perf_events().\n\nBased on this skeleton patch, the 3 different kinds of MIPS PMU, namely,\nmipsxx/loongson2/rm9000, can be supported by adding corresponding lower\nlevel C files at the bottom. The suggested names of these files are\nperf_event_mipsxx.c/perf_event_loongson2.c/perf_event_rm9000.c. So, for\nexample, we can do this by adding \"#include perf_event_mipsxx.c\" at the\nbottom of perf_event.c.\n\nIn addition, PMUs with 64bit counters are also considered in this patch.\n\nSigned-off-by: Deng-Cheng Zhu \u003cdengcheng.zhu@gmail.com\u003e\nTo: linux-mips@linux-mips.org\nCc: a.p.zijlstra@chello.nl\nCc: paulus@samba.org\nCc: mingo@elte.hu\nCc: acme@redhat.com\nCc: jamie.iles@picochip.com\nCc: ddaney@caviumnetworks.com\nCc: matt@console-pimps.org\nPatchwork: https://patchwork.linux-mips.org/patch/1688/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "7f788d2d53085815d474559cd51ef1f38b0a9bb8", "tree": "32c2b6af15da818a02502a678225ff4de754b542", "parents": [ "6dbd972850c092e50e10bd14a3324e2abe88997a" ], "author": { "name": "Deng-Cheng Zhu", "email": "dengcheng.zhu@gmail.com", "time": "Tue Oct 12 19:37:21 2010 +0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Oct 29 19:08:48 2010 +0100" }, "message": "MIPS: add support for software performance events\n\nSoftware events are required as part of the measurable stuff by the\nLinux performance counter subsystem. Here is the list of events added by\nthis patch:\nPERF_COUNT_SW_PAGE_FAULTS\nPERF_COUNT_SW_PAGE_FAULTS_MIN\nPERF_COUNT_SW_PAGE_FAULTS_MAJ\nPERF_COUNT_SW_ALIGNMENT_FAULTS\nPERF_COUNT_SW_EMULATION_FAULTS\n\nSigned-off-by: Deng-Cheng Zhu \u003cdengcheng.zhu@gmail.com\u003e\nTo: linux-mips@linux-mips.org\nCc: a.p.zijlstra@chello.nl\nCc: paulus@samba.org\nCc: mingo@elte.hu\nCc: acme@redhat.com\nCc: jamie.iles@picochip.com\nAcked-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nReviewed-by: Matt Fleming \u003cmatt@console-pimps.org\u003e\nPatchwork: https://patchwork.linux-mips.org/patch/1686/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "6dbd972850c092e50e10bd14a3324e2abe88997a", "tree": "99445160e479bdab166672d9cd120c0dc7634f0a", "parents": [ "238dd317f74250983aefbde6dc0a1f345a717993" ], "author": { "name": "Deng-Cheng Zhu", "email": "dengcheng.zhu@gmail.com", "time": "Tue Oct 12 19:37:20 2010 +0800" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Oct 29 19:08:47 2010 +0100" }, "message": "MIPS: define local_xchg from xchg_local to atomic_long_xchg\n\nPerf-events is now using local_t helper functions internally. There is a\nuse of local_xchg(). On MIPS, this is defined to xchg_local() which is\nmissing in asm/system.h. This patch re-defines local_xchg() in asm/local.h\nto atomic_long_xchg(). Then Perf-events can pass the build.\n\nSigned-off-by: Deng-Cheng Zhu \u003cdengcheng.zhu@gmail.com\u003e\nTo: linux-mips@linux-mips.org\nCc: a.p.zijlstra@chello.nl\nCc: paulus@samba.org\nCc: mingo@elte.hu\nCc: acme@redhat.com\nCc: jamie.iles@picochip.com\nCc: ddaney@caviumnetworks.com\nCc: matt@console-pimps.org\nPatchwork: https://patchwork.linux-mips.org/patch/1687/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "238dd317f74250983aefbde6dc0a1f345a717993", "tree": "7ba6759dbb6e5b2639666fb8b6a0b02dac55a61c", "parents": [ "3bc6968adc7b1926f4582a33a33ad42d9b302ce0" ], "author": { "name": "Florian Fainelli", "email": "florian@openwrt.org", "time": "Sun Aug 29 17:08:44 2010 +0200" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Oct 29 19:08:46 2010 +0100" }, "message": "MIPS: AR7: Add support for Titan (TNETV10xx) SoC variant\n\nAdd support for Titan TNETV1050,1055,1056,1060 variants. This SoC is almost\ncompletely identical to AR7 except on a few points:\n- a second bank of gpios is available\n- vlynq0 on titan is vlynq1 on ar7\n- different PHY addresses for cpmac0\n\nThis SoC can be found on commercial products like the Linksys WRTP54G\n\nOriginal patch by Xin with improvments by Florian.\n\nSigned-off-by: Xin Zhen \u003cxlonestar2000@aim.com\u003e\nSigned-off-by: Florian Fainelli \u003cflorian@openwrt.org\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/1563/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n\n---\n" }, { "commit": "3bc6968adc7b1926f4582a33a33ad42d9b302ce0", "tree": "67d37a08a426247ee059391c54bd363e542a4ca8", "parents": [ "340fbb8b12dd24c83b1e8ff094b8e2c218144217" ], "author": { "name": "Florian Fainelli", "email": "florian@openwrt.org", "time": "Sun Aug 29 17:08:41 2010 +0200" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Oct 29 19:08:46 2010 +0100" }, "message": "MIPS: AR7: Initialize GPIO earlier\n\nIn order to detect the Titan variant, we must initialize GPIOs earlier since\ndetection relies on some GPIO values to be set.\n\nSigned-off-by: Florian Fainelli \u003cflorian@openwrt.org\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/1562/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n\n---\n" }, { "commit": "340fbb8b12dd24c83b1e8ff094b8e2c218144217", "tree": "95d9820ba6c2a2645c70ce6b2c2151587f215482", "parents": [ "1643accdaad4625c2877f7ceefa39c1cb3e90117" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Fri Oct 08 14:47:53 2010 -0700" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Oct 29 19:08:45 2010 +0100" }, "message": "MIPS: Add platform device and Kconfig for Octeon USB EHCI / OHCI\n\nDeclare that OCTEON reference boards have both OHCI and EHCI.\n\nAdd platform devices for the corresponding hardware.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nTo: linux-usb@vger.kernel.org\nTo: dbrownell@users.sourceforge.net\nPatchwork: http://patchwork.linux-mips.org/patch/1676/\nAcked-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "4169b86324fbefdf137a0bd69154d0e874f2bec2", "tree": "0c1bc321ff38fb9492907dd570ae94dc7acecb4b", "parents": [ "c9941158fd8a539a56b0e8a4740ec1f6beb23ea3" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Fri Oct 08 14:47:51 2010 -0700" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Oct 29 19:08:43 2010 +0100" }, "message": "MIPS: Octeon: Add register definitions for EHCI / OHCI USB glue logic.\n\nThe EHCI and OHCI blocks connection to the I/O bus is controlled by\nthese registers.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nTo: linux-usb@vger.kernel.org\nTo: dbrownell@users.sourceforge.net\nPatchwork: http://patchwork.linux-mips.org/patch/1674/\nAcked-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n\n create mode 100644 arch/mips/include/asm/octeon/cvmx-uctlx-defs.h\n" }, { "commit": "c9941158fd8a539a56b0e8a4740ec1f6beb23ea3", "tree": "73e3868737061e1d5b0b61c182ea443e3ccd94e3", "parents": [ "468ffde46d429fbd291b0ef43a06afe9c837629f" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Thu Oct 07 16:03:53 2010 -0700" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Oct 29 19:08:43 2010 +0100" }, "message": "MIPS: Octeon: Apply CN63XXP1 errata workarounds.\n\nThe CN63XXP1 needs a couple of workarounds to ensure memory is not written\nin unexpected ways.\n\nAll PREF with hints in the range 0-4,6-24 are replaced with PREF 28. We\npass a flag to the assembler to cover compiler generated code, and patch\nuasm for the dynamically generated code.\n\nThe write buffer threshold is reduced to 4.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/1672/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "4b8bca7028fbed182c78b4f86769e365f2075d8e", "tree": "7dc9523d3ce671e708a2d3d199e768357cb2d07b", "parents": [ "e195aa3039c5c4eeb60c415a7a0f3006d5cdcd3b" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Thu Oct 07 16:03:50 2010 -0700" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Oct 29 19:08:41 2010 +0100" }, "message": "MIPS: Octeon: Use I/O clock rate for calculations.\n\nThe I2C and UARTS are clocked by the I/O clock, use its rate for these\ndevices.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/1670/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "e195aa3039c5c4eeb60c415a7a0f3006d5cdcd3b", "tree": "62817e61ddac8e1212f04cbdbbcf542849fdd8e6", "parents": [ "3b29dadff98887ecdc5db458c2961777016b7b86" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Thu Oct 07 16:03:49 2010 -0700" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Oct 29 19:08:40 2010 +0100" }, "message": "MIPS: Octeon: Add octeon_get_io_clock_rate() for cn63xx\n\nStarting with cn63xx Octeon I/O blocks are clocked at a different rate\nthan the CPU. Add a new function octeon_get_io_clock_rate() that\nyields the I/O clock rate.\n\nAlso rearrange octeon_get_clock_rate() to get the value from the saved\nsysinfo structure.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/1671/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "3b29dadff98887ecdc5db458c2961777016b7b86", "tree": "e9098cfce91940993ab06e55cb33ceac3ef1ba0c", "parents": [ "54954a6d6ba1c2f44375d2992d50f1db56a8857d" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Thu Oct 07 16:03:48 2010 -0700" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Oct 29 19:08:39 2010 +0100" }, "message": "MIPS: Octeon: Remove bogus code from octeon_get_clock_rate()\n\nWe can run with any simulator clock rate. Get rid of the code\noverriding it to 6MHz.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/1669/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "54954a6d6ba1c2f44375d2992d50f1db56a8857d", "tree": "332959aa2067a9b8819cf9ccd8e735abb78d88cb", "parents": [ "f92a6b0875977132074a696e8d44c95e8472d8ac" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Thu Oct 07 16:03:47 2010 -0700" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Oct 29 19:08:38 2010 +0100" }, "message": "MIPS: Octeon: Scale Octeon2 clocks in octeon_init_cvmcount()\n\nThe per-CPU clocks are synchronized from IPD_CLK_COUNT, on cn63XX it must\nbe scaled by the clock frequency ratio.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/1667/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "f92a6b0875977132074a696e8d44c95e8472d8ac", "tree": "c1c7763f5dcbe637648f3c1b5174609673e30c54", "parents": [ "0e56b3852b1c3be83d1f07a82a86084fabacf789" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Thu Oct 07 16:03:46 2010 -0700" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Oct 29 19:08:38 2010 +0100" }, "message": "MIPS: Octeon: Enable Read Inhibit / eXecute Inhibit on Octeon II.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/1666/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "0e56b3852b1c3be83d1f07a82a86084fabacf789", "tree": "3120f4ae30ef5933dc0bc9bf4c9f30ff29a155d6", "parents": [ "f8bf7e688c226ba83b35a1547146e296e14b33c7" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Thu Oct 07 16:03:45 2010 -0700" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Oct 29 19:08:37 2010 +0100" }, "message": "MIPS: Octeon: Probe for Octeon II CPUs.\n\nThe OCTEON II ISA extends the original OCTEON ISA, so give it its own\n__elf_platform string so optimized libraries can be selected in\nuserspace.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/1665/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "f8bf7e688c226ba83b35a1547146e296e14b33c7", "tree": "c46c98c7cb29e3c93d4b54c5e8e991e19485b79d", "parents": [ "1584d7f2d58999c00066a4afc4ad95e07b2a04e8" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Thu Oct 07 16:03:44 2010 -0700" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Oct 29 19:08:36 2010 +0100" }, "message": "MIPS: Octeon: Handle Octeon II caches.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/1664/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "1584d7f2d58999c00066a4afc4ad95e07b2a04e8", "tree": "cb451b435fb164ca6582a18a214643329adf87cc", "parents": [ "b8db85b5b5c22236d168eb03a67c2641bf7fa651" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Thu Oct 07 16:03:43 2010 -0700" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Oct 29 19:08:35 2010 +0100" }, "message": "MIPS: Add identifiers for Octeon II CPUs.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/1662/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "b8db85b5b5c22236d168eb03a67c2641bf7fa651", "tree": "a372c5f0db85255ce60f2670a1211f205239d045", "parents": [ "a70b13a9f07ae0e21870ed3e9b6829f556579c5c" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Thu Oct 07 16:03:42 2010 -0700" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Oct 29 19:08:35 2010 +0100" }, "message": "MIPS: Octeon: Update L2 Cache code for CN63XX\n\nThe CN63XX has a different L2 cache architecture. Update the helper\nfunctions to reflect this.\n\nSome joining of split lines was also done to improve readability, as\nwell as reformatting of comments.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/1663/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "a70b13a9f07ae0e21870ed3e9b6829f556579c5c", "tree": "e15268066b0b35a0791c76568156812b8973dab4", "parents": [ "aa32a955ae46d4117e880417c89a2efcc88579c2" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Thu Oct 07 16:03:41 2010 -0700" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Oct 29 19:08:34 2010 +0100" }, "message": "MIPS: Octeon: Add cn63XX to Octeon chip detection macros.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/1661/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" }, { "commit": "aa32a955ae46d4117e880417c89a2efcc88579c2", "tree": "538f1564b70d017b224a423d99bc2a0366c1f745", "parents": [ "b93b2abce497873be97d765b848e0a955d29f200" ], "author": { "name": "David Daney", "email": "ddaney@caviumnetworks.com", "time": "Thu Oct 07 16:03:40 2010 -0700" }, "committer": { "name": "Ralf Baechle", "email": "ralf@linux-mips.org", "time": "Fri Oct 29 19:08:33 2010 +0100" }, "message": "MIPS: Octeon: Update register definitions for CN63XX chips\n\nThe CN63XX is a new 6-CPU SOC based on the new OCTEON II CPU cores.\n\nJoin some lines back together. This makes some of them exceed 80\ncolumns, but they are uninteresting and this unclutters things.\n\nSigned-off-by: David Daney \u003cddaney@caviumnetworks.com\u003e\nPatchwork: http://patchwork.linux-mips.org/patch/1668/\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n" } ], "next": "b93b2abce497873be97d765b848e0a955d29f200" }