)]}'
{
  "log": [
    {
      "commit": "2e032b62c4c8560d6416ad3cc925cfc2a5eafb07",
      "tree": "8700a84d68eebf61def8dde6cf4bd5d76a13c5fb",
      "parents": [
        "a88f6667078412e5eff37ead68a043ee0ec9f1da"
      ],
      "author": {
        "name": "H Hartley Sweeten",
        "email": "hartleys@visionengravers.com",
        "time": "Fri Dec 11 21:24:33 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Fri Dec 11 21:24:33 2009 -0700"
      },
      "message": "iop-adma.c: use resource_size()\n\nThe size of the requested and ioremaped memory is off by 1.\nUse resource_size() to get the correct value.\n\nSigned-off-by: H Hartley Sweeten \u003chsweeten@visionengravers.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "bbb20089a3275a19e475dbc21320c3742e3ca423",
      "tree": "216fdc1cbef450ca688135c5b8969169482d9a48",
      "parents": [
        "3e48e656903e9fd8bc805c6a2c4264d7808d315b",
        "657a77fa7284d8ae28dfa48f1dc5d919bf5b2843"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:55:21 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:55:21 2009 -0700"
      },
      "message": "Merge branch \u0027dmaengine\u0027 into async-tx-next\n\nConflicts:\n\tcrypto/async_tx/async_xor.c\n\tdrivers/dma/ioat/dma_v2.h\n\tdrivers/dma/ioat/pci.c\n\tdrivers/md/raid5.c\n"
    },
    {
      "commit": "3e48e656903e9fd8bc805c6a2c4264d7808d315b",
      "tree": "dfee34eb1f317b35f33a02291e65ce6ec46e3a5a",
      "parents": [
        "a6417dd58d6832f123f36c6f22c63ec1ab62ce1c",
        "f6dbf651615900646fe0ba1ef5ce1027e5b4748d"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:53:57 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:53:57 2009 -0700"
      },
      "message": "Merge branch \u0027iop-raid6\u0027 into async-tx-next\n"
    },
    {
      "commit": "308136d1abcb2d759bac40ed4f5d42ac4af59d8b",
      "tree": "c0cf21c5144929332a5f99d1aff8393e6cddcbbb",
      "parents": [
        "eda34234578fd822c950fd06b5c5ff7ac08b3001"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:53:02 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:53:02 2009 -0700"
      },
      "message": "iop-adma: implement a private tx_list\n    \nDrop iop-adma\u0027s use of tx_list from struct dma_async_tx_descriptor in\npreparation for removal of this field.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n"
    },
    {
      "commit": "9308add6ea4fedeba37b0d7c4630a542bd34f214",
      "tree": "5b94b9c8eebc7a7ef6879a7fdfc553c6758312dc",
      "parents": [
        "138f4c359d23d2ec38d18bd70dd9613ae515fe93"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:42:52 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Sep 08 17:42:52 2009 -0700"
      },
      "message": "dmaengine: cleanup unused transaction types\n\nNo drivers currently implement these operation types, so they can be\ndeleted.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "f6dbf651615900646fe0ba1ef5ce1027e5b4748d",
      "tree": "a78d096174765ce893dddfd6fed9e5e92d45aaaa",
      "parents": [
        "7bf649aee8ac93ecc280f8745dcf8ec19d7b9fb1"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sat Aug 29 19:12:40 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sat Aug 29 19:12:40 2009 -0700"
      },
      "message": "iop-adma: P+Q self test\n\nEven though the intent is to extend dmatest with P+Q tests there is\nstill value in having an always-on sanity check to prevent an\nunintentionally broken driver from registering.\n\nThis depends on raid6_pq.ko for verification, the side effect being that\nPQ capable channels will fail to register when raid6 is disabled.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n"
    },
    {
      "commit": "7bf649aee8ac93ecc280f8745dcf8ec19d7b9fb1",
      "tree": "b35282323d278afb16c18a42c8c0db34508cef6c",
      "parents": [
        "72be12f0c39df46832403cbfd82e132a883f5ddc"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Fri Aug 28 14:32:04 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sat Aug 29 19:12:39 2009 -0700"
      },
      "message": "iop-adma: P+Q support for iop13xx adma engines\n\niop33x support is not included because that engine is a bit more awkward\nto handle in that it can either be in xor mode or pq mode.  The\ndmaengine/async_tx layers currently only comprehend static capabilities.\n\nNote iop13xx does not support hardware PQ continuation so the driver\nmust handle the DMA_PREP_CONTINUE flag for operations across \u003e 16\nsources. From the comment for dma_maxpq:\n\n/* When an engine does not support native continuation we need 3 extra\n * source slots to reuse P and Q with the following coefficients:\n * 1/ {00} * P : remove P from Q\u0027, but use it as a source for P\u0027\n * 2/ {01} * Q : use Q to continue Q\u0027 calculation\n * 3/ {00} * Q : subtract Q from P\u0027 to cancel (2)\n */\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n\n\n\n"
    },
    {
      "commit": "72be12f0c39df46832403cbfd82e132a883f5ddc",
      "tree": "61a4014d28852692464aca3f509d2024e7006f68",
      "parents": [
        "507fbec4cff442ebce6706db34603bfb9cc3b5a9"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jul 14 13:38:29 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sat Aug 29 19:12:39 2009 -0700"
      },
      "message": "iop-adma: fix lockdep false positive\n\nlockdep correctly identifies a potential recursive locking case for\niop_chan-\u003elock, but in the dependency submission case we expect that the same\nclass will be acquired for both the parent dependency and the child channel.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n"
    },
    {
      "commit": "507fbec4cff442ebce6706db34603bfb9cc3b5a9",
      "tree": "781901167ab7d2ed2f064d9a0e6faa2e87148165",
      "parents": [
        "cb3c82992f62f838e6476a0bff12909158007fc6"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sat Aug 29 19:12:39 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sat Aug 29 19:12:39 2009 -0700"
      },
      "message": "iop-adma: cleanup iop_adma_run_tx_complete_actions\n\nReplace \u0027desc-\u003easync_tx.\u0027 with \u0027tx-\u003e\u0027\n\n[ Impact: pure cleanup ]\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n"
    },
    {
      "commit": "b2f46fd8ef3dff2ab30f31126833f78b7480283a",
      "tree": "9f111e3e313b4d142c12d2d8156a2704a36904f8",
      "parents": [
        "95475e57113c66aac7583925736ed2e2d58c990d"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jul 14 12:20:36 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sat Aug 29 19:09:27 2009 -0700"
      },
      "message": "async_tx: add support for asynchronous GF multiplication\n\n[ Based on an original patch by Yuri Tikhonov ]\n\nThis adds support for doing asynchronous GF multiplication by adding\ntwo additional functions to the async_tx API:\n\n async_gen_syndrome() does simultaneous XOR and Galois field\n    multiplication of sources.\n\n async_syndrome_val() validates the given source buffers against known P\n    and Q values.\n\nWhen a request is made to run async_pq against more than the hardware\nmaximum number of supported sources we need to reuse the previous\ngenerated P and Q values as sources into the next operation.  Care must\nbe taken to remove Q from P\u0027 and P from Q\u0027.  For example to perform a 5\nsource pq op with hardware that only supports 4 sources at a time the\nfollowing approach is taken:\n\np, q \u003d PQ(src0, src1, src2, src3, COEF({01}, {02}, {04}, {08}))\np\u0027, q\u0027 \u003d PQ(p, q, q, src4, COEF({00}, {01}, {00}, {10}))\n\np\u0027 \u003d p + q + q + src4 \u003d p + src4\nq\u0027 \u003d {00}*p + {01}*q + {00}*q + {10}*src4 \u003d q + {10}*src4\n\nNote: 4 is the minimum acceptable maxpq otherwise we punt to\nsynchronous-software path.\n\nThe DMA_PREP_CONTINUE flag indicates to the driver to reuse p and q as\nsources (in the above manner) and fill the remaining slots up to maxpq\nwith the new sources/coefficients.\n\nNote1: Some devices have native support for P+Q continuation and can skip\nthis extra work.  Devices with this capability can advertise it with\ndma_set_maxpq.  It is up to each driver how to handle the\nDMA_PREP_CONTINUE flag.\n\nNote2: The api supports disabling the generation of P when generating Q,\nthis is ignored by the synchronous path but is implemented by some dma\ndevices to save unnecessary writes.  In this case the continuation\nalgorithm is simplified to only reuse Q as a source.\n\nCc: H. Peter Anvin \u003chpa@zytor.com\u003e\nCc: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\nSigned-off-by: Yuri Tikhonov \u003cyur@emcraft.com\u003e\nSigned-off-by: Ilya Yanok \u003cyanok@emcraft.com\u003e\nReviewed-by: Andre Noll \u003cmaan@systemlinux.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n"
    },
    {
      "commit": "099f53cb50e45ef617a9f1d63ceec799e489418b",
      "tree": "fd57f259f58bcf615fe2b17734ed0cbec612782d",
      "parents": [
        "fd74ea65883c7e6903e9b652795f72b723a2be69"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Apr 08 14:28:37 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Apr 08 14:28:37 2009 -0700"
      },
      "message": "async_tx: rename zero_sum to val\n\n\u0027zero_sum\u0027 does not properly describe the operation of generating parity\nand checking that it validates against an existing buffer.  Change the\nname of the operation to \u0027val\u0027 (for \u0027validate\u0027).  This is in\nanticipation of the p+q case where it is a requirement to identify the\ntarget parity buffers separately from the source buffers, because the\ntarget parity buffers will not have corresponding pq coefficients.\n\nReviewed-by: Andre Noll \u003cmaan@systemlinux.org\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "ccccce229c633a92c42cd1a40c0738d7b0d12644",
      "tree": "a954537ae73f2e03c4431b244796cdc255af7a10",
      "parents": [
        "8d47bae004f062630f69f7f83d098424252e232d"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Mar 25 09:13:24 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Mar 25 09:13:24 2009 -0700"
      },
      "message": "dmaengine: initialize tx_list in dma_async_tx_descriptor_init\n\nCentralize this common initialization (and one case where ipu_idmac is\nduplicating -\u003echan initialization).\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n"
    },
    {
      "commit": "5dc18f51a2c06ddab708184e30b7967fb71c1784",
      "tree": "b080f2a651f694f523491487bf92d28c3c63d981",
      "parents": [
        "fd6ec5f3acfe7e94469d83374b83ff183953fa45",
        "7cbd4877e5b167b56a3d6033b926a9f925186e12"
      ],
      "author": {
        "name": "Linus Torvalds",
        "email": "torvalds@linux-foundation.org",
        "time": "Sun Mar 08 10:23:05 2009 -0700"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@linux-foundation.org",
        "time": "Sun Mar 08 10:23:05 2009 -0700"
      },
      "message": "Merge branch \u0027fixes\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx\n\n* \u0027fixes\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx:\n  dmatest: fix use after free in dmatest_exit\n  ipu_idmac: fix spinlock type\n  iop-adma, mv_xor: fix mem leak on self-test setup failure\n  fsldma: fix off by one in dma_halt\n  I/OAT: fail self-test if callback test reaches timeout\n  I/OAT: update driver version and copyright dates\n  I/OAT: list usage cleanup\n  I/OAT: set tcp_dma_copybreak to 256k for I/OAT ver.3\n  I/OAT: cancel watchdog before dma remove\n  I/OAT: fail initialization on zero channels detection\n  I/OAT: do not set DCACTRL_CMPL_WRITE_ENABLE for I/OAT ver.3\n  I/OAT: add verification for proper APICID_TAG_MAP setting by BIOS\n  dmaengine: update kerneldoc\n"
    },
    {
      "commit": "a09b09ae51ace43d28cd9bc1c8bb97986f2b55a6",
      "tree": "a70862b01fc038b92067faf13f623ce5b9492105",
      "parents": [
        "900325a6ce33995688b7a680a34e7698f16f4d72"
      ],
      "author": {
        "name": "Roel Kluin",
        "email": "roel.kluin@gmail.com",
        "time": "Wed Feb 25 13:56:21 2009 +0100"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Mar 04 16:04:40 2009 -0700"
      },
      "message": "iop-adma, mv_xor: fix mem leak on self-test setup failure\n\niop_adma_zero_sum_self_test has the brackets in the wrong place for the\nsetup failure deallocation path.  This error was duplicated in\nmv_xor_xor_self_test.\n\nSigned-off-by: Roel Kluin \u003croel.kluin@gmail.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "bdf602bd737eb07d63d6fa2da826b4751fdf9bab",
      "tree": "6b5478c009ce41008196abbd26961d352e056bd8",
      "parents": [
        "b57ee99fab25dbc12150fe66fe54dc52bc6de784"
      ],
      "author": {
        "name": "Russell King",
        "email": "rmk@dyn-67.arm.linux.org.uk",
        "time": "Tue Mar 03 13:43:47 2009 +0000"
      },
      "committer": {
        "name": "Russell King",
        "email": "rmk+kernel@arm.linux.org.uk",
        "time": "Tue Mar 03 21:04:04 2009 +0000"
      },
      "message": "[ARM] fix lots of ARM __devexit sillyness\n\n`iop_adma_remove\u0027 referenced in section `.data\u0027 of drivers/built-in.o: defined in discarded section `.devexit.text\u0027 of drivers/built-in.o\n`mv_xor_remove\u0027 referenced in section `.data\u0027 of drivers/built-in.o: defined in discarded section `.devexit.text\u0027 of drivers/built-in.o\n`mv64xxx_i2c_unmap_regs\u0027 referenced in section `.devinit.text\u0027 of drivers/built-in.o: defined in discarded section `.devexit.text\u0027 of drivers/built-in.o\n`mv64xxx_i2c_remove\u0027 referenced in section `.data\u0027 of drivers/built-in.o: defined in discarded section `.devexit.text\u0027 of drivers/built-in.o\n`orion_nand_remove\u0027 referenced in section `.data\u0027 of drivers/built-in.o: defined in discarded section `.devexit.text\u0027 of drivers/built-in.o\n`pxafb_remove\u0027 referenced in section `.data\u0027 of drivers/built-in.o: defined in discarded section `.devexit.text\u0027 of drivers/built-in.o\n\nAcked-by: Uwe Kleine-König \u003cu.kleine-koenig@pengutronix.de\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n"
    },
    {
      "commit": "630738b9a52bee40cba685f4ff43fbbc28f2e1ff",
      "tree": "c90ac1fe356e6cdcfc332a2217246e0f319fcadc",
      "parents": [
        "0d603f611d6515049fbceb0267ded43c33b95451"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jan 06 11:38:20 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jan 06 11:38:20 2009 -0700"
      },
      "message": "iop-adma: enable module removal\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n"
    },
    {
      "commit": "0d603f611d6515049fbceb0267ded43c33b95451",
      "tree": "6d5468c0b0a07f100e9cbbb901fd840ebe91b89d",
      "parents": [
        "f38822033d9eafd8a7b12dd7ad6dea26480ba339"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jan 06 11:38:20 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jan 06 11:38:20 2009 -0700"
      },
      "message": "iop-adma: kill debug BUG_ON\n\nThis BUG_ON caught problems in early development but now it is in the\nway as it invalidly triggers when trying to remove the module.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n"
    },
    {
      "commit": "f38822033d9eafd8a7b12dd7ad6dea26480ba339",
      "tree": "b8fb09a98b52a1519a038a9623928de59ec58e7f",
      "parents": [
        "7dd602510128d7a64b11ff3b7d4f30ac8e3946ce"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jan 06 11:38:19 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jan 06 11:38:19 2009 -0700"
      },
      "message": "iop-adma: let devm do its job, don\u0027t duplicate free\n\nNo need to free stuff that the devm infrastructure will take care of...\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n"
    },
    {
      "commit": "f27c580c3628d79b17f38976d842a6d7f3616e2e",
      "tree": "f1a1a96c1130e7e1c88f75cb5f5aab4c53fe0297",
      "parents": [
        "aa1e6f1a385eb2b04171ec841f3b760091e4a8ee"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jan 06 11:38:18 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jan 06 11:38:18 2009 -0700"
      },
      "message": "dmaengine: remove \u0027bigref\u0027 infrastructure\n\nReference counting is done at the module level so clients need not worry\nthat a channel will leave while they are actively using dmaengine.\n\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n"
    },
    {
      "commit": "aa1e6f1a385eb2b04171ec841f3b760091e4a8ee",
      "tree": "1401e7f1e867e5d4a769b648605e0317d25d5ccb",
      "parents": [
        "209b84a88fe81341b4d8d465acc4a67cb7c3feb3"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jan 06 11:38:17 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jan 06 11:38:17 2009 -0700"
      },
      "message": "dmaengine: kill struct dma_client and supporting infrastructure\n\nAll users have been converted to either the general-purpose allocator,\ndma_find_channel, or dma_request_channel.\n\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n\n\n"
    },
    {
      "commit": "07f2211e4fbce6990722d78c4f04225da9c0e9cf",
      "tree": "51934e20a334e93c8c399d2e6375f264551e9bc3",
      "parents": [
        "28405d8d9ce05f5bd869ef8b48da5086f9527d73"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Mon Jan 05 17:14:31 2009 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Mon Jan 05 18:10:19 2009 -0700"
      },
      "message": "dmaengine: remove dependency on async_tx\n\nasync_tx.ko is a consumer of dma channels.  A circular dependency arises\nif modules in drivers/dma rely on common code in async_tx.ko.  It\nprevents either module from being unloaded.\n\nMove dma_wait_for_async_tx and async_tx_run_dependencies to dmaeninge.o\nwhere they should have been from the beginning.\n\nReviewed-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n\n\n"
    },
    {
      "commit": "a06d568f7c5e40e34ea64881842deb8f4382babf",
      "tree": "15b38b4652705b7c58bd89052c81ab91ca94cc4a",
      "parents": [
        "b0b42b16ff2b90f17bc1a4308366c9beba4b276e"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Mon Dec 08 13:46:00 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Mon Dec 08 13:46:00 2008 -0700"
      },
      "message": "async_xor: dma_map destination DMA_BIDIRECTIONAL\n\nMapping the destination multiple times is a misuse of the dma-api.\nSince the destination may be reused as a source, ensure that it is only\nmapped once and that it is mapped bidirectionally.  This appears to add\nugliness on the unmap side in that it always reads back the destination\naddress from the descriptor, but gcc can determine that dma_unmap is a\nnop and not emit the code that calculates its arguments.\n\nCc: \u003cstable@kernel.org\u003e\nCc: Saeed Bishara \u003csaeed@marvell.com\u003e\nAcked-by: Yuri Tikhonov \u003cyur@emcraft.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "65e503814dec83c7b2ac955e75919d009109c919",
      "tree": "6cd01ca32ae269760d864d3c1bae94fdb0e95a45",
      "parents": [
        "137cb55c6dcd56cb367285adaf15f808a2a9fec7"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Nov 11 13:12:33 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Nov 11 13:12:33 2008 -0700"
      },
      "message": "iop-adma: use iop_paranoia() for debug BUG_ONs\n\nNow that the critical read back to flush the next descriptor address is\nfixed we can downgrade some BUG_ONs that need only be enabled when testing\nchanges to the driver.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "137cb55c6dcd56cb367285adaf15f808a2a9fec7",
      "tree": "4828887b960a451d7ab09a4250b472a2a9f97884",
      "parents": [
        "f21f237cf55494c3a4209de323281a3b0528da10"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Nov 11 13:12:33 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Nov 11 13:12:33 2008 -0700"
      },
      "message": "iop-adma: add a dummy read to flush next descriptor update\n\nThe current dummy read references the wrong address allowing the next\ndescriptor address update to linger in the store buffer and get passed\nby an \u0027append\u0027 event.\n\nThis issue was uncovered by the change from strongly-ordered to device\nmemory for the adma registers.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "a09e64fbc0094e3073dbb09c3b4bfe4ab669244b",
      "tree": "69689f467179891b498bd7423fcf61925173db31",
      "parents": [
        "a1b81a84fff05dbfef45b7012c26e1fee9973e5d"
      ],
      "author": {
        "name": "Russell King",
        "email": "rmk@dyn-67.arm.linux.org.uk",
        "time": "Tue Aug 05 16:14:15 2008 +0100"
      },
      "committer": {
        "name": "Russell King",
        "email": "rmk+kernel@arm.linux.org.uk",
        "time": "Thu Aug 07 09:55:48 2008 +0100"
      },
      "message": "[ARM] Move include/asm-arm/arch-* to arch/arm/*/include/mach\n\nThis just leaves include/asm-arm/plat-* to deal with.\n\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n"
    },
    {
      "commit": "5eb907aaaf7a316a0097ff9f8c21bf9fc468a1f1",
      "tree": "33238b492dc0f823e59586ca2a2ec981c3ba9f74",
      "parents": [
        "c7141d005a19d2a0a316b3bf9c170d3bedf07bfd"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Jul 17 17:59:56 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Jul 17 17:59:56 2008 -0700"
      },
      "message": "iop_adma: document how to calculate the minimum descriptor pool size\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "c7141d005a19d2a0a316b3bf9c170d3bedf07bfd",
      "tree": "cac1072c6230a3c8f33213802f399a70fdc7e882",
      "parents": [
        "0839875e0c197ded56bbae820e699f26d6fa2697"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Jul 17 17:59:56 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Jul 17 17:59:56 2008 -0700"
      },
      "message": "iop_adma: directly reclaim descriptors on allocation failure\n\nForce callers that trigger an \"out of descriptors\" condition to run the\ncleanup loop directly.  Alleviates the requirement to have soft-irqs\nenabled when polling for a descriptor in async_xor.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "e1d181efb14a93cf263d6c588a5395518edf3294",
      "tree": "1792d1faa7e344401789bbcfad8102d0d93036e2",
      "parents": [
        "848c536a37b8db4e461f14ca15fe29850151c822"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Fri Jul 04 00:13:40 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jul 08 11:59:12 2008 -0700"
      },
      "message": "dmaengine: add DMA_COMPL_SKIP_{SRC,DEST}_UNMAP flags to control dma unmap\n\nIn some cases client code may need the dma-driver to skip the unmap of source\nand/or destination buffers.  Setting these flags indicates to the driver to\nskip the unmap step.  In this regard async_xor is currently broken in that it\nallows the destination buffer to be unmapped while an operation is still in\nprogress, i.e. when the number of sources exceeds the hardware channel\u0027s\nmaximum (fixed in a subsequent patch).\n\nAcked-by: Saeed Bishara \u003csaeed@marvell.com\u003e\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nAcked-by: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "848c536a37b8db4e461f14ca15fe29850151c822",
      "tree": "f4a88e92e31de28511e3a3de99200a77d2613dae",
      "parents": [
        "4a776f0aa922a552460192c07b56f4fe9cd82632"
      ],
      "author": {
        "name": "Haavard Skinnemoen",
        "email": "haavard.skinnemoen@atmel.com",
        "time": "Tue Jul 08 11:58:58 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jul 08 11:58:58 2008 -0700"
      },
      "message": "dmaengine: Add dma_client parameter to device_alloc_chan_resources\n\nA DMA controller capable of doing slave transfers may need to know a\nfew things about the slave when preparing the channel. We don\u0027t want\nto add this information to struct dma_channel since the channel hasn\u0027t\nyet been bound to a client at this point.\n\nInstead, pass a reference to the client requesting the channel to the\ndriver\u0027s device_alloc_chan_resources hook so that it can pick the\nnecessary information from the dma_client struct by itself.\n\n[dan.j.williams@intel.com: fixed up fsldma and mv_xor]\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Haavard Skinnemoen \u003chaavard.skinnemoen@atmel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "ebabe2762607147d28aa395ea6df2a0ee7f795a1",
      "tree": "35b0292bb723a855846b0b1f7a20a6e14c77f1b4",
      "parents": [
        "7cc5bf9a3a84e5a02e23e5739fb894790b37c101"
      ],
      "author": {
        "name": "Kay Sievers",
        "email": "kay.sievers@vrfy.org",
        "time": "Tue Jul 08 11:58:28 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jul 08 11:58:28 2008 -0700"
      },
      "message": "iop-adma: fix platform driver hotplug/coldplug\n\nSince 43cc71eed1250755986da4c0f9898f9a635cb3bf, the platform\nmodalias is prefixed with \"platform:\". Add MODULE_ALIAS() to most\nof the hotpluggable platform drivers, to re-enable auto loading.\n\nCc: \u003cstable@kernel.org\u003e\nSigned-off-by: Kay Sievers \u003ckay.sievers@vrfy.org\u003e\nSigned-off-by: David Brownell \u003cdbrownell@users.sourceforge.net\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "eccf2144e1232c33a8235033ffa079b6ebf92faf",
      "tree": "870dece32d3a26405f335884ffee0276d23f4a65",
      "parents": [
        "76b0c788e6033c514f2a75171b04c73c68d28e8d"
      ],
      "author": {
        "name": "Christophe Jaillet",
        "email": "christophe.jaillet@wanadoo.fr",
        "time": "Tue May 20 16:33:06 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue May 20 13:51:20 2008 -0700"
      },
      "message": "iop-adma: fixup some kzalloc/memset confusions\n\n1) Remove an explicit memset(.., 0, ...) to a variable allocated with\nkzalloc (i.e. \u0027dest\u0027).\n\n2) Allocate \u0027src\u0027 with kmalloc instead of kzalloc as all elements of the\n\u0027src\u0027 buffer are initialized in a \u0027for(...)\u0027 loop just after.\n\n3) remove useless \u0027sizeof(u8)\u0027, which always returns 1, when computing the\nsize of the memory to be allocated.\n\nSigned-off-by: Christophe Jaillet \u003cchristophe.jaillet@wanadoo.fr\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "636bdeaa1243327501edfd2a597ed7443eb4239a",
      "tree": "59b894f124e3664ea4a537d7c07c527abdb9c8da",
      "parents": [
        "c4fe15541d0ef5cc8cc1ce43057663851f8fc387"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Apr 17 20:17:26 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Apr 17 13:25:54 2008 -0700"
      },
      "message": "dmaengine: ack to flags: make use of the unused bits in the \u0027ack\u0027 field\n\n\u0027ack\u0027 is currently a simple integer that flags whether or not a client is done\ntouching fields in the given descriptor.  It is effectively just a single bit\nof information.  Converting this to a flags parameter allows the other bits to\nbe put to use to control completion actions, like dma-unmap, and capture\nresults, like xor-zero-sum \u003d\u003d 0.\n\nChanges are one of:\n1/ convert all open-coded -\u003eack manipulations to use async_tx_ack\n   and async_tx_test_ack.\n2/ set the ack bit at prep time where possible\n3/ make drivers store the flags at prep time\n4/ add flags to the device_prep_dma_interrupt prototype\n\nAcked-by: Maciej Sosnowski \u003cmaciej.sosnowski@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "c4fe15541d0ef5cc8cc1ce43057663851f8fc387",
      "tree": "f54ffc254e1264ab7d33fe43e30078e6ecd36bd8",
      "parents": [
        "ce4d65a5db77e1568c82d5151a746f627c4f6ed5"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Apr 17 20:17:26 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Apr 17 13:25:54 2008 -0700"
      },
      "message": "iop-adma: remove the workaround for missed interrupts on iop3xx\n\nThis workaround was covering the dependency submission bug in async_tx.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "ce4d65a5db77e1568c82d5151a746f627c4f6ed5",
      "tree": "1f3936d2984fc03125bde025796465f9cada9075",
      "parents": [
        "19242d7233df7d658405d4b7ee1758d21414cfaa"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Apr 17 20:17:26 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Apr 17 13:25:54 2008 -0700"
      },
      "message": "async_tx: kill -\u003edevice_dependency_added\n\nDMA drivers no longer need to be notified of dependency submission\nevents as async_tx_run_dependencies and async_tx_channel_switch will\nhandle the scheduling and execution of dependent operations.\n\n[sfr@canb.auug.org.au: extend this for fsldma]\nAcked-by: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "19242d7233df7d658405d4b7ee1758d21414cfaa",
      "tree": "4bffa2700c30fdb454dfa150115a0607c6cf3d2a",
      "parents": [
        "1c62979ed29a8e2bf9fbe1db101c81a0089676f8"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Apr 17 20:17:25 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Apr 17 13:25:05 2008 -0700"
      },
      "message": "async_tx: fix multiple dependency submission\n\nShrink struct dma_async_tx_descriptor and introduce\nasync_tx_channel_switch to properly inject a channel switch interrupt in\nthe descriptor stream.  This simplifies the locking model as drivers no\nlonger need to handle dma_async_tx_descriptor.lock.\n\nAcked-by: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "3d9b525b69bc3302d8355e5f5cf081a856c211e0",
      "tree": "d0f8b4c9be02e4e48bc4bd0e099a6907eacf40ce",
      "parents": [
        "9c98718e7371fa781043d5a2e70cecebec048091"
      ],
      "author": {
        "name": "Harvey Harrison",
        "email": "harvey.harrison@gmail.com",
        "time": "Thu Mar 13 17:45:28 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Thu Mar 13 10:57:09 2008 -0700"
      },
      "message": "iop-adma.c: replace remaining __FUNCTION__ occurrences\n\n__FUNCTION__ is gcc-specific, use __func__\n\nSigned-off-by: Harvey Harrison \u003charvey.harrison@gmail.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "d4c56f97ff21df405d0cebe11f49e3c3c79662b5",
      "tree": "e6b0de433d7c985982ac12815998242a786d87b2",
      "parents": [
        "0036731c88fdb5bf4f04a796a30b5e445fc57f54"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sat Feb 02 19:49:58 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Feb 06 10:12:18 2008 -0700"
      },
      "message": "async_tx: replace \u0027int_en\u0027 with operation preparation flags\n\nPass a full set of flags to drivers\u0027 per-operation \u0027prep\u0027 routines.\nCurrently the only flag passed is DMA_PREP_INTERRUPT.  The expectation is\nthat arch-specific async_tx_find_channel() implementations can exploit this\ncapability to find the best channel for an operation.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nAcked-by: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\nReviewed-by: Haavard Skinnemoen \u003chskinnemoen@atmel.com\u003e\n"
    },
    {
      "commit": "0036731c88fdb5bf4f04a796a30b5e445fc57f54",
      "tree": "66982e4a9fdb92fedadca35c0ccaa0b9a75e9d2e",
      "parents": [
        "d909b347591a23c5a2c324fbccd4c9c966f31c67"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sat Feb 02 19:49:57 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Feb 06 10:12:17 2008 -0700"
      },
      "message": "async_tx: kill tx_set_src and tx_set_dest methods\n\nThe tx_set_src and tx_set_dest methods were originally implemented to allow\nan array of addresses to be passed down from async_xor to the dmaengine\ndriver while minimizing stack overhead.  Removing these methods allows\ndrivers to have all transaction parameters available at \u0027prep\u0027 time, saves\ntwo function pointers in struct dma_async_tx_descriptor, and reduces the\nnumber of indirect branches..\n\nA consequence of moving this data to the \u0027prep\u0027 routine is that\nmulti-source routines like async_xor need temporary storage to convert an\narray of linear addresses into an array of dma addresses.  In order to keep\nthe same stack footprint of the previous implementation the input array is\nreused as storage for the dma addresses.  This requires that\nsizeof(dma_addr_t) be less than or equal to sizeof(void *).  As a\nconsequence CONFIG_DMADEVICES now depends on !CONFIG_HIGHMEM64G.  It also\nrequires that drivers be able to make descriptor resources available when\nthe \u0027prep\u0027 routine is polled.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nAcked-by: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\n"
    },
    {
      "commit": "e73ef9acfd30f36bf7c60237ecffe7bbca8068d6",
      "tree": "bf949d319cb87ebc23ee26f650dcf1b39aa794e0",
      "parents": [
        "cf8f68aa76e8e12f9dcbba3ffe61fb9f2a3a0c2b"
      ],
      "author": {
        "name": "Denis Cheng",
        "email": "crquan@gmail.com",
        "time": "Sat Feb 02 19:30:01 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Feb 06 10:12:17 2008 -0700"
      },
      "message": "iop-adma: use LIST_HEAD instead of LIST_HEAD_INIT\n\nthese three list_head are all local variables, but can also use LIST_HEAD.\n\nSigned-off-by: Denis Cheng \u003ccrquan@gmail.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "af49d9248fca6f26cbdb01918334f71d9040df80",
      "tree": "5d6a7f4d5ca55ff17fbfc98cacac37be62c7a4a3",
      "parents": [
        "d9c9bef1345e5d9258febce2a37e4d40319fa728"
      ],
      "author": {
        "name": "Rusty Russell",
        "email": "rusty@rustcorp.com.au",
        "time": "Tue Oct 16 23:26:27 2007 -0700"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@woody.linux-foundation.org",
        "time": "Wed Oct 17 08:42:49 2007 -0700"
      },
      "message": "Remove \"unsafe\" from module struct\n\nAdrian Bunk points out that \"unsafe\" was used to mark modules touched by\nthe deprecated MOD_INC_USE_COUNT interface, which has long gone.  It\u0027s time\nto remove the member from the module structure, as well.\n\nIf you want a module which can\u0027t unload, don\u0027t register an exit function.\n\n(Vlad Yasevich says SCTP is now safe to unload, so just remove the\n__unsafe there).\n\nSigned-off-by: Rusty Russell \u003crusty@rustcorp.com.au\u003e\nAcked-by: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\nAcked-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nAcked-by: Vlad Yasevich \u003cvladislav.yasevich@hp.com\u003e\nCc: Sridhar Samudrala \u003csri@us.ibm.com\u003e\nCc: Adrian Bunk \u003cbunk@stusta.de\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n"
    },
    {
      "commit": "c211092313b90f898dec61f35207fc282d1eadc3",
      "tree": "30df0c81f207d0babb3fe56a17419f37e71e973a",
      "parents": [
        "f6dff381af01006ffae3c23cd2e07e30584de0ec"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jan 02 13:52:26 2007 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Fri Jul 13 08:06:18 2007 -0700"
      },
      "message": "dmaengine: driver for the iop32x, iop33x, and iop13xx raid engines\n\nThe Intel(R) IOP series of i/o processors integrate an Xscale core with\nraid acceleration engines.  The capabilities per platform are:\n\niop219:\n (2) copy engines\niop321:\n (2) copy engines\n (1) xor and block fill engine\niop33x:\n (2) copy and crc32c engines\n (1) xor, xor zero sum, pq, pq zero sum, and block fill engine\niop34x (iop13xx):\n (2) copy, crc32c, xor, xor zero sum, and block fill engines\n (1) copy, crc32c, xor, xor zero sum, pq, pq zero sum, and block fill engine\n\nThe driver supports the features of the async_tx api:\n* asynchronous notification of operation completion\n* implicit (interupt triggered) handling of inter-channel transaction\n  dependencies\n\nThe driver adapts to the platform it is running by two methods.\n1/ #include \u003casm/arch/adma.h\u003e which defines the hardware specific\n   iop_chan_* and iop_desc_* routines as a series of static inline\n   functions\n2/ The private platform data attached to the platform_device defines the\n   capabilities of the channels\n\n20070626: Callbacks are run in a tasklet.  Given the recent discussion on\nLKML about killing tasklets in favor of workqueues I did a quick conversion\nof the driver.  Raid5 resync performance dropped from 50MB/s to 30MB/s, so\nthe tasklet implementation remains until a generic softirq interface is\navailable.\n\nChangelog:\n* fixed a slot allocation bug in do_iop13xx_adma_xor that caused too few\nslots to be requested eventually leading to data corruption\n* enabled the slot allocation routine to attempt to free slots before\nreturning -ENOMEM\n* switched the cleanup routine to solely use the software chain and the\nstatus register to determine if a descriptor is complete.  This is\nnecessary to support other IOP engines that do not have status writeback\ncapability\n* make the driver iop generic\n* modified the allocation routines to understand allocating a group of\nslots for a single operation\n* added a null xor initialization operation for the xor only channel on\niop3xx\n* support xor operations on buffers larger than the hardware maximum\n* split the do_* routines into separate prep, src/dest set, submit stages\n* added async_tx support (dependent operations initiation at cleanup time)\n* simplified group handling\n* added interrupt support (callbacks via tasklets)\n* brought the pending depth inline with ioat (i.e. 4 descriptors)\n* drop dma mapping methods, suggested by Chris Leech\n* don\u0027t use inline in C files, Adrian Bunk\n* remove static tasklet declarations\n* make iop_adma_alloc_slots easier to read and remove chances for a\n  corrupted descriptor chain\n* fix locking bug in iop_adma_alloc_chan_resources, Benjamin Herrenschmidt\n* convert capabilities over to dma_cap_mask_t\n* fixup sparse warnings\n* add descriptor flush before iop_chan_enable\n* checkpatch.pl fixes\n* gpl v2 only correction\n* move set_src, set_dest, submit to async_tx methods\n* move group_list and phys to async_tx\n\nCc: Russell King \u003crmk@arm.linux.org.uk\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    }
  ]
}