)]}' { "log": [ { "commit": "f007e99c8e2e322b8331aba72414715119a2920d", "tree": "616bfcdda74341dc8b5d9ea1013bb7506407a961", "parents": [ "c4658b4e777bebf69884f4884a9bfb2f84dd71d9" ], "author": { "name": "Weidong Han", "email": "weidong.han@intel.com", "time": "Sat May 23 00:41:15 2009 +0800" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Tue Jun 23 22:09:17 2009 +0100" }, "message": "Intel-IOMMU, intr-remap: source-id checking\n\nTo support domain-isolation usages, the platform hardware must be\ncapable of uniquely identifying the requestor (source-id) for each\ninterrupt message. Without source-id checking for interrupt remapping\n, a rouge guest/VM with assigned devices can launch interrupt attacks\nto bring down anothe guest/VM or the VMM itself.\n\nThis patch adds source-id checking for interrupt remapping, and then\nreally isolates interrupts for guests/VMs with assigned devices.\n\nBecause PCI subsystem is not initialized yet when set up IOAPIC\nentries, use read_pci_config_byte to access PCI config space directly.\n\nSigned-off-by: Weidong Han \u003cweidong.han@intel.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "687d680985b1438360a9ba470ece8b57cd205c3b", "tree": "ae253608531e5c3e823600974c610e722e7de759", "parents": [ "1053414068bad659479e6efa62a67403b8b1ec0a", "008fe148cb0fb51d266baabe2c09997b21cf90c6" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Jun 22 21:38:22 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Jun 22 21:38:22 2009 -0700" }, "message": "Merge git://git.infradead.org/~dwmw2/iommu-2.6.31\n\n* git://git.infradead.org/~dwmw2/iommu-2.6.31:\n intel-iommu: Fix one last ia64 build problem in Pass Through Support\n VT-d: support the device IOTLB\n VT-d: cleanup iommu_flush_iotlb_psi and flush_unmaps\n VT-d: add device IOTLB invalidation support\n VT-d: parse ATSR in DMA Remapping Reporting Structure\n PCI: handle Virtual Function ATS enabling\n PCI: support the ATS capability\n intel-iommu: dmar_set_interrupt return error value\n intel-iommu: Tidy up iommu-\u003egcmd handling\n intel-iommu: Fix tiny theoretical race in write-buffer flush.\n intel-iommu: Clean up handling of \"caching mode\" vs. IOTLB flushing.\n intel-iommu: Clean up handling of \"caching mode\" vs. context flushing.\n VT-d: fix invalid domain id for KVM context flush\n Fix !CONFIG_DMAR build failure introduced by Intel IOMMU Pass Through Support\n Intel IOMMU Pass Through Support\n\nFix up trivial conflicts in drivers/pci/{intel-iommu.c,intr_remapping.c}\n" }, { "commit": "aa5d2b515b6fca5f8a56eac84f7fa0a68c1ce9b7", "tree": "c98753254dfe2f3e54a4c38c9191ab5f4afb4c39", "parents": [ "e277d2fc79d6abb86fafadb58dca0b9c498a9aa7" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Mon May 18 13:51:34 2009 +0800" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon May 18 14:45:09 2009 +0100" }, "message": "VT-d: parse ATSR in DMA Remapping Reporting Structure\n\nParse the Root Port ATS Capability Reporting Structure in the DMA\nRemapping Reporting Structure ACPI table.\n\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "fc1edaf9e7cc4d4696f83dee495b8f158d01c4eb", "tree": "c5a361ca44205b6341c03427816876e10b07f7c5", "parents": [ "667c5296cc76fefe0abcb79228952b28d9af45e3" ], "author": { "name": "Suresh Siddha", "email": "suresh.b.siddha@intel.com", "time": "Mon Apr 20 13:02:27 2009 -0700" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Tue Apr 21 09:08:25 2009 +0200" }, "message": "x86: x2apic, IR: Clean up X86_X2APIC and INTR_REMAP config checks\n\nAdd x2apic_supported() to clean up CONFIG_X86_X2APIC checks.\n\nFix CONFIG_INTR_REMAP checks.\n\n[ Impact: cleanup ]\n\nSigned-off-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nCc: dwmw2@infradead.org\nCc: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nCc: Weidong Han \u003cweidong.han@intel.com\u003e\nLKML-Reference: \u003c20090420200450.128993000@linux-os.sc.intel.com\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "937582382c71b75b29fbb92615629494e1a05ac0", "tree": "e73af8d10d388fcc78d19534611db66233907a9e", "parents": [ "5d0ae2db6deac4f15dac4f42f23bc56448fc8d4d" ], "author": { "name": "Weidong Han", "email": "weidong.han@intel.com", "time": "Fri Apr 17 16:42:14 2009 +0800" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Sun Apr 19 10:21:43 2009 +0200" }, "message": "x86, intr-remap: enable interrupt remapping early\n\nCurrently, when x2apic is not enabled, interrupt remapping\nwill be enabled in init_dmars(), where it is too late to remap\nioapic interrupts, that is, ioapic interrupts are really in\ncompatibility mode, not remappable mode.\n\nThis patch always enables interrupt remapping before ioapic\nsetup, it guarantees all interrupts will be remapped when\ninterrupt remapping is enabled. Thus it doesn\u0027t need to set\nthe compatibility interrupt bit.\n\n[ Impact: refactor intr-remap init sequence, enable fuller remap mode ]\n\nSigned-off-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nSigned-off-by: Weidong Han \u003cweidong.han@intel.com\u003e\nAcked-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\nCc: iommu@lists.linux-foundation.org\nCc: allen.m.kay@intel.com\nCc: fenghua.yu@intel.com\nLKML-Reference: \u003c1239957736-6161-4-git-send-email-weidong.han@intel.com\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "276dbf997043cbf38f0087624e0f9c51742c8885", "tree": "eface2519a6ad4c25c2864ee1ee69361ea3f594c", "parents": [ "924b6231edfaf1e764ffb4f97ea382bf4facff58" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Apr 04 01:45:37 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Sat Apr 04 10:43:31 2009 +0100" }, "message": "intel-iommu: Handle PCI domains appropriately.\n\nWe were comparing {bus,devfn} and assuming that a match meant it was the\nsame device. It doesn\u0027t -- the same {bus,devfn} can exist in\nmultiple PCI domains. Include domain number in device identification\n(and call it \u0027segment\u0027 in most places, because there\u0027s already a lot of\nreferences to \u0027domain\u0027 which means something else, and this code is\ninfected with ACPI thinking already).\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "b24696bc55f66fecc30715e003f10fc2555a9271", "tree": "3ef565bf041a06106a73d0b27ccc256845ef5644", "parents": [ "eb4a52bc660ea835482c582eaaf4893742cbd160" ], "author": { "name": "Fenghua Yu", "email": "fenghua.yu@intel.com", "time": "Fri Mar 27 14:22:44 2009 -0700" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Fri Apr 03 21:45:59 2009 +0100" }, "message": "Intel IOMMU Suspend/Resume Support - Interrupt Remapping\n\nThis patch enables suspend/resume for interrupt remapping. During suspend,\ninterrupt remapping is disabled. When resume, interrupt remapping is enabled\nagain.\n\nSigned-off-by: Fenghua Yu \u003cfenghua.yu@intel.com\u003e\nAcked-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "8f912ba4d7cdaf7d31cf39fe5a9b7732308a256d", "tree": "2f2e63e48c32471d729289c0772be1a093529228", "parents": [ "20bec8ab1458c24bed0d5492ee15d87807fc415a" ], "author": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Fri Apr 03 15:19:32 2009 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Fri Apr 03 21:45:46 2009 +0100" }, "message": "intel-iommu: Add for_each_iommu() and for_each_active_iommu() macros\n\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\nAcked-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "29b61be65a33c95564fa82e7e8d60d97adb68ea8", "tree": "2a9898b3ff1c04805d2bb876061c00052c9647bc", "parents": [ "0280f7c416c652a2fd95d166f52b199ae61122c0" ], "author": { "name": "Suresh Siddha", "email": "suresh.b.siddha@intel.com", "time": "Mon Mar 16 17:05:02 2009 -0700" }, "committer": { "name": "H. Peter Anvin", "email": "hpa@linux.intel.com", "time": "Tue Mar 17 15:45:07 2009 -0700" }, "message": "x86, x2apic: cleanup ifdef CONFIG_INTR_REMAP in io_apic code\n\nImpact: cleanup\n\nClean up #ifdefs and replace them with helper functions.\n\nSigned-off-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nSigned-off-by: H. Peter Anvin \u003chpa@linux.intel.com\u003e\n" }, { "commit": "1531a6a6b81a4e6f9eec9a5608758a6ea14b96e0", "tree": "3b1523516192fdd19b286879376b4d3d7c827b0d", "parents": [ "eba67e5da6e971993b2899d2cdf459ce77d3dbc5" ], "author": { "name": "Suresh Siddha", "email": "suresh.b.siddha@intel.com", "time": "Mon Mar 16 17:04:57 2009 -0700" }, "committer": { "name": "H. Peter Anvin", "email": "hpa@linux.intel.com", "time": "Tue Mar 17 15:39:58 2009 -0700" }, "message": "x86, dmar: start with sane state while enabling dma and interrupt-remapping\n\nImpact: cleanup/sanitization\n\nStart from a sane state while enabling dma and interrupt-remapping, by\nclearing the previous recorded faults and disabling previously\nenabled queued invalidation and interrupt-remapping.\n\nSigned-off-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nSigned-off-by: H. Peter Anvin \u003chpa@linux.intel.com\u003e\n" }, { "commit": "9d783ba042771284fb4ee5013c3d94220755ae7f", "tree": "102ec9f89d363589108ae35e4b38c12fc6e2765c", "parents": [ "0ac2491f57af5644f88383d28809760902d6f4d7" ], "author": { "name": "Suresh Siddha", "email": "suresh.b.siddha@intel.com", "time": "Mon Mar 16 17:04:55 2009 -0700" }, "committer": { "name": "H. Peter Anvin", "email": "hpa@linux.intel.com", "time": "Tue Mar 17 15:38:59 2009 -0700" }, "message": "x86, x2apic: enable fault handling for intr-remapping\n\nImpact: interface augmentation (not yet used)\n\nEnable fault handling flow for intr-remapping aswell. Fault handling\ncode now shared by both dma-remapping and intr-remapping.\n\nSigned-off-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nSigned-off-by: H. Peter Anvin \u003chpa@linux.intel.com\u003e\n" }, { "commit": "58fa7304a2c2bfd46e505c293ef779aa1d9715c2", "tree": "924dcf821a9ec6e1601d5e0b7c22bbbeaf0f3634", "parents": [ "a647dacbb1389aa6a5fa631766c1eaea35905890" ], "author": { "name": "Mark McLoughlin", "email": "markmc@redhat.com", "time": "Thu Nov 20 15:49:49 2008 +0000" }, "committer": { "name": "Joerg Roedel", "email": "joerg.roedel@amd.com", "time": "Sat Jan 03 11:57:35 2009 +0100" }, "message": "intel-iommu: kill off duplicate def of dmar_disabled\n\nThis is only used in dmar.c and intel-iommu.h, so dma_remapping.h\nseems like the appropriate place for it.\n\nSigned-off-by: Mark McLoughlin \u003cmarkmc@redhat.com\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "f6dd5c3106fb283e37d915eeb33019ef40510f85", "tree": "61d95e10b63847c8dfdc13e40e7e3291427d3123", "parents": [ "a11b5abef50722e42a7d13f6b799c4f606fcb797" ], "author": { "name": "Yinghai Lu", "email": "yhlu.kernel@gmail.com", "time": "Wed Sep 03 16:58:32 2008 -0700" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Thu Oct 16 16:53:04 2008 +0200" }, "message": "dmar: fix using early fixmap mapping for DMAR table parsing\n\nVery early detection of the DMAR tables will setup fixmap mapping. For\nparsing these tables later (while enabling dma and/or interrupt remapping),\nearly fixmap mapping shouldn\u0027t be used. Fix it by calling table detection\nroutines again, which will call generic apci_get_table() for setting up\nthe correct mapping.\n\nSigned-off-by: Yinghai Lu \u003cyhlu.kernel@gmail.com\u003e\nSigned-off-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "75c46fa61bc5b4ccd20a168ff325c58771248fcd", "tree": "ff5abfe689fe732ad73a198e1f3e56b8c4ca6024", "parents": [ "89027d35aa5b8f45ce0f7fa0911db85b46563da0" ], "author": { "name": "Suresh Siddha", "email": "suresh.b.siddha@intel.com", "time": "Thu Jul 10 11:16:57 2008 -0700" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Sat Jul 12 08:45:05 2008 +0200" }, "message": "x64, x2apic/intr-remap: MSI and MSI-X support for interrupt remapping infrastructure\n\nMSI and MSI-X support for interrupt remapping infrastructure.\n\nMSI address register will be programmed with interrupt-remapping table\nentry(IRTE) index and the IRTE will contain information about the vector,\ncpu destination, etc.\n\nFor MSI-X, all the IRTE\u0027s will be consecutively allocated in the table,\nand the address registers will contain the starting index to the block\nand the data register will contain the subindex with in that block.\n\nThis also introduces a new irq_chip for cleaner irq migration (in the process\ncontext as opposed to the current irq migration in the context of an interrupt.\ninterrupt-remapping infrastructure will help us achieve this).\n\nAs MSI is edge triggered, irq migration is a simple atomic update(of vector\nand cpu destination) of IRTE and flushing the hardware cache.\n\nSigned-off-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nCc: akpm@linux-foundation.org\nCc: arjan@linux.intel.com\nCc: andi@firstfloor.org\nCc: ebiederm@xmission.com\nCc: jbarnes@virtuousgeek.org\nCc: steiner@sgi.com\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "89027d35aa5b8f45ce0f7fa0911db85b46563da0", "tree": "bf2f9570231bbd4cc2cd24247059fdb72bdee57e", "parents": [ "5c520a6724e912a7e6153b7597192edad6752750" ], "author": { "name": "Suresh Siddha", "email": "suresh.b.siddha@intel.com", "time": "Thu Jul 10 11:16:56 2008 -0700" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Sat Jul 12 08:45:05 2008 +0200" }, "message": "x64, x2apic/intr-remap: IO-APIC support for interrupt-remapping\n\nIO-APIC support in the presence of interrupt-remapping infrastructure.\n\nIO-APIC RTE will be programmed with interrupt-remapping table entry(IRTE)\nindex and the IRTE will contain information about the vector, cpu destination,\ntrigger mode etc, which traditionally was present in the IO-APIC RTE.\n\nIntroduce a new irq_chip for cleaner irq migration (in the process\ncontext as opposed to the current irq migration in the context of an interrupt.\ninterrupt-remapping infrastructure will help us achieve this cleanly).\n\nFor edge triggered, irq migration is a simple atomic update(of vector\nand cpu destination) of IRTE and flush the hardware cache.\n\nFor level triggered, we need to modify the io-apic RTE aswell with the update\nvector information, along with modifying IRTE with vector and cpu destination.\nSo irq migration for level triggered is little bit more complex compared to\nedge triggered migration. But the good news is, we use the same algorithm\nfor level triggered migration as we have today, only difference being,\nwe now initiate the irq migration from process context instead of the\ninterrupt context.\n\nIn future, when we do a directed EOI (combined with cpu EOI broadcast\nsuppression) to the IO-APIC, level triggered irq migration will also be\nas simple as edge triggered migration and we can do the irq migration\nwith a simple atomic update to IO-APIC RTE.\n\nTBD: some tests/changes needed in the presence of fixup_irqs() for\nlevel triggered irq migration.\n\nSigned-off-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nCc: akpm@linux-foundation.org\nCc: arjan@linux.intel.com\nCc: andi@firstfloor.org\nCc: ebiederm@xmission.com\nCc: jbarnes@virtuousgeek.org\nCc: steiner@sgi.com\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "b6fcb33ad6c05f152a672f7c96c1fab006527b80", "tree": "9926a4914b7d929f31794315dc21768f38c3628e", "parents": [ "2ae21010694e56461a63bfc80e960090ce0a5ed9" ], "author": { "name": "Suresh Siddha", "email": "suresh.b.siddha@intel.com", "time": "Thu Jul 10 11:16:44 2008 -0700" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Sat Jul 12 08:44:54 2008 +0200" }, "message": "x64, x2apic/intr-remap: routines managing Interrupt remapping table entries.\n\nRoutines handling the management of interrupt remapping table entries.\n\nSigned-off-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nCc: akpm@linux-foundation.org\nCc: arjan@linux.intel.com\nCc: andi@firstfloor.org\nCc: ebiederm@xmission.com\nCc: jbarnes@virtuousgeek.org\nCc: steiner@sgi.com\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "2ae21010694e56461a63bfc80e960090ce0a5ed9", "tree": "d4ecdb710c4361df473b063eda9e1426fcf5c309", "parents": [ "fe962e90cb17a8426e144dee970e77ed789d98ee" ], "author": { "name": "Suresh Siddha", "email": "suresh.b.siddha@intel.com", "time": "Thu Jul 10 11:16:43 2008 -0700" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Sat Jul 12 08:44:53 2008 +0200" }, "message": "x64, x2apic/intr-remap: Interrupt remapping infrastructure\n\nInterrupt remapping (part of Intel Virtualization Tech for directed I/O)\ninfrastructure.\n\nSigned-off-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nCc: akpm@linux-foundation.org\nCc: arjan@linux.intel.com\nCc: andi@firstfloor.org\nCc: ebiederm@xmission.com\nCc: jbarnes@virtuousgeek.org\nCc: steiner@sgi.com\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "ad3ad3f6a2caebf56869b83b69e23eb9fa5e0ab6", "tree": "7bc99dde6a6313eb43783086a33f6eebc1da1907", "parents": [ "2d6b5f85bb4ca919d8ab0f30311309b53fb93bc3" ], "author": { "name": "Suresh Siddha", "email": "suresh.b.siddha@intel.com", "time": "Thu Jul 10 11:16:40 2008 -0700" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Sat Jul 12 08:44:50 2008 +0200" }, "message": "x64, x2apic/intr-remap: parse ioapic scope under vt-d structures\n\nParse the vt-d device scope structures to find the mapping between IO-APICs\nand the interrupt remapping hardware units.\n\nThis will be used later for enabling Interrupt-remapping for IOAPIC devices.\n\nSigned-off-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nCc: akpm@linux-foundation.org\nCc: arjan@linux.intel.com\nCc: andi@firstfloor.org\nCc: ebiederm@xmission.com\nCc: jbarnes@virtuousgeek.org\nCc: steiner@sgi.com\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "1886e8a90a580f3ad343f2065c84c1b9e1dac9ef", "tree": "1f0a6b536a1bb7b24585973e70ad8e1a9a076f09", "parents": [ "c42d9f32443397aed2d37d37df161392e6a5862f" ], "author": { "name": "Suresh Siddha", "email": "suresh.b.siddha@intel.com", "time": "Thu Jul 10 11:16:37 2008 -0700" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Sat Jul 12 08:44:48 2008 +0200" }, "message": "x64, x2apic/intr-remap: code re-structuring, to be used by both DMA and Interrupt remapping\n\nAllocate the iommu during the parse of DMA remapping hardware\ndefinition structures. And also, introduce routines for device\nscope initialization which will be explicitly called during\ndma-remapping initialization.\n\nThese will be used for enabling interrupt remapping separately from the\nexisting DMA-remapping enabling sequence.\n\nSigned-off-by: Suresh Siddha \u003csuresh.b.siddha@intel.com\u003e\nCc: akpm@linux-foundation.org\nCc: arjan@linux.intel.com\nCc: andi@firstfloor.org\nCc: ebiederm@xmission.com\nCc: jbarnes@virtuousgeek.org\nCc: steiner@sgi.com\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n" }, { "commit": "d94afc6ccf6690b30ae112ec8101b3f10d50114e", "tree": "f54fb1fe147861db876b99809ff1cd1a316c45c0", "parents": [ "f8bab73515ca5b392680bb033dceeb37b8463e95" ], "author": { "name": "mark gross", "email": "mgross@linux.intel.com", "time": "Fri Feb 08 04:18:39 2008 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Fri Feb 08 09:22:24 2008 -0800" }, "message": "intel-iommu: fault_reason index cleanup\n\nFix an off by one bug in the fault reason string reporting function, and\nclean up some of the code around this buglet.\n\n[akpm@linux-foundation.org: cleanup]\nSigned-off-by: mark gross \u003cmgross@linux.intel.com\u003e\nCc: Ingo Molnar \u003cmingo@elte.hu\u003e\nCc: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: Andi Kleen \u003cak@suse.de\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "3460a6d9cef9ac2aa997da7eff7ff1c8291b361c", "tree": "3cf7eb916456d781d2edb135f9069f7c94d10085", "parents": [ "7d3b03ce7bff9d39ebaee1bb8de1968c4434b883" ], "author": { "name": "Keshavamurthy, Anil S", "email": "anil.s.keshavamurthy@intel.com", "time": "Sun Oct 21 16:41:54 2007 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Mon Oct 22 08:13:19 2007 -0700" }, "message": "Intel IOMMU: DMAR fault handling support\n\nMSI interrupt handler registrations and fault handling support for Intel-IOMMU\nhadrware.\n\nThis patch enables the MSI interrupts for the DMA remapping units and in the\ninterrupt handler read the fault cause and outputs the same on to the console.\n\nSigned-off-by: Anil S Keshavamurthy \u003canil.s.keshavamurthy@intel.com\u003e\nCc: Andi Kleen \u003cak@suse.de\u003e\nCc: Peter Zijlstra \u003ca.p.zijlstra@chello.nl\u003e\nCc: Muli Ben-Yehuda \u003cmuli@il.ibm.com\u003e\nCc: \"Siddha, Suresh B\" \u003csuresh.b.siddha@intel.com\u003e\nCc: Arjan van de Ven \u003carjan@infradead.org\u003e\nCc: Ashok Raj \u003cashok.raj@intel.com\u003e\nCc: \"David S. Miller\" \u003cdavem@davemloft.net\u003e\nCc: Christoph Lameter \u003cclameter@sgi.com\u003e\nCc: Greg KH \u003cgreg@kroah.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "ba39592764ed20cee09aae5352e603a27bf56b0d", "tree": "efe7ec88bbd4d6b08b639830352c68411a7ef7fb", "parents": [ "f8de50eb6b085572ea773f26e066835ea3d3028b" ], "author": { "name": "Keshavamurthy, Anil S", "email": "anil.s.keshavamurthy@intel.com", "time": "Sun Oct 21 16:41:49 2007 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Mon Oct 22 08:13:18 2007 -0700" }, "message": "Intel IOMMU: Intel IOMMU driver\n\nActual intel IOMMU driver. Hardware spec can be found at:\nhttp://www.intel.com/technology/virtualization\n\nThis driver sets X86_64 \u0027dma_ops\u0027, so hook into standard DMA APIs. In this\nway, PCI driver will get virtual DMA address. This change is transparent to\nPCI drivers.\n\n[akpm@linux-foundation.org: remove unneeded cast]\n[akpm@linux-foundation.org: build fix]\n[bunk@stusta.de: fix duplicate CONFIG_DMAR Makefile line]\nSigned-off-by: Anil S Keshavamurthy \u003canil.s.keshavamurthy@intel.com\u003e\nCc: Andi Kleen \u003cak@suse.de\u003e\nCc: Peter Zijlstra \u003ca.p.zijlstra@chello.nl\u003e\nCc: Muli Ben-Yehuda \u003cmuli@il.ibm.com\u003e\nCc: \"Siddha, Suresh B\" \u003csuresh.b.siddha@intel.com\u003e\nCc: Arjan van de Ven \u003carjan@infradead.org\u003e\nCc: Ashok Raj \u003cashok.raj@intel.com\u003e\nCc: \"David S. Miller\" \u003cdavem@davemloft.net\u003e\nCc: Christoph Lameter \u003cclameter@sgi.com\u003e\nCc: Greg KH \u003cgreg@kroah.com\u003e\nSigned-off-by: Adrian Bunk \u003cbunk@stusta.de\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "10e5247f40f3bf7508a0ed2848c9cae37bddf4bc", "tree": "adca606f00ebcbdbdc5c474f012105d7e59152f6", "parents": [ "89910cccb8fec0c1140d33a743e72a712efd4f05" ], "author": { "name": "Keshavamurthy, Anil S", "email": "anil.s.keshavamurthy@intel.com", "time": "Sun Oct 21 16:41:41 2007 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Mon Oct 22 08:13:18 2007 -0700" }, "message": "Intel IOMMU: DMAR detection and parsing logic\n\nThis patch supports the upcomming Intel IOMMU hardware a.k.a. Intel(R)\nVirtualization Technology for Directed I/O Architecture and the hardware spec\nfor the same can be found here\nhttp://www.intel.com/technology/virtualization/index.htm\n\nFAQ! (questions from akpm, answers from ak)\n\n\u003e So... what\u0027s all this code for?\n\u003e\n\u003e I assume that the intent here is to speed things up under Xen, etc?\n\nYes in some cases, but not this code. That would be the Xen version of this\ncode that could potentially assign whole devices to guests. I expect this to\nbe only useful in some special cases though because most hardware is not\nvirtualizable and you typically want an own instance for each guest.\n\nOk at some point KVM might implement this too; i likely would use this code\nfor this.\n\n\u003e Do we\n\u003e have any benchmark results to help us to decide whether a merge would be\n\u003e justified?\n\nThe main advantage for doing it in the normal kernel is not performance, but\nmore safety. Broken devices won\u0027t be able to corrupt memory by doing random\nDMA.\n\nUnfortunately that doesn\u0027t work for graphics yet, for that need user space\ninterfaces for the X server are needed.\n\nThere are some potential performance benefits too:\n\n- When you have a device that cannot address the complete address range an\n IOMMU can remap its memory instead of bounce buffering. Remapping is likely\n cheaper than copying.\n\n- The IOMMU can merge sg lists into a single virtual block. This could\n potentially speed up SG IO when the device is slow walking SG lists. [I\n long ago benchmarked 5% on some block benchmark with an old MPT Fusion; but\n it probably depends a lot on the HBA]\n\nAnd you get better driver debugging because unexpected memory accesses from\nthe devices will cause a trappable event.\n\n\u003e\n\u003e Does it slow anything down?\n\nIt adds more overhead to each IO so yes.\n\nThis patch:\n\nAdd support for early detection and parsing of DMAR\u0027s (DMA Remapping) reported\nto OS via ACPI tables.\n\nDMA remapping(DMAR) devices support enables independent address translations\nfor Direct Memory Access(DMA) from Devices. These DMA remapping devices are\nreported via ACPI tables and includes pci device scope covered by these DMA\nremapping device.\n\nFor detailed info on the specification of \"Intel(R) Virtualization Technology\nfor Directed I/O Architecture\" please see\nhttp://www.intel.com/technology/virtualization/index.htm\n\nSigned-off-by: Anil S Keshavamurthy \u003canil.s.keshavamurthy@intel.com\u003e\nCc: Andi Kleen \u003cak@suse.de\u003e\nCc: Peter Zijlstra \u003ca.p.zijlstra@chello.nl\u003e\nCc: Muli Ben-Yehuda \u003cmuli@il.ibm.com\u003e\nCc: \"Siddha, Suresh B\" \u003csuresh.b.siddha@intel.com\u003e\nCc: Arjan van de Ven \u003carjan@infradead.org\u003e\nCc: Ashok Raj \u003cashok.raj@intel.com\u003e\nCc: \"David S. Miller\" \u003cdavem@davemloft.net\u003e\nCc: Christoph Lameter \u003cclameter@sgi.com\u003e\nCc: Greg KH \u003cgreg@kroah.com\u003e\nCc: Len Brown \u003clenb@kernel.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" } ] }