)]}' { "log": [ { "commit": "bf4d29086972ceaeaf72544d8f64933c2cfdc992", "tree": "301ee83217bc9a19cef5c7569801095b4d6f89b4", "parents": [ "1bcd495be9ed3194f618e8af0446459dc52a1423" ], "author": { "name": "Matthew Garrett", "email": "mjg@redhat.com", "time": "Mon Oct 04 14:22:26 2010 -0400" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Sun Oct 17 20:03:06 2010 -0700" }, "message": "PCI: Export some PCI PM functionality\n\nIt\u0027s helpful to have some extra PCI power management functions available to\nplatform code, so move the declarations to an exported header.\n\nAcked-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Matthew Garrett \u003cmjg@redhat.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "42b219322a97ccef347388b233aceaafe3fa517d", "tree": "eb810f27080a9eab5cee2e52413fcc46788d7a15", "parents": [ "5a37f1381f1d8625fa458360c9b5d17f0c5f1dea" ], "author": { "name": "Stephen Hemminger", "email": "shemminger@vyatta.com", "time": "Thu Sep 02 14:28:51 2010 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Oct 15 13:09:49 2010 -0700" }, "message": "PCI: pci_driver make name const\n\nThe name field in pci_driver should be const, it is not\nmodified by PCI subsystem.\n\nSigned-off-by: Stephen Hemminger \u003cshemminger@vyatta.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "92298e668372f2f6c8a79fb272f13d65161a4876", "tree": "0e7a20da42b5fba01873cba65141f0c947f953ff", "parents": [ "2be1f3a73dd02e38e181cf5abacb3d45a6a2d6b8" ], "author": { "name": "Dave Airlie", "email": "airlied@gmail.com", "time": "Fri Aug 13 10:22:17 2010 +1000" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Aug 13 16:19:59 2010 -0700" }, "message": "PCI: provide stub pci_domain_nr function for !CONFIG_PCI configs\n\nAllows the new PCI domain aware DRM code to compile on m68k.\n\nReported-by: Geert Uytterhoeven \u003cgeert@linux-m68k.org\u003e\nSigned-off-by: Dave Airlie \u003cairlied@gmail.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "253d2e549818f5a4a52e2db0aba3dacee21e5b38", "tree": "535ff224cb89860809fa5d948e19e1f3342cf7b3", "parents": [ "fcd097f31a6ee207cc0c3da9cccd2a86d4334785" ], "author": { "name": "Jacob Pan", "email": "jacob.jun.pan@linux.intel.com", "time": "Fri Jul 16 10:19:22 2010 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jul 30 09:29:35 2010 -0700" }, "message": "PCI: disable mmio during bar sizing\n\nIt is a known issue that mmio decoding shall be disabled while doing PCI\nbar sizing. Host bridge and other devices (PCI PIC) shall be excluded for\ncertain platforms. This patch mainly comes from Mathew Willcox\u0027s\npatch in http://kerneltrap.org/mailarchive/linux-kernel/2007/9/13/258969.\n\nA new flag bit \"mmio_alway_on\" is added to pci_dev with the intention that\ndevices with their mmio decoding cannot be disabled during BAR sizing shall\nhave this bit set, preferrablly in their quirks.\n\nWithout this patch, Intel Moorestown platform graphics unit will be\ncorrupted during bar sizing activities.\n\nSigned-off-by: Jacob Pan \u003cjacob.jun.pan@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "58c84eda07560a6b75b03e8d3b26d6eddfc14011", "tree": "0104345d24d5fb79842ffd563ea69fdf2906931d", "parents": [ "2f7989efd4398d92b8adffce2e07dd043a0895fe" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Thu Jul 15 09:41:42 2010 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jul 16 11:39:48 2010 -0700" }, "message": "PCI: fall back to original BIOS BAR addresses\n\nIf we fail to assign resources to a PCI BAR, this patch makes us try the\noriginal address from BIOS rather than leaving it disabled.\n\nLinux tries to make sure all PCI device BARs are inside the upstream\nPCI host bridge or P2P bridge apertures, reassigning BARs if necessary.\nWindows does similar reassignment.\n\nBefore this patch, if we could not move a BAR into an aperture, we left\nthe resource unassigned, i.e., at address zero. Windows leaves such BARs\nat the original BIOS addresses, and this patch makes Linux do the same.\n\nThis is a bit ugly because we disable the resource long before we try to\nreassign it, so we have to keep track of the BIOS BAR address somewhere.\nFor lack of a better place, I put it in the struct pci_dev.\n\nI think it would be cleaner to attempt the assignment immediately when the\nclaim fails, so we could easily remember the original address. But we\ncurrently claim motherboard resources in the middle, after attempting to\nclaim PCI resources and before assigning new PCI resources, and changing\nthat is a fairly big job.\n\nAddresses https://bugzilla.kernel.org/show_bug.cgi?id\u003d16263\n\nReported-by: Andrew \u003cnitr0@seti.kr.ua\u003e\nTested-by: Andrew \u003cnitr0@seti.kr.ua\u003e\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "9a9620db07b27700a4de9e86985735fffb78e2f8", "tree": "14cf3a384ea0d7afeb759cdaf96de7fec7abc9a7", "parents": [ "e620d1e39aa33b43bed96aa7f2ebbc88914aed58", "52707f918cca231f8461d45e78a60014795f20d9" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Jun 04 15:39:54 2010 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Jun 04 15:39:54 2010 -0700" }, "message": "Merge branch \u0027linux_next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/i7core\n\n* \u0027linux_next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/i7core: (83 commits)\n i7core_edac: Better describe the supported devices\n Add support for Westmere to i7core_edac driver\n i7core_edac: don\u0027t free on success\n i7core_edac: Add support for X5670\n Always call i7core_[ur]dimm_check_mc_ecc_err\n i7core_edac: fix memory leak of i7core_dev\n EDAC: add __init to i7core_xeon_pci_fixup\n i7core_edac: Fix wrong device id for channel 1 devices\n i7core: add support for Lynnfield alternate address\n i7core_edac: Add initial support for Lynnfield\n i7core_edac: do not export static functions\n edac: fix i7core build\n edac: i7core_edac produces undefined behaviour on 32bit\n i7core_edac: Use a more generic approach for probing PCI devices\n i7core_edac: PCI device is called NONCORE, instead of NOCORE\n i7core_edac: Fix ringbuffer maxsize\n i7core_edac: First store, then increment\n i7core_edac: Better parse \"any\" addrmask\n i7core_edac: Use a lockless ringbuffer\n edac: Create an unique instance for each kobj\n ...\n" }, { "commit": "9a90e09854a3c7cc603ab8fc9163f77bb1f66cfa", "tree": "c8c5f767dd2351c9db440f003cc14401583bafd3", "parents": [ "d372e7fe4698bde3a00b718f7901a0025dda47ef", "d3b383338f105f50724c10a7d81b04a3930e886b" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri May 28 14:42:18 2010 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri May 28 14:42:18 2010 -0700" }, "message": "Merge branch \u0027release\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-acpi-2.6\n\n* \u0027release\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-acpi-2.6: (27 commits)\n ACPI: Don\u0027t let acpi_pad needlessly mark TSC unstable\n drivers/acpi/sleep.h: Checkpatch cleanup\n ACPI: Minor cleanup eliminating redundant PMTIMER_TICKS to NS conversion\n ACPI: delete unused c-state promotion/demotion data strucutures\n ACPI: video: fix acpi_backlight\u003dvideo\n ACPI: EC: Use kmemdup\n drivers/acpi: use kasprintf\n ACPI, APEI, EINJ injection parameters support\n Add x64 support to debugfs\n ACPI, APEI, Use ERST for persistent storage of MCE\n ACPI, APEI, Error Record Serialization Table (ERST) support\n ACPI, APEI, Generic Hardware Error Source memory error support\n ACPI, APEI, UEFI Common Platform Error Record (CPER) header\n Unified UUID/GUID definition\n ACPI Hardware Error Device (PNP0C33) support\n ACPI, APEI, PCIE AER, use general HEST table parsing in AER firmware_first setup\n ACPI, APEI, Document for APEI\n ACPI, APEI, EINJ support\n ACPI, APEI, HEST table parsing\n ACPI, APEI, APEI supporting infrastructure\n ...\n" }, { "commit": "affb72c3a8984ba55e055b0a0228c3ea1a056758", "tree": "a6d4c9051110c03f9222bde9c3dcea7822f8570c", "parents": [ "ea8c071cad789b1919355fc7a67182a5c9994e6b" ], "author": { "name": "Huang Ying", "email": "ying.huang@intel.com", "time": "Tue May 18 14:35:16 2010 +0800" }, "committer": { "name": "Len Brown", "email": "len.brown@intel.com", "time": "Wed May 19 22:40:14 2010 -0400" }, "message": "ACPI, APEI, PCIE AER, use general HEST table parsing in AER firmware_first setup\n\nNow, a dedicated HEST tabling parsing code is used for PCIE AER\nfirmware_first setup. It is rebased on general HEST tabling parsing\ncode of APEI. The firmware_first setup code is moved from PCI core to\nAER driver too, because it is only AER related.\n\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Andi Kleen \u003cak@linux.intel.com\u003e\nReviewed-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: Len Brown \u003clen.brown@intel.com\u003e\n" }, { "commit": "d1fd4fb69eeeb7db0693df58b9116db498d5bfe1", "tree": "e3870ec2d0c20804c2865a67c606acf8a736c01c", "parents": [ "5707b24a50b40582226618c56692af932db9fe02" ], "author": { "name": "Mauro Carvalho Chehab", "email": "mchehab@redhat.com", "time": "Fri Jul 10 18:39:53 2009 -0300" }, "committer": { "name": "Mauro Carvalho Chehab", "email": "mchehab@redhat.com", "time": "Mon May 10 11:44:51 2010 -0300" }, "message": "i7core_edac: Add a code to probe Xeon 55xx bus\n\nThis code changes the detection procedure of i7core_edac. Instead of\ndirectly probing for MC registers, it probes for another register found\non Nehalem. If found, it tries to pick the first MC PCI BUS. This should\nwork fine with Xeon 35xx, but, on Xeon 55xx, this is at bus 254 and 255\nthat are not properly detected by the non-legacy PCI methods.\n\nThe new detection code scans specifically at buses 254 and 255 for the\nXeon 55xx devices.\n\nThis code has not tested yet. After working, a change at the code will\nbe needed, since the i7core is not yet ready for working with 2 sets of\nMC.\n\nSigned-off-by: Mauro Carvalho Chehab \u003cmchehab@redhat.com\u003e\n" }, { "commit": "dda565492776b7dff5f8507298d868745e734aab", "tree": "0e93c6d3cad304b860fa8b8715a3dbd03832b2ae", "parents": [ "680a7524622356f5476e8fad2fe32b2b68b432c0" ], "author": { "name": "Yinghai", "email": "yinghai.lu@oracle.com", "time": "Fri Apr 09 01:07:55 2010 +0100" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Fri Apr 09 17:00:00 2010 +0100" }, "message": "intel-iommu: use physfn to search drhd for VF\n\nWhen virtfn is used, we should use physfn to find correct drhd\n\n-v2: add pci_physfn() Suggested by Roland Dreier \u003crdreier@cisco.com\u003e\n do can remove ifdef in dmar.c\n-v3: Chris pointed out we need that for dma_find_matched_atsr_unit too\n also change dmar_pci_device_match() static\n\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nAcked-by: Roland Dreier \u003crdreier@cisco.com\u003e\nAcked-by: Chris Wright \u003cchrisw@sous-sol.org\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "5f3cd1e0bb452c31a306a3e764514ea2eaf7d2e0", "tree": "2fe245e004491e195127fe2327d48775b45ed4e1", "parents": [ "6fee48cd330c68332f9712bc968d934a1a84a32a" ], "author": { "name": "FUJITA Tomonori", "email": "fujita.tomonori@lab.ntt.co.jp", "time": "Wed Mar 10 15:23:41 2010 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Mar 12 15:52:42 2010 -0800" }, "message": "dma-mapping: pci: move pci_set_dma_mask and pci_set_consistent_dma_mask to pci-dma-compat.h\n\nWe can use pci-dma-compat.h to implement pci_set_dma_mask and\npci_set_consistent_dma_mask as we do with the other PCI DMA API.\n\nWe can remove HAVE_ARCH_PCI_SET_DMA_MASK too.\n\nSigned-off-by: FUJITA Tomonori \u003cfujita.tomonori@lab.ntt.co.jp\u003e\nCc: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nCc: Greg KH \u003cgreg@kroah.com\u003e\nCc: Kay Sievers \u003ckay.sievers@vrfy.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "f41b177157718abe9a93868bb76e47d4a6f3681d", "tree": "555d8608a2fe320483c8761dcb2e80cc37b5e822", "parents": [ "c7e67ac1f329fa28b6a411335787c786de618cba" ], "author": { "name": "FUJITA Tomonori", "email": "fujita.tomonori@lab.ntt.co.jp", "time": "Wed Mar 10 15:23:30 2010 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Fri Mar 12 15:52:42 2010 -0800" }, "message": "pci-dma: add linux/pci-dma.h to linux/pci.h\n\nAll the architectures properly set NEED_DMA_MAP_STATE now so we can safely\nadd linux/pci-dma.h to linux/pci.h and remove the linux/pci-dma.h\ninclusion in arch\u0027s asm/pci.h\n\nSigned-off-by: FUJITA Tomonori \u003cfujita.tomonori@lab.ntt.co.jp\u003e\nAcked-by: Arnd Bergmann \u003carnd@arndb.de\u003e\nCc: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "322aafa6645a48c3b7837ca7385f126ab78127fd", "tree": "50f6665aedcf051cecd571183df81ba7f248014b", "parents": [ "dd04265b028c00c365a78f9ff78a05e217f98656", "c7bbf52aa4fa332b84c4f2bb33e69561ee6870b4" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun Mar 07 15:59:39 2010 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun Mar 07 15:59:39 2010 -0800" }, "message": "Merge branch \u0027x86-mrst-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip\n\n* \u0027x86-mrst-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (30 commits)\n x86, mrst: Fix whitespace breakage in apb_timer.c\n x86, mrst: Fix APB timer per cpu clockevent\n x86, mrst: Remove X86_MRST dependency on PCI_IOAPIC\n x86, olpc: Use pci subarch init for OLPC\n x86, pci: Add arch_init to x86_init abstraction\n x86, mrst: Add Kconfig dependencies for Moorestown\n x86, pci: Exclude Moorestown PCI code if CONFIG_X86_MRST\u003dn\n x86, numaq: Make CONFIG_X86_NUMAQ depend on CONFIG_PCI\n x86, pci: Add sanity check for PCI fixed bar probing\n x86, legacy_irq: Remove duplicate vector assigment\n x86, legacy_irq: Remove left over nr_legacy_irqs\n x86, mrst: Platform clock setup code\n x86, apbt: Moorestown APB system timer driver\n x86, mrst: Add vrtc platform data setup code\n x86, mrst: Add platform timer info parsing code\n x86, mrst: Fill in PCI functions in x86_init layer\n x86, mrst: Add dummy legacy pic to platform setup\n x86/PCI: Moorestown PCI support\n x86, ioapic: Add dummy ioapic functions\n x86, ioapic: Early enable ioapic for timer irq\n ...\n\nFixed up semantic conflict of new clocksources due to commit\n17622339af25 (\"clocksource: add argument to resume callback\").\n" }, { "commit": "47871889c601d8199c51a4086f77eebd77c29b0b", "tree": "40cdcac3bff0ee40cc33dcca61d0577cdf965f77", "parents": [ "c16cc0b464b8876cfd57ce1c1dbcb6f9a6a0bce3", "30ff056c42c665b9ea535d8515890857ae382540" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sun Feb 28 19:23:06 2010 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sun Feb 28 19:23:06 2010 -0800" }, "message": "Merge branch \u0027master\u0027 of /home/davem/src/GIT/linux-2.6/\n\nConflicts:\n\tdrivers/firmware/iscsi_ibft.c\n" }, { "commit": "c7e15899d07c9813c1aa96b21699d2d9c8314c4b", "tree": "16e9b4dceddf1b4d1dad05588d700c70cf8fcb88", "parents": [ "f6a0b5cd34d6e922cc7258c5429fb0f17508ceb6", "78c06176466cbd1b3f0f67709d3023c40dbebcbd" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun Feb 28 10:59:18 2010 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Sun Feb 28 10:59:18 2010 -0800" }, "message": "Merge branch \u0027x86-pci-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip\n\n* \u0027x86-pci-for-linus\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:\n x86: Enable NMI on all cpus on UV\n vgaarb: Add user selectability of the number of GPUS in a system\n vgaarb: Fix VGA arbiter to accept PCI domains other than 0\n x86, uv: Update UV arch to target Legacy VGA I/O correctly.\n pci: Update pci_set_vga_state() to call arch functions\n" }, { "commit": "4067a8541d397e9d6b443dd2ce0ecb78bfd991db", "tree": "49690419b218020b8a0e9381db2f9cc90b658cd0", "parents": [ "e1d5bdabb94da89bdb3c3f2ee105cf61fca88ec8" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Fri Feb 26 14:04:43 2010 +0000" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sun Feb 28 00:43:33 2010 -0800" }, "message": "pci: Add helper to search for VPD keywords\n\nThis patch adds the pci_vpd_find_info_keyword() helper function to\nfind information field keywords within read-only and read-write large\nresource data type sections.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "e1d5bdabb94da89bdb3c3f2ee105cf61fca88ec8", "tree": "bc5b86b19bc49ace2df10ed9e7ba7d1ca2b74d33", "parents": [ "b55ac1b22690d2e5b02a61cf6d69c2d66969c79d" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Fri Feb 26 14:04:42 2010 +0000" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sun Feb 28 00:43:32 2010 -0800" }, "message": "pci: Add VPD information field helper functions\n\nThis patch adds a preprocessor constant to describe the PCI VPD\ninformation field header size and an inline function to extract the\nsize of the information field itself.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "b55ac1b22690d2e5b02a61cf6d69c2d66969c79d", "tree": "d336b38719dba482e2734f2091f5a60dfcb134b4", "parents": [ "7ad506fa1adc2da3d394c562f09b8e1b3026c402" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Fri Feb 26 14:04:41 2010 +0000" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sun Feb 28 00:43:32 2010 -0800" }, "message": "pci: Add helper to find a VPD resource data type\n\nThis patch adds the pci_vpd_find_tag() helper function to find VPD\nresource data types in a buffer.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "7ad506fa1adc2da3d394c562f09b8e1b3026c402", "tree": "a4ace2d9918a000d7983eb0770f2346ed7e323aa", "parents": [ "a2ce766238f72ff7337606c0bc96803c30c9e05c" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Fri Feb 26 14:04:40 2010 +0000" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sun Feb 28 00:43:31 2010 -0800" }, "message": "pci: Add large and small resource data type code\n\nThis patch introduces more VPD preprocessor definitions to identify some\nsmall and large resource data type item names. The patch then continues\nto correct how the tg3 and bnx2 drivers search for the \"read-only data\"\nlarge resource data type.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "a2ce766238f72ff7337606c0bc96803c30c9e05c", "tree": "5968e585402263556481075a49599dc697aeab49", "parents": [ "2ea186ae533c7b4f4c56811b69d3e40a6209a9c0" ], "author": { "name": "Matt Carlson", "email": "mcarlson@broadcom.com", "time": "Fri Feb 26 14:04:39 2010 +0000" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Sun Feb 28 00:43:30 2010 -0800" }, "message": "pci: Add PCI LRDT tag size and section size\n\nThis patch adds a preprocessor constant to describe the PCI VPD large\nresource data type tag size and an inline function to extract the large\nresource section size from the large resource data type tag.\n\nSigned-off-by: Matt Carlson \u003cmcarlson@broadcom.com\u003e\nSigned-off-by: Michael Chan \u003cmchan@broadcom.com\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "2fe2abf896c1e7a0ee65faaf3ef0ce654848abbd", "tree": "f066d5c94bbed5ca3556b4d2f0c4b3a9795b6eff", "parents": [ "89a74ecccd1f78e51faf6287e5c0e93a92ac096e" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Tue Feb 23 10:24:36 2010 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Feb 23 09:43:37 2010 -0800" }, "message": "PCI: augment bus resource table with a list\n\nPreviously we used a table of size PCI_BUS_NUM_RESOURCES (16) for resources\nforwarded to a bus by its upstream bridge. We\u0027ve increased this size\nseveral times when the table overflowed.\n\nBut there\u0027s no good limit on the number of resources because host bridges\nand subtractive decode bridges can forward any number of ranges to their\nsecondary buses.\n\nThis patch reduces the table to only PCI_BRIDGE_RESOURCE_NUM (4) entries,\nwhich corresponds to the number of windows a PCI-to-PCI (3) or CardBus (4)\nbridge can positively decode. Any additional resources, e.g., PCI host\nbridge windows or subtractively-decoded regions, are kept in a list.\n\nI\u0027d prefer a single list rather than this split table/list approach, but\nthat requires simultaneous changes to every architecture. This approach\nonly requires immediate changes where we set up (a) host bridges with more\nthan four windows and (b) subtractive-decode P2P bridges, and we can\nincrementally change other architectures to use the list.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "89a74ecccd1f78e51faf6287e5c0e93a92ac096e", "tree": "6d167d73fb2cf5bb457b0b19145fcbf81cf441ef", "parents": [ "2adf75160b10bf3f09ed7d3d04e937f923fc557e" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Tue Feb 23 10:24:31 2010 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Feb 23 09:43:31 2010 -0800" }, "message": "PCI: add pci_bus_for_each_resource(), remove direct bus-\u003eresource[] refs\n\nNo functional change; this converts loops that iterate from 0 to\nPCI_BUS_NUM_RESOURCES through pci_bus resource[] table to use the\npci_bus_for_each_resource() iterator instead.\n\nThis doesn\u0027t change the way resources are stored; it merely removes\ndependencies on the fact that they\u0027re in a table.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "6cbf82148ff286ec22a55be6836c3a5bffc489c1", "tree": "77b1b0097f9c2389d56734ec4c022611aa1bd9db", "parents": [ "552be54cc4232dc5acc49ccb372129d6f1b6923f" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Wed Feb 17 23:44:58 2010 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:21:19 2010 -0800" }, "message": "PCI PM: Run-time callbacks for PCI bus type\n\nIntroduce run-time PM callbacks for the PCI bus type. Make the new\ncallbacks work in analogy with the existing system sleep PM\ncallbacks, so that the drivers already converted to struct dev_pm_ops\ncan use their suspend and resume routines for run-time PM without\nmodifications.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "b67ea76172d4b1922c4b3c46c8ea8e9fec1ff38c", "tree": "c2f51811376060b3b59ac43243a182b94a48be9b", "parents": [ "3f0be67188c60ebf1b5d00354b44b4b24f5af313" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Wed Feb 17 23:44:09 2010 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:21:02 2010 -0800" }, "message": "PCI / ACPI / PM: Platform support for PCI PME wake-up\n\nAlthough the majority of PCI devices can generate PMEs that in\nprinciple may be used to wake up devices suspended at run time,\nplatform support is generally necessary to convert PMEs into wake-up\nevents that can be delivered to the kernel. If ACPI is used for this\npurpose, PME signals generated by a PCI device will trigger the ACPI\nGPE associated with the device to generate an ACPI wake-up event that\nwe can set up a handler for, provided that everything is configured\ncorrectly.\n\nUnfortunately, the subset of PCI devices that have GPEs associated\nwith them is quite limited. The devices without dedicated GPEs have\nto rely on the GPEs associated with other devices (in the majority of\ncases their upstream bridges and, possibly, the root bridge) to\ngenerate ACPI wake-up events in response to PME signals from them.\n\nAdd ACPI platform support for PCI PME wake-up:\no Add a framework making is possible to use ACPI system notify\n handlers for run-time PM.\no Add new PCI platform callback -\u003erun_wake() to struct\n pci_platform_pm_ops allowing us to enable/disable the platform to\n generate wake-up events for given device. Implemet this callback\n for the ACPI platform.\no Define ACPI wake-up handlers for PCI devices and PCI root buses and\n make the PCI-ACPI binding code register wake-up notifiers for all\n PCI devices present in the ACPI tables.\no Add function pci_dev_run_wake() which can be used by PCI drivers to\n check if given device is capable of generating wake-up events at\n run time.\n\nDeveloped in cooperation with Matthew Garrett \u003cmjg@redhat.com\u003e.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "c7f486567c1d0acd2e4166c47069835b9f75e77b", "tree": "5552890ac80fc53f61dd9c53a6211610375efa1f", "parents": [ "58ff463396ad00828e922d50998787e97fd32512" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Wed Feb 17 23:39:08 2010 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:20:31 2010 -0800" }, "message": "PCI PM: PCIe PME root port service driver\n\nPCIe native PME detection mechanism is based on interrupts generated\nby root ports or event collectors every time a PCIe device sends a\nPME message upstream.\n\nOnce a PME message has been sent by an endpoint device and received\nby its root port (or event collector in the case of root complex\nintegrated endpoints), the Requester ID from the message header is\nregistered in the root port\u0027s Root Status register. At the same\ntime, the PME Status bit of the Root Status register is set to\nindicate that there\u0027s a PME to handle. If PCIe PME interrupt is\nenabled for the root port, it generates an interrupt once the PME\nStatus has been set. After receiving the interrupt, the kernel can\nidentify the PCIe device that generated the PME using the Requester\nID from the root port\u0027s Root Status register. [For details, see PCI\nExpress Base Specification, Rev. 2.0.]\n\nImplement a driver for the PCIe PME root port service working in\naccordance with the above description.\n\nBased on a patch from Shaohua Li \u003cshaohua.li@intel.com\u003e.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "6d3be84aab461815978d970aa45f5bc9e52dd772", "tree": "b81755ad2a384c225c2b707591ef3df049b0653e", "parents": [ "9958610552c0bd7558b41cb8addbd865587f142a" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Tue Feb 09 12:21:27 2010 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:17:26 2010 -0800" }, "message": "PCI: mark is_pcie obsolete\n\nThe \"is_pcie\" field in struct pci_dev is no longer needed because\nstruct pci_dev has PCIe capability offset in \"pcie_cap\" field and\n(pcie_cap !\u003d 0) means the device is PCIe capable. This patch marks\n\"is_pcie\" fields obsolete.\n\nCurrent users of \"is_pcie\" field are:\n\n- drivers/ssb/scan.c\n- drivers/net/wireless/ath/ath9k/pci.c\n- drivers/net/wireless/ath/ath5k/attach.c\n- drivers/net/wireless/ath/ath5k/reset.c\n- drivers/acpi/hest.c\n- drivers/pci/pcie/pme/pcie_pme.c\n\nWill post patches for each to use pci_is_pcie() as a follow-up.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "6841ec681a88b66651e4563040b9c7a7ad25d7b5", "tree": "412ddf4db54257d64136930ccd921e674fffd1f9", "parents": [ "977d17bb1749517b353874ccdc9b85abc7a58c2a" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Fri Jan 22 01:02:25 2010 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:17:23 2010 -0800" }, "message": "PCI: introduce pci_assign_unassigned_bridge_resources\n\nFor use by pciehp.\n\npci_setup_bridge() will not check enabled for the slot bridge, otherwise\nupdate res is not updated to bridge BAR. That is, bridge is already\nenabled for port service.\n\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nReviewed-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "41a68a748bbc61f5bcea999e33ba72926dfbe6f7", "tree": "d6b100c49d847270c235a9788b0bebb9372bcec9", "parents": [ "7c9342b8dd1a32386fc32bffb9eedebbfe264763" ], "author": { "name": "Tilman Schmidt", "email": "tilman@imap.cc", "time": "Mon Jan 18 17:24:10 2010 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:17:01 2010 -0800" }, "message": "PCI: push deprecated pci_find_device() function to last user\n\nThe ISDN4Linux HiSax driver family contains the last remaining users\nof the deprecated pci_find_device() function. This patch creates a\nprivate copy of that function in HiSax, and removes the now unused\nglobal function together with its controlling configuration option,\nCONFIG_PCI_LEGACY.\n\nSigned-off-by: Tilman Schmidt \u003ctilman@imap.cc\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "3b7a17fcdae532d29dffab9d564a28be08960988", "tree": "64ac96e997751e34fcd237485fac9b868d1e0614", "parents": [ "b26b2d494b659f988b4d75eb394dfa0ddac415c9" ], "author": { "name": "Dominik Brodowski", "email": "linux@dominikbrodowski.net", "time": "Fri Jan 01 17:40:50 2010 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:16:57 2010 -0800" }, "message": "resource/PCI: mark struct resource as const\n\nNow that we return the new resource start position, there is no\nneed to update \"struct resource\" inside the align function.\nTherefore, mark the struct resource as const.\n\nCc: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nCc: Yinghai Lu \u003cyhlu.kernel@gmail.com\u003e\nSigned-off-by: Dominik Brodowski \u003clinux@dominikbrodowski.net\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "b26b2d494b659f988b4d75eb394dfa0ddac415c9", "tree": "d262f333e529a21017dc072e604a626b38520515", "parents": [ "93da6202264ce1256b04db8008a43882ae62d060" ], "author": { "name": "Dominik Brodowski", "email": "linux@dominikbrodowski.net", "time": "Fri Jan 01 17:40:49 2010 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:16:56 2010 -0800" }, "message": "resource/PCI: align functions now return start of resource\n\nAs suggested by Linus, align functions should return the start\nof a resource, not void. An update of \"res-\u003estart\" is no longer\nnecessary.\n\nCc: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nCc: Yinghai Lu \u003cyhlu.kernel@gmail.com\u003e\nSigned-off-by: Dominik Brodowski \u003clinux@dominikbrodowski.net\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "93177a748ba0d4f3d3e51c8e6c785773bf6a70df", "tree": "1207e03e87d1b68a54ff159c9a8a2f279ea0b6a1", "parents": [ "3804259475314a50e4d7a8a974a22fddb6ac7dd7" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Sat Jan 02 22:57:24 2010 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:15:21 2010 -0800" }, "message": "PCI: Clean up build for CONFIG_PCI_QUIRKS unset\n\nCurrently, drivers/pci/quirks.c is built unconditionally, but if\nCONFIG_PCI_QUIRKS is unset, the only things actually built in this\nfile are definitions of global variables and empty functions (due to\nthe #ifdef CONFIG_PCI_QUIRKS embracing all of the code inside the\nfile). This is not particularly nice and if someone overlooks\nthe #ifdef CONFIG_PCI_QUIRKS, build errors are introduced.\n\nTo clean that up, move the definitions of the global variables in\nquirks.c that are always built to pci.c, move the definitions of\nthe empty functions (compiled when CONFIG_PCI_QUIRKS is unset) to\nheaders (additionally make these functions static inline) and modify\ndrivers/pci/Makefile so that quirks.c is only built if\nCONFIG_PCI_QUIRKS is set.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "9dfd97fe12f79ec8b68feb63912a4ef2f31f571a", "tree": "845515c430a3cc48b1d88496d3b8f4d13bd7efb2", "parents": [ "45b4cdd57ef0e57555b2ab61b584784819b39365" ], "author": { "name": "Matthew Wilcox", "email": "matthew@wil.cx", "time": "Sun Dec 13 08:11:35 2009 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:15:19 2010 -0800" }, "message": "PCI: Add support for reporting PCIe 3.0 speeds\n\nAdd the 8.0 GT/s speed.\n\nSigned-off-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "45b4cdd57ef0e57555b2ab61b584784819b39365", "tree": "1e08008e0cdc57252022b5ad1a0e3029c7e96f99", "parents": [ "9be60ca0497a2563662fde4c9007841c3b79a742" ], "author": { "name": "Matthew Wilcox", "email": "matthew@wil.cx", "time": "Sun Dec 13 08:11:34 2009 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:15:19 2010 -0800" }, "message": "PCI: Add support for AGP in cur/max bus speed\n\nTake advantage of some gaps in the table to fit in support for AGP speeds.\n\nSigned-off-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "3749c51ac6c1560aa1cb1520066bed84c6f8152a", "tree": "3cbfb6a6d2df821e3e80ccce29ede8011b94246e", "parents": [ "536c8cb49eccd4f753b4782e7e975ef87359cb44" ], "author": { "name": "Matthew Wilcox", "email": "matthew@wil.cx", "time": "Sun Dec 13 08:11:32 2009 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:15:17 2010 -0800" }, "message": "PCI: Make current and maximum bus speeds part of the PCI core\n\nMove the max_bus_speed and cur_bus_speed into the pci_bus. Expose the\nvalues through the PCI slot driver instead of the hotplug slot driver.\nUpdate all the hotplug drivers to use the pci_bus instead of their own\ndata structures.\n\nSigned-off-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "536c8cb49eccd4f753b4782e7e975ef87359cb44", "tree": "1cc2a32b17e4eb1fc4c9b64dc4895892a2fd3d41", "parents": [ "f07852d6442c46c50b59c7e2acc8a1b291f9ab6d" ], "author": { "name": "Matthew Wilcox", "email": "matthew@wil.cx", "time": "Sun Dec 13 08:11:31 2009 -0500" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Feb 22 16:15:17 2010 -0800" }, "message": "PCI: Unify pcie_link_speed and pci_bus_speed\n\nThese enums must not overlap anyway, since we only have a single\npci_bus_speed_strings array. Use a single enum, and move it to\npci.h. Add \u0027SPEED\u0027 to the pcie names to make it clear what they are.\n\nSigned-off-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "cf4c43dd439b90a1a876b3f836ebe745abb9a269", "tree": "59d7a278d9d5cb6c9927819fa75231e284b29556", "parents": [ "724e6d3fe8003c3f60bf404bf22e4e331327c596" ], "author": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Jul 15 13:13:00 2009 -0700" }, "committer": { "name": "H. Peter Anvin", "email": "hpa@zytor.com", "time": "Fri Feb 19 16:12:26 2010 -0800" }, "message": "PCI: Add pci_bus_find_ext_capability\n\nFor use by code that needs to walk extended capability lists before\npci_dev structures are set up.\n\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nLKML-Reference: \u003c43F901BD926A4E43B106BF17856F07559FB80CFD@orsmsx508.amr.corp.intel.com\u003e\nSigned-off-by: Jacob Pan \u003cjacob.jun.pan@intel.com\u003e\nSigned-off-by: H. Peter Anvin \u003chpa@zytor.com\u003e\n" }, { "commit": "2bb4646fce8d09916b351d1a62f98db7cec6fc41", "tree": "c1f0d002e69868606eca9d1b919835f422892063", "parents": [ "6836b9bdd98e3b500cd49512484df68f46e14659", "b0483e78e5c4c9871fc5541875b3bc006846d46b" ], "author": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Feb 16 22:09:29 2010 -0800" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Tue Feb 16 22:09:29 2010 -0800" }, "message": "Merge branch \u0027master\u0027 of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6\n" }, { "commit": "fb8a0d9d1bfd1e4355f307e86a6da7209eefd5f3", "tree": "99f23a4bc7c51343619f63970e5d017d75b5a66f", "parents": [ "81d54ec8479a2c695760da81f05b5a9fb2dbe40a" ], "author": { "name": "Williams, Mitch A", "email": "mitch.a.williams@intel.com", "time": "Wed Feb 10 01:43:04 2010 +0000" }, "committer": { "name": "David S. Miller", "email": "davem@davemloft.net", "time": "Fri Feb 12 16:56:07 2010 -0800" }, "message": "pci: Add SR-IOV convenience functions and macros\n\nAdd and export pci_num_vf to allow other subsystems to determine how many\nvirtual function devices are associated with an SR-IOV physical function\ndevice.\nAdd macros dev_is_pci, dev_is_ps, and dev_num_vf to make it easier for\nnon-PCI specific code to determine SR-IOV capabilities.\n\nSigned-off-by: Mitch Williams \u003cmitch.a.williams@intel.com\u003e\nSigned-off-by: Jeff Kirsher \u003cjeffrey.t.kirsher@intel.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "95a8b6efc5d07103583f706c8a5889437d537939", "tree": "a8e9161eea03b0eb21e838826c547771158ecdce", "parents": [ "499a2673713c85734a54c37dd90b4b729de399c4" ], "author": { "name": "Mike Travis", "email": "travis@sgi.com", "time": "Tue Feb 02 14:38:13 2010 -0800" }, "committer": { "name": "H. Peter Anvin", "email": "hpa@zytor.com", "time": "Fri Feb 05 14:05:41 2010 -0800" }, "message": "pci: Update pci_set_vga_state() to call arch functions\n\nUpdate pci_set_vga_state to call arch dependent functions to enable Legacy\nVGA I/O transactions to be redirected to correct target.\n\n[akpm@linux-foundation.org: make pci_register_set_vga_state() __init]\nSigned-off-by: Mike Travis \u003ctravis@sgi.com\u003e\nLKML-Reference: \u003c201002022238.o12McE1J018723@imap1.linux-foundation.org\u003e\nCc: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: Robin Holt \u003cholt@sgi.com\u003e\nCc: Jack Steiner \u003csteiner@sgi.com\u003e\nCc: Ingo Molnar \u003cmingo@elte.hu\u003e\nCc: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nCc: David Airlie \u003cairlied@linux.ie\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: H. Peter Anvin \u003chpa@zytor.com\u003e\n" }, { "commit": "bb209c8287d2d55ec4a67e3933346e0a3ee0da76", "tree": "2e444f273e631fa4dded4ee13ac779565e5efb43", "parents": [ "b04da8bfdfbbd79544cab2fadfdc12e87eb01600" ], "author": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Tue Jan 26 17:10:03 2010 +0000" }, "committer": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Fri Jan 29 16:51:10 2010 +1100" }, "message": "powerpc/pci: Add calls to set_pcie_port_type() and set_pcie_hotplug_bridge()\n\nWe are missing these when building the pci_dev from scratch off\nthe Open Firmware device-tree\n\nSigned-off-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "1ae861e652b5457e7fa98ccbc55abea1e207916e", "tree": "d0326aab2746a779f3ab140ec9fdea2508f2e99b", "parents": [ "6be954d1f91b81ca85c74792b13654069278c577" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Thu Dec 31 12:15:54 2009 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Jan 04 15:41:47 2010 -0800" }, "message": "PCI/PM: Use per-device D3 delays\n\nIt turns out that some PCI devices require extra delays when changing\npower state from D3 to D0 (and the other way around). Although this\nis against the PCI specification, we can handle it quite easily by\nallowing drivers to define arbitrary D3 delays for devices known to\nrequire extra time for switching power states.\n\nIntroduce additional field d3_delay in struct pci_dev and use it to\nstore the value of the device\u0027s D0-\u003eD3 delay, in miliseconds. Make\nthe PCI PM core code use the per-device d3_delay unless\npci_pm_d3_delay is greater (in which case the latter is used).\n[This also allows the driver to specify d3_delay shorter than the\n 10 ms required by the PCI standard if the device is known to be able\n to handle that.]\n\nMake the sky2 driver set d3_delay to 150 for devices handled by it.\n\nFixes http://bugzilla.kernel.org/show_bug.cgi?id\u003d14730 which is a\nlisted regression from 2.6.30.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "2d1c861871d767153538a77c498752b36d4bb4b8", "tree": "2ed80140487cd68e539c55876ba361199a4b92c1", "parents": [ "7e8af37a9a71b479f58d2fd5f0ddaa6780c51f11" ], "author": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Wed Dec 09 17:52:13 2009 +1100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Dec 16 18:55:51 2009 -0800" }, "message": "PCI/cardbus: Add a fixup hook and fix powerpc\n\nThe cardbus code creates PCI devices without ever going through the\nnecessary fixup bits and pieces that normal PCI devices go through.\n\nThere\u0027s in fact a commented out call to pcibios_fixup_bus() in there,\nit\u0027s commented because ... it doesn\u0027t work.\n\nI could make pcibios_fixup_bus() do the right thing on powerpc easily\nbut I felt it cleaner instead to provide a specific hook pci_fixup_cardbus\nfor which a weak empty implementation is provided by the PCI core.\n\nThis fixes cardbus on powerbooks and probably all other PowerPC\nplatforms which was broken completely for ever on some platforms and\nsince 2.6.31 on others such as PowerBooks when we made the DMA ops\nmandatory (since those are setup by the fixups).\n\nAcked-by: Dominik Brodowski \u003clinux@dominikbrodowski.net\u003e\nSigned-off-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "491424c0f46c282a854b88830212bdb0763e93dc", "tree": "54e3272da9bdc638c6efcb43fa94f96454106d0a", "parents": [ "5185fb069972b653dd7177292e7510ff99d9e8aa" ], "author": { "name": "David Howells", "email": "dhowells@redhat.com", "time": "Mon Dec 14 14:13:44 2009 +0000" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Dec 14 10:11:34 2009 -0800" }, "message": "PCI: Global variable decls must match the defs in section attributes\n\nGlobal variable declarations must match the definitions in section attributes\nas the compiler is at liberty to vary the method it uses to access a variable,\ndepending on the section it is in.\n\nWhen building the FRV arch, I now see:\n\n drivers/built-in.o: In function `pci_apply_final_quirks\u0027:\n drivers/pci/quirks.c:2606: relocation truncated to fit: R_FRV_GPREL12 against symbol `pci_dfl_cache_line_size\u0027 defined in .devinit.data section in drivers/built-in.o\n drivers/pci/quirks.c:2623: relocation truncated to fit: R_FRV_GPREL12 against symbol `pci_dfl_cache_line_size\u0027 defined in .devinit.data section in drivers/built-in.o\n drivers/pci/quirks.c:2630: relocation truncated to fit: R_FRV_GPREL12 against symbol `pci_dfl_cache_line_size\u0027 defined in .devinit.data section in drivers/built-in.o\n\nbecause the declaration of pci_dfl_cache_line_size in linux/pci.h does not\nmatch the definition in drivers/pci/pci.c.\n\nSigned-off-by: David Howells \u003cdhowells@redhat.com\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "5d990b627537e59a3a2f039ff588a4750e9c1a6a", "tree": "8c0e723c3f9146da52b30c087a80fc417df2b41b", "parents": [ "b26a34aa4792b3db2500b8a98cb7702765c1a92e" ], "author": { "name": "Chris Wright", "email": "chrisw@sous-sol.org", "time": "Fri Dec 04 12:15:21 2009 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Dec 04 16:19:24 2009 -0800" }, "message": "PCI: add pci_request_acs\n\nCommit ae21ee65e8bc228416bbcc8a1da01c56a847a60c \"PCI: acs p2p upsteram\nforwarding enabling\" doesn\u0027t actually enable ACS.\n\nAdd a function to pci core to allow an IOMMU to request that ACS\nbe enabled. The existing mechanism of using iommu_found() in the pci\ncore to know when ACS should be enabled doesn\u0027t actually work due to\ninitialization order; iommu has only been detected not initialized.\n\nHave Intel and AMD IOMMUs request ACS, and Xen does as well during early\ninit of dom0.\n\nCc: Allen Kay \u003callen.m.kay@intel.com\u003e\nCc: David Woodhouse \u003cdwmw2@infradead.org\u003e\nCc: Jeremy Fitzhardinge \u003cjeremy@goop.org\u003e\nCc: Joerg Roedel \u003cjoerg.roedel@amd.com\u003e\nSigned-off-by: Chris Wright \u003cchrisw@sous-sol.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "7eb776c42e75d17bd8107a1359068d8c742639d1", "tree": "eddee4ecffebc2ac54c1eee548802367c5f17c68", "parents": [ "1518c17ab736303098843bd306a0fc4f8f5faa42" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 11 14:35:22 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Nov 24 15:25:16 2009 -0800" }, "message": "PCI: introduce pci_is_pcie()\n\nIntroduce pci_is_pcie() which returns true if the specified PCI device\nis PCI Express capable, false otherwise.\n\nThe purpose of pci_is_pcie() is removing \u0027is_pcie\u0027 flag in the struct\npci_dev, which is not needed because we can check it using \u0027pcie_cap\u0027\nfield. To remove \u0027is_pcie\u0027, we need to update user of \u0027is_pcie\u0027 to use\npci_is_pcie() instead first.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "d7b7e60526d54da4c94afe5f137714cee7d05c41", "tree": "e8cdf8d2e60c274848e860501234ebb958ab0ae9", "parents": [ "8c8def26bfaa704db67d515da3eb92cf26067548" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Wed Nov 11 14:29:54 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Nov 24 15:25:11 2009 -0800" }, "message": "PCI: introduce pci_pcie_cap()\n\nIntroduce pci_pcie_cap() API that returns saved PCIe capability offset\n(currently it is saved in \u0027pcie_cap\u0027 field in the struct PCI dev).\nUsing pci_pcie_cap() instead of pci_find_capability() avoids\nunnecessary search in PCI configuration space.\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "0efea0006335a2425b1a12a2ad35efad626fe353", "tree": "d139b06a32665ec1227c06f1c0a14b21e3c0d654", "parents": [ "1e5ad9679016275d422e36b12a98b0927d76f556" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Thu Nov 05 12:05:11 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Nov 06 13:59:02 2009 -0800" }, "message": "PCI: cache PCIe capability offset\n\nThere are a lot of codes that searches PCI express capability offset\nin the PCI configuration space using pci_find_capability(). Caching it\nin the struct pci_dev will reduce unncecessary search. This patch adds\nan additional \u0027pcie_cap\u0027 fields into struct pci_dev, which is\ninitialized at pci device scan time (in set_pcie_port_type()).\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "3c299dc22635e500214707aa28be119ff2b3901c", "tree": "6d9cb3710c674639041ead3247e179fa82dcaf35", "parents": [ "bc577d2bb98cc44371287fce3e892d26ad4050a8" ], "author": { "name": "Andrew Patterson", "email": "andrew.patterson@hp.com", "time": "Mon Oct 12 13:14:00 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 13:06:36 2009 -0800" }, "message": "PCI: add pci_get_domain_bus_and_slot function\n\nAdded the pci_get_domain_and_slot_function which is analogous to\npci_get_bus_and_slot. It returns a pci_dev given a domain (segment) number,\nbus number, and devnr. Like pci_get_bus_and_slot,\npci_get_domain_bus_and_slot holds a reference to the returned pci_dev.\n\nConverted pci_get_bus_and_slot to a wrapper that calls\npci_get_domain_bus_and_slot with the domain hard-coded to 0.\n\nThis routine was patterned off code suggested by Bjorn Helgaas.\n\nAcked-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "0584396157ad2d008e2cc76b4ed6254151183a25", "tree": "8860a033938b1a01cccf9a203208f741758724ac", "parents": [ "8792e11f1c54bcba34412f03959e70ee217f2231" ], "author": { "name": "Matt Domsch", "email": "Matt_Domsch@dell.com", "time": "Mon Nov 02 11:51:24 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 13:06:25 2009 -0800" }, "message": "PCI: PCIe AER: honor ACPI HEST FIRMWARE FIRST mode\n\nFeedback from Hidetoshi Seto and Kenji Kaneshige incorporated. This\ncorrectly handles PCI-X bridges, PCIe root ports and endpoints, and\nprints debug messages when invalid/reserved types are found in the\nHEST. PCI devices not in domain/segment 0 are not represented in\nHEST, thus will be ignored.\n\nToday, the PCIe Advanced Error Reporting (AER) driver attaches itself\nto every PCIe root port for which BIOS reports it should, via ACPI\n_OSC.\n\nHowever, _OSC alone is insufficient for newer BIOSes. Part of ACPI\n4.0 is the new APEI (ACPI Platform Error Interfaces) which is a way\nfor OS and BIOS to handshake over which errors for which components\neach will handle. One table in ACPI 4.0 is the Hardware Error Source\nTable (HEST), where BIOS can define that errors for certain PCIe\ndevices (or all devices), should be handled by BIOS (\"Firmware First\nmode\"), rather than be handled by the OS.\n\nDell PowerEdge 11G server BIOS defines Firmware First mode in HEST, so\nthat it may manage such errors, log them to the System Event Log, and\npossibly take other actions. The aer driver should honor this, and\nnot attach itself to devices noted as such.\n\nFurthermore, Kenji Kaneshige reminded us to disallow changing the AER\nregisters when respecting Firmware First mode. Platform firmware is\nexpected to manage these, and if changes to them are allowed, it could\nbreak that firmware\u0027s behavior.\n\nThe HEST parsing code may be replaced in the future by a more\nfeature-rich implementation. This patch provides the minimum needed\nto prevent breakage until that implementation is available.\n\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nReviewed-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Matt Domsch \u003cMatt_Domsch@dell.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "15ea76d407d560f985224b65fe59c9db01692a0d", "tree": "dd9dd1cd4cab4bff26c34853a1c67898e8500243", "parents": [ "4c0eec7a86303ce6e3edf7825d0ef1d414e76767" ], "author": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Tue Sep 22 17:34:48 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 08:47:11 2009 -0800" }, "message": "pccard: configure CLS on attach\n\nFor non hotplug PCI devices, the system firmware usually configures\nCLS correctly. For pccard devices system firmware can\u0027t do it and\nLinux PCI layer doesn\u0027t do it either. Unfortunately this leads to\npoor performance for certain devices (sata_sil). Unless MWI, which\nrequires separate configuration, is to be used, CLS doesn\u0027t affect\ncorrectness, so the configuration should be harmless.\n\nThis patch makes pci_set_cacheline_size() always built and export it\nand make pccard call it during attach.\n\nPlease note that some other PCI hotplug drivers (shpchp and pciehp)\nalso configure CLS on hotplug.\n\nSigned-off-by: Tejun Heo \u003ctj@kernel.org\u003e\nCc: Daniel Ritz \u003cdaniel.ritz@gmx.ch\u003e\nCc: Dominik Brodowski \u003clinux@dominikbrodowski.net\u003e\nCc: Greg KH \u003cgreg@kroah.com\u003e\nCc: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nCc: Axel Birndt \u003ctowerlexa@gmx.de\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "ac1aa47b131416a6ff37eb1005a0a1d2541aad6c", "tree": "1d7efa15a16f61664a240520970e729b1a47e4a5", "parents": [ "99935a7a59eaca0292c1a5880e10bae03f4a5e3d" ], "author": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Oct 26 13:20:44 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Nov 04 08:47:10 2009 -0800" }, "message": "PCI: determine CLS more intelligently\n\nTill now, CLS has been determined either by arch code or as\nL1_CACHE_BYTES. Only x86 and ia64 set CLS explicitly and x86 doesn\u0027t\nalways get it right. On most configurations, the chance is that\nfirmware configures the correct value during boot.\n\nThis patch makes pci_init() determine CLS by looking at what firmware\nhas configured. It scans all devices and if all non-zero values\nagree, the value is used. If none is configured or there is a\ndisagreement, pci_dfl_cache_line_size is used. arch can set the dfl\nvalue (via PCI_CACHE_LINE_BYTES or pci_dfl_cache_line_size) or\noverride the actual one.\n\nia64, x86 and sparc64 updated to set the default cls instead of the\nactual one.\n\nWhile at it, declare pci_cache_line_size and pci_dfl_cache_line_size\nin pci.h and drop private declarations from arch code.\n\nSigned-off-by: Tejun Heo \u003ctj@kernel.org\u003e\nAcked-by: David Miller \u003cdavem@davemloft.net\u003e\nAcked-by: Greg KH \u003cgregkh@suse.de\u003e\nCc: Ingo Molnar \u003cmingo@elte.hu\u003e\nCc: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nCc: Tony Luck \u003ctony.luck@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "e80bb09d2c73d76a2a4cd79e4a83802dd901c642", "tree": "fff892db62dd092ab8e3d70d19d813d4979a2503", "parents": [ "df8db91fc3b543d373afa61beef35b072eea1368" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Tue Sep 08 23:14:49 2009 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 14:19:11 2009 -0700" }, "message": "PCI PM: Introduce device flag wakeup_prepared\n\nIntroduce a new PCI device flag, wakeup_prepared, to prevent PCI\nwake-up preparation code from being executed twice in a row for the\nsame device and for the same purpose.\n\nReviewed-by: Matthew Garrett \u003cmjg59@srcf.ucam.org\u003e\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "28760489a3f1e136c5ae8581c0fa8f63511f2f4c", "tree": "a3c890e9c8d9e98385691d56f5c007d280514fe5", "parents": [ "0ba379ec0fb182a87b8891c5754abbcd9c035b4f" ], "author": { "name": "Eric W. Biederman", "email": "ebiederm@aristanetworks.com", "time": "Wed Sep 09 14:09:24 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 14:10:24 2009 -0700" }, "message": "PCI: pcie: Ensure hotplug ports have a minimum number of resources\n\nIn general a BIOS may goof or we may hotplug in a hotplug controller.\nIn either case the kernel needs to reserve resources for plugging\nin more devices in the future instead of creating a minimal resource\nassignment.\n\nWe already do this for cardbus bridges I am just adding a variant\nfor pcie bridges.\n\nv2: Make testing for pcie hotplug bridges based on a flag.\n\n So far we only set the flag for pcie but a header_quirk\n could easily be added for the non-standard pci hotplug\n bridges.\n\nSigned-off-by: Eric W. Biederman \u003cebiederm@aristanetworks.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "9dba910e9de2c4aa15ec1286f10052c107ef48ca", "tree": "4870eccc95e406ae8d490136f5d65953203418c8", "parents": [ "825c423a35a80a8fd66398a3f9bde7f0b0187a76" ], "author": { "name": "Tejun Heo", "email": "tj@kernel.org", "time": "Thu Sep 03 15:26:36 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:43:58 2009 -0700" }, "message": "PCI: separate out pci_add_dynid()\n\nSeparate out pci_add_dynid() from store_new_id() and export it so that\nin-kernel code can add PCI IDs dynamically. As the function will be\navailable regardless of HOTPLUG, put it and pull pci_free_dynids()\noutside of CONFIG_HOTPLUG.\n\nThis will be used by pci-stub to initialize initial IDs via module\nparam.\n\nWhile at it, remove bogus get_driver() failure check.\n\nSigned-off-by: Tejun Heo \u003ctj@kernel.org\u003e\nAcked-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\nReviewed-by: Grant Grundler \u003cgrundler@parisc-linux.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "260d703adc5f275e3ba7ddff6e2e0217bc613b35", "tree": "b91dbf65c67dcd1d7349e5b8df6128ffcd1389c4", "parents": [ "deb2d2ecd43dfc51efe71eed7128fda514da96c6" ], "author": { "name": "Mike Mason", "email": "mmlnx@us.ibm.com", "time": "Thu Jul 30 15:33:21 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:29:37 2009 -0700" }, "message": "PCI: support for PCI Express fundamental reset\n\nThis is the first of three patches that implement a bit field that PCI\nExpress device drivers can use to indicate they need a fundamental reset\nduring error recovery.\n\nBy default, the EEH framework on powerpc does what\u0027s known as a \"hot\nreset\" during recovery of a PCI Express device. We\u0027ve found a case\nwhere the device needs a \"fundamental reset\" to recover properly. The\ncurrent PCI error recovery and EEH frameworks do not support this\ndistinction.\n\nThe attached patch (courtesy of Richard Lary) adds a bit field to\npci_dev that indicates whether the device requires a fundamental reset\nduring recovery.\n\nThese patches supersede the previously submitted patch that implemented\na fundamental reset bit field.\n\nSigned-off-by: Mike Mason \u003cmmlnx@us.ibm.com\u003e\nSigned-off-by: Richard Lary \u003crlary@us.ibm.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "deb2d2ecd43dfc51efe71eed7128fda514da96c6", "tree": "ba05339620bc285265f88d2c7c43df5fc25b732c", "parents": [ "500559a92dd36af7cee95ed2f5b7722fb95a82e7" ], "author": { "name": "Benjamin Herrenschmidt", "email": "benh@kernel.crashing.org", "time": "Tue Aug 11 15:52:06 2009 +1000" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:29:36 2009 -0700" }, "message": "PCI/GPU: implement VGA arbitration on Linux\n\nBackground:\nGraphic devices are accessed through ranges in I/O or memory space. While most\nmodern devices allow relocation of such ranges, some \"Legacy\" VGA devices\nimplemented on PCI will typically have the same \"hard-decoded\" addresses as\nthey did on ISA. For more details see \"PCI Bus Binding to IEEE Std 1275-1994\nStandard for Boot (Initialization Configuration) Firmware Revision 2.1\"\nSection 7, Legacy Devices.\n\nThe Resource Access Control (RAC) module inside the X server currently does\nthe task of arbitration when more than one legacy device co-exists on the same\nmachine. But the problem happens when these devices are trying to be accessed\nby different userspace clients (e.g. two server in parallel). Their address\nassignments conflict. Therefore an arbitration scheme _outside_ of the X\nserver is needed to control the sharing of these resources. This document\nintroduces the operation of the VGA arbiter implemented for Linux kernel.\n\nSigned-off-by: Benjamin Herrenschmidt \u003cbenh@kernel.crashing.org\u003e\nSigned-off-by: Tiago Vignatti \u003ctiago.vignatti@nokia.com\u003e\nSigned-off-by: Dave Airlie \u003cairlied@redhat.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "711d57796f5ce2d02d6e62c9034afbb16aedda31", "tree": "935861fee775b171cafc96de57fe4fbfa19892eb", "parents": [ "5228a828ee044834d78abdf25306bf46b19dcc4d" ], "author": { "name": "Michael S. Tsirkin", "email": "mst@redhat.com", "time": "Mon Jul 27 23:37:48 2009 +0300" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Sep 09 13:29:24 2009 -0700" }, "message": "PCI: expose function reset capability in sysfs\n\nSome devices allow an individual function to be reset without affecting\nother functions in the same device: that\u0027s what pci_reset_function does.\nFor devices that have this support, expose reset attribite in sysfs.\n\nThis is useful e.g. for virtualization, where a qemu userspace\nprocess wants to reset the device when the guest is reset,\nto emulate machine reboot as closely as possible.\n\nAcked-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\nSigned-off-by: Michael S. Tsirkin \u003cmst@redhat.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "2fc90f6133a87da8177636866557d4cc5f56e661", "tree": "b308f14cd99d8980107a581b729db6b35b940b06", "parents": [ "7a661c6f1082693a7e9627e9ad2d1546a9337fdc" ], "author": { "name": "Alexey Zaytsev", "email": "zaytsev@altell.ru", "time": "Wed Jun 24 16:22:30 2009 +0400" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Jun 29 12:14:51 2009 -0700" }, "message": "PCI: make pci_name() take const argument\n\nSince this function should never modify it (saves warnings when called with\nconst args too).\n\nSigned-off-by: Alexey Zaytsev \u003czaytsev@altell.ru\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "687d680985b1438360a9ba470ece8b57cd205c3b", "tree": "ae253608531e5c3e823600974c610e722e7de759", "parents": [ "1053414068bad659479e6efa62a67403b8b1ec0a", "008fe148cb0fb51d266baabe2c09997b21cf90c6" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Jun 22 21:38:22 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Jun 22 21:38:22 2009 -0700" }, "message": "Merge git://git.infradead.org/~dwmw2/iommu-2.6.31\n\n* git://git.infradead.org/~dwmw2/iommu-2.6.31:\n intel-iommu: Fix one last ia64 build problem in Pass Through Support\n VT-d: support the device IOTLB\n VT-d: cleanup iommu_flush_iotlb_psi and flush_unmaps\n VT-d: add device IOTLB invalidation support\n VT-d: parse ATSR in DMA Remapping Reporting Structure\n PCI: handle Virtual Function ATS enabling\n PCI: support the ATS capability\n intel-iommu: dmar_set_interrupt return error value\n intel-iommu: Tidy up iommu-\u003egcmd handling\n intel-iommu: Fix tiny theoretical race in write-buffer flush.\n intel-iommu: Clean up handling of \"caching mode\" vs. IOTLB flushing.\n intel-iommu: Clean up handling of \"caching mode\" vs. context flushing.\n VT-d: fix invalid domain id for KVM context flush\n Fix !CONFIG_DMAR build failure introduced by Intel IOMMU Pass Through Support\n Intel IOMMU Pass Through Support\n\nFix up trivial conflicts in drivers/pci/{intel-iommu.c,intr_remapping.c}\n" }, { "commit": "59ef7a83f1127038a433464597df02e2dc9540e7", "tree": "725d262fc2e68eb9c592d76265f878cec73f8f2d", "parents": [ "5165aece0efac6574fc3e32b6f1c2a964820d1c6", "2af5066f664cb011cf17d2e4414491fe24597e07" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Jun 22 11:59:51 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Mon Jun 22 11:59:51 2009 -0700" }, "message": "Merge branch \u0027linux-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6\n\n* \u0027linux-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: (74 commits)\n PCI: make msi_free_irqs() to use msix_mask_irq() instead of open coded write\n PCI: Fix the NIU MSI-X problem in a better way\n PCI ASPM: remove get_root_port_link\n PCI ASPM: cleanup pcie_aspm_sanity_check\n PCI ASPM: remove has_switch field\n PCI ASPM: cleanup calc_Lx_latency\n PCI ASPM: cleanup pcie_aspm_get_cap_device\n PCI ASPM: cleanup clkpm checks\n PCI ASPM: cleanup __pcie_aspm_check_state_one\n PCI ASPM: cleanup initialization\n PCI ASPM: cleanup change input argument of aspm functions\n PCI ASPM: cleanup misc in struct pcie_link_state\n PCI ASPM: cleanup clkpm state in struct pcie_link_state\n PCI ASPM: cleanup latency field in struct pcie_link_state\n PCI ASPM: cleanup aspm state field in struct pcie_link_state\n PCI ASPM: fix typo in struct pcie_link_state\n PCI: drivers/pci/slot.c should depend on CONFIG_SYSFS\n PCI: remove redundant __msi_set_enable()\n PCI PM: consistently use type bool for wake enable variable\n x86/ACPI: Correct maximum allowed _CRS returned resources and warn if exceeded\n ...\n" }, { "commit": "7d9a73f6dcf4390d256bf19330c81e91523a26d5", "tree": "dddaeb3e6a1f5d5dd8d1b96ed6105566b69a3b21", "parents": [ "f9cde5ffed17bf74f6bef042d99edb0622f58576" ], "author": { "name": "Frans Pop", "email": "elendil@planet.nl", "time": "Wed Jun 17 00:16:15 2009 +0200" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Jun 16 15:19:02 2009 -0700" }, "message": "PCI PM: consistently use type bool for wake enable variable\n\nOther functions use type bool, so use that for pci_enable_wake as well.\n\nSigned-off-by: Frans Pop \u003celendil@planet.nl\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "8c1c699fec9e9021bf6ff0285dee086bb27aec90", "tree": "4af7bd96c1b651633ff7b6721959aeacd120e4ee", "parents": [ "c465def6bfe834b62623caa9b98f2d4f4739875a" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Sat Jun 13 15:52:13 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Jun 16 14:30:15 2009 -0700" }, "message": "PCI: cleanup Function Level Reset\n\nThis patch enhances the FLR functions:\n 1) remove disable_irq() so the shared IRQ won\u0027t be disabled.\n 2) replace the 1s wait with 100, 200 and 400ms wait intervals\n for the Pending Transaction.\n 3) replace mdelay() with msleep().\n 4) add might_sleep().\n 5) lock the device to prevent PM suspend from accessing the CSRs\n during the reset.\n 6) coding style fixes.\n\nReviewed-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "70298c6e6c1ba68346336b4ea54bd5c0abbf73c8", "tree": "363d0a784d8a28688c0fda006279563a7fd3629b", "parents": [ "a6c0d5c6ebb3d988b1f18a1612b5188f3f555637" ], "author": { "name": "Zhang, Yanmin", "email": "yanmin_zhang@linux.intel.com", "time": "Tue Jun 16 13:34:38 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Jun 16 14:30:13 2009 -0700" }, "message": "PCI AER: support Multiple Error Received and no error source id\n\nBased on PCI Express AER specs, a root port might receive multiple\nTLP errors while it could only save a correctable error source id\nand an uncorrectable error source id at the same time. In addition,\nsome root port hardware might be unable to provide a correct source\nid, i.e., the source id, or the bus id part of the source id provided\nby root port might be equal to 0.\n\nThe patchset implements the support in kernel by searching the device\ntree under the root port.\n\nPatch 1 changes parameter cb of function pci_walk_bus to return a value.\nWhen cb return non-zero, pci_walk_bus stops more searching on the\ndevice tree.\n\nReviewed-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Zhang Yanmin \u003cyanmin_zhang@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "c825bc94c8c1908750ab20413eb639c6be029e2d", "tree": "6e5800fe52e0f94f42fdcd4c327b8cfaf803978a", "parents": [ "498a8faf2c7eb974f70b7c5a60a31f0d48c35d44" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Tue Jun 16 11:01:25 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Jun 16 14:30:11 2009 -0700" }, "message": "PCI hotplug: create symlink to hotplug driver module\n\nCreate symbolic link to hotplug driver module in the PCI slot\ndirectory (/sys/bus/pci/slots/\u003cSLOT#\u003e). In the past, we need to load\nhotplug drivers one by one to identify the hotplug driver that handles\nthe slot, and it was very inconvenient especially for trouble shooting.\nWith this change, we can easily identify the hotplug driver.\n\nSigned-off-by: Taku Izumi \u003cizumi.taku@jp.fujitsu.com\u003e\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nReviewed-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "a72b46c3849cdb05993015991bde548ab8b6d7ac", "tree": "a782d4ab9c217792c9a8cefe48db9aebc0734dbe", "parents": [ "1eb3948716f68bdb71509d0175765295f1aca23d" ], "author": { "name": "Huang Ying", "email": "ying.huang@intel.com", "time": "Fri Apr 24 10:45:17 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Tue Jun 16 14:29:33 2009 -0700" }, "message": "PCI: Add pci_bus_set_ops\n\npci_bus_set_ops changes pci_ops associated with a pci_bus. This can be\nused by debug tools such as PCIE AER error injection to fake some PCI\nconfiguration registers.\n\nAcked-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Huang Ying \u003cying.huang@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "00240c3839d843ccf07abd52806f421f7b87bbdc", "tree": "4ad3a8c543a7a3de0893b1289086e62fffb98bc6", "parents": [ "604eb89ffed9fba268582dc44d5b462ea94cc0ca" ], "author": { "name": "Alan Stern", "email": "stern@rowland.harvard.edu", "time": "Mon Apr 27 13:33:16 2009 -0400" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Mon Jun 15 21:44:44 2009 -0700" }, "message": "PCI: add power-state name strings\n\nThis patch (as1235) adds an array of PCI power-state names, together\nwith a simple inline accessor routine.\n\nSigned-off-by: Alan Stern \u003cstern@rowland.harvard.edu\u003e\nAcked-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n" }, { "commit": "43c16408842b0eeb367c23a6fa540ce69f99e347", "tree": "25be054b280b430b8bb00ff5f9c1f422bc21a3a0", "parents": [ "f62795f1e892ca9269849fa83de97621da7e02c0" ], "author": { "name": "Andrew Patterson", "email": "andrew.patterson@hp.com", "time": "Wed Apr 22 16:52:09 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 11 12:04:21 2009 -0700" }, "message": "PCI: Add support for turning PCIe ECRC on or off\n\nAdds support for PCI Express transaction layer end-to-end CRC checking\n(ECRC). This patch will enable/disable ECRC checking by setting/clearing\nthe ECRC Check Enable and/or ECRC Generation Enable bits for devices that\nsupport ECRC.\n\nThe ECRC setting is controlled by the \"pci\u003decrc\u003d\u003cpolicy\u003e\" command-line\noption. If this option is not set or is set to \u0027bios\", the enable and\ngeneration bits are left in whatever state that firmware/BIOS set them to.\nThe \"off\" setting turns them off, and the \"on\" option turns them on (if the\ndevice supports it).\n\nTurning ECRC on or off can be a data integrity versus performance\ntradeoff. In theory, turning it on will catch more data errors, turning\nit off means possibly better performance since CRC does not need to be\ncalculated by the PCIe hardware and packet sizes are reduced.\n\nSigned-off-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "3b073eda9557975a87a27b08a46a545fe8da66fb", "tree": "11fe4c053294f5ed8343258e113d91ff49435e9c", "parents": [ "12a9da0fcb147b46de33bb919b1de2bb92c9e2a9" ], "author": { "name": "Alex Chiang", "email": "achiang@hp.com", "time": "Tue Mar 31 09:24:22 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 11 12:04:16 2009 -0700" }, "message": "PCI: remove deprecated pci_find_slot() interface\n\nThe last in-tree caller of pci_find_slot has been converted, so\nlet\u0027s get rid of this deprecated interface.\n\nSigned-off-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "1f82de10d6b1d845155363c895c552e61b36b51a", "tree": "3e93b9d1c97ae48509133fbbec9c81b4823816a5", "parents": [ "67b5db6502ddd27d65dea43bf036abbd82d0dfc9" ], "author": { "name": "Yinghai Lu", "email": "yinghai@kernel.org", "time": "Thu Apr 23 20:48:32 2009 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Thu Jun 11 12:04:06 2009 -0700" }, "message": "PCI/x86: don\u0027t assume prefetchable ranges are 64bit\n\nWe should not assign 64bit ranges to PCI devices that only take 32bit\nprefetchable addresses.\n\nTry to set IORESOURCE_MEM_64 in 64bit resource of pci_device/pci_bridge\nand make the bus resource only have that bit set when all devices under\nit support 64bit prefetchable memory. Use that flag to allocate\nresources from that range.\n\nReported-by: Yannick \u003cyannick.roehlly@free.fr\u003e\nReviewed-by: Ivan Kokshaysky \u003cink@jurassic.park.msu.ru\u003e\nSigned-off-by: Yinghai Lu \u003cyinghai@kernel.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "302b4215daa0a704c843da40fd2529e5757a72da", "tree": "1bc40108fceafd3fbc9faee38c971fa94d560b13", "parents": [ "dd7264355a203c3456dbba04db471947d3b55e7e" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Mon May 18 13:51:32 2009 +0800" }, "committer": { "name": "David Woodhouse", "email": "David.Woodhouse@intel.com", "time": "Mon May 18 11:25:54 2009 +0100" }, "message": "PCI: support the ATS capability\n\nThe PCIe ATS capability makes the Endpoint be able to request the\nDMA address translation from the IOMMU and cache the translation\nin the device side, thus alleviate IOMMU pressure and improve the\nhardware performance in the I/O virtualization environment.\n\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: David Woodhouse \u003cDavid.Woodhouse@intel.com\u003e\n" }, { "commit": "296ccb086dfb89b5b8d73ef08c795ffdff12a597", "tree": "8c4ef0f0271e448b6843811a1bcded8c47c005a1", "parents": [ "7eb93b175d4de9438a4b0af3a94a112cb5266944" ], "author": { "name": "Yuji Shimada", "email": "shimada-yxb@necst.nec.co.jp", "time": "Fri Apr 03 16:41:46 2009 +0900" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Apr 06 11:25:06 2009 -0700" }, "message": "PCI: Setup disabled bridges even if buses are added\n\nThis patch sets up disabled bridges even if buses have already been\nadded.\n\npci_assign_unassigned_resources is called after buses are added.\npci_assign_unassigned_resources calls pci_bus_assign_resources.\npci_bus_assign_resources calls pci_setup_bridge to configure BARs of\nbridges.\n\nCurrently pci_setup_bridge returns immediately if the bus have already\nbeen added. So pci_assign_unassigned_resources can\u0027t configure BARs of\nbridges that were added in a disabled state; this patch fixes the issue.\n\nOn logical hot-add, we need to prevent the kernel from re-initializing\nbridges that have already been initialized. To achieve this,\npci_setup_bridge returns immediately if the bridge have already been\nenabled.\n\nWe don\u0027t need to check whether the specified bus is a root bus or not.\npci_setup_bridge is not called on a root bus, because a root bus does\nnot have a bridge.\n\nThe patch adds a new helper function, pci_is_enabled. I made the\nfunction name similar to pci_is_managed. The codes which use\nenable_cnt directly are changed to use pci_is_enabled.\n\nAcked-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Yuji Shimada \u003cshimada-yxb@necst.nec.co.jp\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "e76e5b2c663ac74ae6a542ac20795c625e36a5cd", "tree": "2e7271be1f3a26832f4b121839fc4044fbbf27a6", "parents": [ "32527bc0e4b4fa7711ad1c923cf64ae72a7ffd9d", "eeafda70bf2807544e96fa4e52b2433cd470ff46" ], "author": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Apr 01 09:47:12 2009 -0700" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@linux-foundation.org", "time": "Wed Apr 01 09:47:12 2009 -0700" }, "message": "Merge branch \u0027linux-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6\n\n* \u0027linux-next\u0027 of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: (88 commits)\n PCI: fix HT MSI mapping fix\n PCI: don\u0027t enable too much HT MSI mapping\n x86/PCI: make pci\u003dlastbus\u003d255 work when acpi is on\n PCI: save and restore PCIe 2.0 registers\n PCI: update fakephp for bus_id removal\n PCI: fix kernel oops on bridge removal\n PCI: fix conflict between SR-IOV and config space sizing\n powerpc/PCI: include pci.h in powerpc MSI implementation\n PCI Hotplug: schedule fakephp for feature removal\n PCI Hotplug: rename legacy_fakephp to fakephp\n PCI Hotplug: restore fakephp interface with complete reimplementation\n PCI: Introduce /sys/bus/pci/devices/.../rescan\n PCI: Introduce /sys/bus/pci/devices/.../remove\n PCI: Introduce /sys/bus/pci/rescan\n PCI: Introduce pci_rescan_bus()\n PCI: do not enable bridges more than once\n PCI: do not initialize bridges more than once\n PCI: always scan child buses\n PCI: pci_scan_slot() returns newly found devices\n PCI: don\u0027t scan existing devices\n ...\n\nFix trivial append-only conflict in Documentation/feature-removal-schedule.txt\n" }, { "commit": "0e5dd46b761195356065a30611f265adec286d0d", "tree": "4ca10dac14ac44789a51048c4ceb3989be175f63", "parents": [ "931ff68a5a53fa84bcdf9b1b179a80e54e034bd0" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Thu Mar 26 22:51:40 2009 +0100" }, "committer": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Mon Mar 30 21:46:56 2009 +0200" }, "message": "PCI PM: Introduce __pci_[start|complete]_power_transition() (rev. 2)\n\nThe radeonfb driver needs to program the device\u0027s PMCSR directly due\nto some quirky hardware it has to handle (see\nhttp://bugzilla.kernel.org/show_bug.cgi?id\u003d12846 for details) and\nafter doing that it needs to call the platform (usually ACPI) to\nfinish the power transition of the device. Currently it uses\npci_set_power_state() for this purpose, however making a specific\nassumption about the internal behavior of this function, which has\nchanged recently so that this assumption is no longer satisfied.\nFor this reason, introduce __pci_complete_power_transition() that may\nbe called by the radeonfb driver to complete the power transition of\nthe device. For symmetry, introduce __pci_start_power_transition().\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nAcked-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "3ed4fd96b3188406ac5357d9290bcffa08c65cf6", "tree": "1e48401b56c35554e84c8d627c6c04e83a999a9e", "parents": [ "9dd90cafa7a712d283e2e0c625b022e19f746762" ], "author": { "name": "Alex Chiang", "email": "achiang@hp.com", "time": "Fri Mar 20 14:56:25 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 14:57:44 2009 -0700" }, "message": "PCI: Introduce pci_rescan_bus()\n\nThis API is used by the PCI core to rescan a bus and rediscover\nnewly added devices.\n\nOver time, it is expected that the various PCI hotplug drivers\nwill migrate to this interface and away from the old\npci_do_scan_bus() interface.\n\nSigned-off-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "79af72d716cf1bb13b175429cf181a6c4d063ee8", "tree": "2665c3e34983c8bcaf5fec76480fda163a88b045", "parents": [ "068258bc15439c11a966e873f931cc8e513dca61" ], "author": { "name": "Kenji Kaneshige", "email": "kaneshige.kenji@jp.fujitsu.com", "time": "Fri Mar 20 14:55:55 2009 -0600" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 14:56:36 2009 -0700" }, "message": "PCI: pci_is_root_bus helper\n\nIntroduce pci_is_root_bus helper function. This will help make code\nmore consistent, as well as prevent incorrect assumptions (such as\npci_bus-\u003eself \u003d\u003d NULL on a root bus, which is not always true).\n\nSigned-off-by: Kenji Kaneshige \u003ckaneshige.kenji@jp.fujitsu.com\u003e\nSigned-off-by: Alex Chiang \u003cachiang@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "74bb1bcc7dbbc9ddef773bf3395d7ff92aaaad2e", "tree": "38dd25aed251b00a4b34612320beb64f4a058814", "parents": [ "dd7cc44d0bcec5e9c42fe52e88dc254ae62eac8d" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Fri Mar 20 11:25:16 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 10:48:28 2009 -0700" }, "message": "PCI: handle SR-IOV Virtual Function Migration\n\nAdd or remove a Virtual Function after receiving a Migrate In or Out\nRequest.\n\nReviewed-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "dd7cc44d0bcec5e9c42fe52e88dc254ae62eac8d", "tree": "742b2c903580eded1e352988b068c0362eccc634", "parents": [ "480b93b7837fb3cf0579a42f4953ac463a5b9e1e" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Fri Mar 20 11:25:15 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 10:48:26 2009 -0700" }, "message": "PCI: add SR-IOV API for Physical Function driver\n\nAdd or remove the Virtual Function when the SR-IOV is enabled or\ndisabled by the device driver. This can happen anytime rather than\nonly at the device probe stage.\n\nReviewed-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "d1b054da8f599905f3c18a218961dcf17f9d5f13", "tree": "99b62e6771c3b73142dd0622463bed0e19724342", "parents": [ "8293b0f629095efbe7c7e3f9b437f8c040c19eb5" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Fri Mar 20 11:25:11 2009 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 10:48:22 2009 -0700" }, "message": "PCI: initialize and release SR-IOV capability\n\nIf a device has the SR-IOV capability, initialize it (set the ARI\nCapable Hierarchy in the lowest numbered PF if necessary; calculate\nthe System Page Size for the VF MMIO, probe the VF Offset, Stride\nand BARs). A lock for the VF bus allocation is also initialized if\na PF is the lowest numbered PF.\n\nReviewed-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "1c8d7b0a562da06d3ebe83f01b1ed553205d1ae4", "tree": "79c84432f5aed5a08b3bef262a10d933daae6a9b", "parents": [ "f2440d9acbe866b917b16cc0f927366341ce9215" ], "author": { "name": "Matthew Wilcox", "email": "willy@linux.intel.com", "time": "Tue Mar 17 08:54:10 2009 -0400" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Mar 20 10:48:14 2009 -0700" }, "message": "PCI MSI: Add support for multiple MSI\n\nAdd the new API pci_enable_msi_block() to allow drivers to\nrequest multiple MSI and reimplement pci_enable_msi in terms of\npci_enable_msi_block. Ensure that the architecture back ends don\u0027t\nhave to know about multiple MSI.\n\nSigned-off-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "ea7415512a07add2b09c070c9a5d1950833cf9b3", "tree": "1c0d7468f57d38f74f4649cb9f4655b1937cf2a0", "parents": [ "c48f1670f42b71f39f4a3bfba01ffb691cc9206c" ], "author": { "name": "Andrew Morton", "email": "akpm@linux-foundation.org", "time": "Wed Feb 18 10:44:29 2009 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@hobbes.lan", "time": "Thu Mar 19 19:29:35 2009 -0700" }, "message": "PCI: constify pci_bus_assign_resources()\n\ndrivers/pci/hotplug/fakephp.c: In function \u0027pci_rescan_bus\u0027:\ndrivers/pci/hotplug/fakephp.c:271: warning: passing argument 1 of \u0027pci_bus_assign_resources\u0027 discards qualifiers from pointer target type\n\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "c48f1670f42b71f39f4a3bfba01ffb691cc9206c", "tree": "a407190fd3141b9d0bbb4a861f334f0bb4be6143", "parents": [ "b5fbf53324f65646154e172af350674d5a2a1629" ], "author": { "name": "akpm@linux-foundation.org", "email": "akpm@linux-foundation.org", "time": "Tue Feb 03 15:45:26 2009 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@hobbes.lan", "time": "Thu Mar 19 19:29:35 2009 -0700" }, "message": "PCI: constify pci_bus_add_devices()\n\ndrivers/pci/hotplug/fakephp.c:283: warning: passing argument 1 of \u0027pci_bus_add_devices\u0027 discards qualifiers from pointer target type\n\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "a52e2e3513d4beafe8fe8699f1519b021c2d05ba", "tree": "4a2aea26275e0ffe58e53629e50696b559b8c6e0", "parents": [ "a447b772826fde2a3abfd9bb943dee8750994c55" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Sat Jan 24 00:21:14 2009 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@hobbes.lan", "time": "Thu Mar 19 19:29:25 2009 -0700" }, "message": "PCI/MSI: Introduce pci_msix_table_size()\n\nIntroduce new function pci_msix_table_size() returning the size of\nthe MSI-X table of given PCI device or 0 if the device doesn\u0027t\nsupport MSI-X.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nReviewed-by: Hidetoshi Seto \u003cseto.hidetoshi@jp.fujitsu.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "97c44836cdec1ea713a15d84098a1a908157e68f", "tree": "bc544c64ed8eeb3feb2f0b210ae7db04a40e1bae", "parents": [ "3419c75e15f82c3ab09bd944fddbde72c9e4b3ea" ], "author": { "name": "Timothy S. Nelson", "email": "wayland@wayland.id.au", "time": "Fri Jan 30 06:12:47 2009 +1100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Feb 04 16:58:41 2009 -0800" }, "message": "PCI: return error on failure to read PCI ROMs\n\nThis patch makes the ROM reading code return an error to user space if\nthe size of the ROM read is equal to 0.\n\nThe patch also emits a warnings if the contents of the ROM are invalid,\nand documents the effects of the \"enable\" file on ROM reading.\n\nSigned-off-by: Timothy S. Nelson \u003cwayland@wayland.id.au\u003e\nAcked-by: Alex Villacis-Lasso \u003ca_villacis@palosanto.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "aa8c6c93747f7b55fa11e1624fec8ca33763a805", "tree": "e40bf643ec9916dd2738ef9aaafdfa49ad8b4781", "parents": [ "0db29af1e767464d71b89410d61a1e5b668d0370" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Fri Jan 16 21:54:43 2009 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Fri Jan 16 12:57:58 2009 -0800" }, "message": "PCI PM: Restore standard config registers of all devices early\n\nThere is a problem in our handling of suspend-resume of PCI devices that\nmany of them have their standard config registers restored with\ninterrupts enabled and they are put into the full power state with\ninterrupts enabled as well. This may lead to the following scenario:\n * an interrupt vector is shared between two or more devices\n * one device is resumed earlier and generates an interrupt\n * the interrupt handler of another device tries to handle it and\n attempts to access the device the config space of which hasn\u0027t been\n restored yet and/or which still is in a low power state\n * the system crashes as a result\n\nTo prevent this from happening we should restore the standard\nconfiguration registers of all devices with interrupts disabled and we\nshould put them into the D0 power state right after that.\nUnfortunately, this cannot be done using the existing\npci_set_power_state(), because it can sleep. Also, to do it we have to\nmake sure that the config spaces of all devices were actually saved\nduring suspend.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nAcked-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "16cf0ebc35dd63f72628ba1246132a6fd17bced2", "tree": "502bfcaac930695eb7f4ff8d7748f913b9accb83", "parents": [ "ef1bba28bfe68ef3c0488feeaabd3e8bc523130c" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Mon Jan 05 14:50:27 2009 +0100" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Jan 07 11:13:25 2009 -0800" }, "message": "x86/PCI: Do not use interrupt links for devices using MSI-X\n\npcibios_enable_device() and pcibios_disable_device() don\u0027t handle\nIRQs for devices that have MSI enabled and it should treat the\ndevices with MSI-X enabled in the same way.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nAcked-by: Ingo Molnar \u003cmingo@elte.hu\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "6a479079c07211bf348ac8a79754f26bea258f26", "tree": "1587c0ed9446c7d0d6ab8a38d1524132e2faae35", "parents": [ "b8d9cb2a2226118fd71f657c80b06b670a653022" ], "author": { "name": "Ben Hutchings", "email": "bhutchings@solarflare.com", "time": "Tue Dec 23 03:08:29 2008 +0000" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Jan 07 11:13:23 2009 -0800" }, "message": "PCI: Add pci_clear_master() as opposite of pci_set_master()\n\nDuring an online device reset it may be useful to disable bus-mastering.\npci_disable_device() does that, and far more besides, so is not suitable\nfor an online reset.\n\nAdd pci_clear_master() which does just this.\n\nSigned-off-by: Ben Hutchings \u003cbhutchings@solarflare.com\u003e\nReviewed-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "db5679437a2b938c9127480a3923633721583a4f", "tree": "b2625345baa35490104b81fc1c7bd8ef6bb74100", "parents": [ "287d19ce2e67c15e79a187b3bdcbbea1a0a51a7d" ], "author": { "name": "Stephen Hemminger", "email": "shemminger@vyatta.com", "time": "Thu Dec 18 09:17:16 2008 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Jan 07 11:13:18 2009 -0800" }, "message": "PCI: add interface to set visible size of VPD\n\nThe VPD on all devices may not be 32K. Unfortunately, there is no\ngeneric way to find the size, so this adds a simple API hook\nto reset it.\n\nSigned-off-by: Stephen Hemminger \u003cshemminger@vyatta.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "287d19ce2e67c15e79a187b3bdcbbea1a0a51a7d", "tree": "128d9c67557a4fe5e5e910b8ca2d50aedee31b7c", "parents": [ "1120f8b8169fb2cb51219d326892d963e762edb6" ], "author": { "name": "Stephen Hemminger", "email": "shemminger@vyatta.com", "time": "Thu Dec 18 09:17:16 2008 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Jan 07 11:13:17 2009 -0800" }, "message": "PCI: revise VPD access interface\n\nChange PCI VPD API which was only used by sysfs to something usable\nin drivers.\n * move iteration over multiple words to the low level\n * use conventional types for arguments\n * add exportable wrapper\n\nSigned-off-by: Stephen Hemminger \u003cshemminger@vyatta.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "68feac87de15edfc2c700d2d81b814288c93d003", "tree": "97ee9f0dc3ee3728aca7d5a252eda6a1cb633430", "parents": [ "e8c331e963c58b83db24b7d0e39e8c07f687dbc6" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Tue Dec 16 21:36:55 2008 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Jan 07 11:13:12 2009 -0800" }, "message": "PCI: add pci_common_swizzle() for INTx swizzling\n\nThis patch adds pci_common_swizzle(), which swizzles INTx values all the\nway up to a root bridge.\n\nThis common implementation can replace several architecture-specific\nones. This should someday be combined with pci_get_interrupt_pin(),\nbut I left it separate for now to make reviewing easier.\n\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "fde09c6d8f92de0c9f75698a75f0989f2234c517", "tree": "7d01ac3c194e87897185a2bf015f6d3b472e7601", "parents": [ "14add80b5120966fe0659d61815b9e9b4b68fdc5" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Sat Nov 22 02:39:32 2008 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Jan 07 11:13:01 2009 -0800" }, "message": "PCI: define PCI resource names in an \u0027enum\u0027\n\nThis patch moves all definitions of the PCI resource names to an \u0027enum\u0027,\nand also replaces some hard-coded resource variables with symbol\nnames. This change eases introduction of device specific resources.\n\nReviewed-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "14add80b5120966fe0659d61815b9e9b4b68fdc5", "tree": "7f803ec36d14e76fb0bc672717bd0dd3dea30a08", "parents": [ "6a49d8120021897e139641062236215aac5d220e" ], "author": { "name": "Yu Zhao", "email": "yu.zhao@intel.com", "time": "Sat Nov 22 02:38:52 2008 +0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Jan 07 11:13:00 2009 -0800" }, "message": "PCI: remove unnecessary arg of pci_update_resource()\n\nThis cleanup removes unnecessary argument \u0027struct resource *res\u0027 in\npci_update_resource(), so it takes same arguments as other companion\nfunctions (pci_assign_resource(), etc.).\n\nSigned-off-by: Yu Zhao \u003cyu.zhao@intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "1684f5ddd4c0c754f52c78eaa2c5c69ad09fb18c", "tree": "1085974a81fba002bcc05cdd88a11134ec13799c", "parents": [ "bebd590ca27e80ffe3129ab4f0a3124f0a340f43" ], "author": { "name": "Andrew Morton", "email": "akpm@linux-foundation.org", "time": "Mon Dec 01 14:30:30 2008 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Jan 07 11:12:57 2009 -0800" }, "message": "PCI: uninline pci_ioremap_bar()\n\nIt\u0027s too large to be inlined.\n\nAcked-by: Arjan van de Ven \u003carjan@linux.intel.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "57c2cf71c12318b72ebaa5720d210476b6bac4d4", "tree": "ba071276800dc24d9232fd124c4678b2a86f86b5", "parents": [ "12b955ff63db0b75cfc2d4939696c57b31891ec6" ], "author": { "name": "Bjorn Helgaas", "email": "bjorn.helgaas@hp.com", "time": "Thu Dec 11 11:24:23 2008 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Jan 07 11:12:50 2009 -0800" }, "message": "PCI: add pci_swizzle_interrupt_pin()\n\nThis patch adds pci_swizzle_interrupt_pin(), which implements the\nINTx swizzling algorithm specified in Table 9-1 of the \"PCI-to-PCI\nBridge Architecture Specification,\" revision 1.2.\n\nThere are many architecture-specific implementations of this\nswizzle that can be replaced by this common one.\n\nReviewed-by: David Howells \u003cdhowells@redhat.com\u003e\nSigned-off-by: Bjorn Helgaas \u003cbjorn.helgaas@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "e8de1481fd7126ee9e93d6889da6f00c05e1e019", "tree": "3e0e564f6aff2f8f0f66bdf37dc2eb87d6e17cde", "parents": [ "23616941914917cf25b94789856b5326b68d8ee8" ], "author": { "name": "Arjan van de Ven", "email": "arjan@linux.intel.com", "time": "Wed Oct 22 19:55:31 2008 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Jan 07 11:12:32 2009 -0800" }, "message": "resource: allow MMIO exclusivity for device drivers\n\nDevice drivers that use pci_request_regions() (and similar APIs) have a\nreasonable expectation that they are the only ones accessing their device.\nAs part of the e1000e hunt, we were afraid that some userland (X or some\nbootsplash stuff) was mapping the MMIO region that the driver thought it\nhad exclusively via /dev/mem or via various sysfs resource mappings.\n\nThis patch adds the option for device drivers to cause their reserved\nregions to the \"banned from /dev/mem use\" list, so now both kernel memory\nand device-exclusive MMIO regions are banned.\nNOTE: This is only active when CONFIG_STRICT_DEVMEM is set.\n\nIn addition to the config option, a kernel parameter iomem\u003drelaxed is\nprovided for the cases where developers want to diagnose, in the field,\ndrivers issues from userspace.\n\nReviewed-by: Matthew Wilcox \u003cwilly@linux.intel.com\u003e\nSigned-off-by: Arjan van de Ven \u003carjan@linux.intel.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "07ae95f988a34465bdcb384bfa73c03424fe2312", "tree": "4e1901b7fd2ccfdb85a92953c0010a4d3900a3f8", "parents": [ "eb9188bdb9d65aeead2382ec3dd656a17ec8936d" ], "author": { "name": "Andrew Patterson", "email": "andrew.patterson@hp.com", "time": "Mon Nov 10 15:31:05 2008 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Jan 07 11:12:31 2009 -0800" }, "message": "ACPI/PCI: PCI MSI _OSC support capabilities called when root bridge added\n\nThe _OSC capability OSC_MSI_SUPPORT is set when the root bridge is added\nwith pci_acpi_osc_support(), so we no longer need to do it in the PCI\nMSI driver. Also adds the function pci_msi_enabled, which returns true\nif pci\u003dnomsi is not on the kernel command-line.\n\nSigned-off-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "3e1b16002af29758b6bc9c38939d43838d9335bc", "tree": "6782f844e3813355280ad3367c58d90d576901f2", "parents": [ "0ef5f8f6159e44b4faa997be08d1a3bcbf44ad08" ], "author": { "name": "Andrew Patterson", "email": "andrew.patterson@hp.com", "time": "Mon Nov 10 15:30:55 2008 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Jan 07 11:12:29 2009 -0800" }, "message": "ACPI/PCI: PCIe ASPM _OSC support capabilities called when root bridge added\n\nThe _OSC capabilities OSC_ACTIVE_STATE_PWR_SUPPORT and\nOSC_CLOCK_PWR_CAPABILITY_SUPPORT are set when the root bridge is added\nwith pci_acpi_osc_support(), so we no longer need to do it in the ASPM\ndriver. Also add the function pcie_aspm_enabled, which returns true if\npcie_aspm\u003doff is not on the kernel command-line.\n\nSigned-off-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "0ef5f8f6159e44b4faa997be08d1a3bcbf44ad08", "tree": "0753c27a1eb2f5802501e60d575f01fe6edccc2f", "parents": [ "990a7ac5645883a833a11b900bb6f25b65dea65b" ], "author": { "name": "Andrew Patterson", "email": "andrew.patterson@hp.com", "time": "Mon Nov 10 15:30:50 2008 -0700" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Wed Jan 07 11:12:28 2009 -0800" }, "message": "ACPI/PCI: PCI extended config _OSC support called when root bridge added\n\nThe _OSC capability OSC_EXT_PCI_CONFIG_SUPPORT is set when the root\nbridge is added with pci_acpi_osc_support() if we can access PCI\nextended config space.\n\nThis adds the function pci_ext_cfg_avail which returns true if we can\naccess PCI extended config space (offset greater than 0xff). It\ncurrently only returns false if arch\u003dx86 and raw_pci_ext_ops is not set\n(which might happen if pci\u003dnommcfg is set on the kernel command-line).\n\nSigned-off-by: Andrew Patterson \u003candrew.patterson@hp.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" }, { "commit": "adf094931ffb25ef4b381559918f1a34181a5273", "tree": "bd343d4c15b21dff6a73359fd2d82ff77e30e0d4", "parents": [ "238c6d54830c624f34ac9cf123ac04aebfca5013" ], "author": { "name": "Rafael J. Wysocki", "email": "rjw@sisk.pl", "time": "Mon Oct 06 22:46:05 2008 +0200" }, "committer": { "name": "Greg Kroah-Hartman", "email": "gregkh@suse.de", "time": "Tue Jan 06 10:44:29 2009 -0800" }, "message": "PM: Simplify the new suspend/hibernation framework for devices\n\nPM: Simplify the new suspend/hibernation framework for devices\n\nFollowing the discussion at the Kernel Summit, simplify the new\ndevice PM framework by merging \u0027struct pm_ops\u0027 and\n\u0027struct pm_ext_ops\u0027 and removing pointers to \u0027struct pm_ext_ops\u0027\nfrom \u0027struct platform_driver\u0027 and \u0027struct pci_driver\u0027.\n\nAfter this change, the suspend/hibernation callbacks will only\nreside in \u0027struct device_driver\u0027 as well as at the bus type/\ndevice class/device type level. Accordingly, PCI and platform\ndevice drivers are now expected to put their suspend/hibernation\ncallbacks into the \u0027struct device_driver\u0027 embedded in\n\u0027struct pci_driver\u0027 or \u0027struct platform_driver\u0027, respectively.\n\nSigned-off-by: Rafael J. Wysocki \u003crjw@sisk.pl\u003e\nAcked-by: Pavel Machek \u003cpavel@suse.cz\u003e\nCc: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\nSigned-off-by: Greg Kroah-Hartman \u003cgregkh@suse.de\u003e\n\n" }, { "commit": "fa623d1b0222adbe8f822e53c08003b9679a410c", "tree": "261a320f3fbf88fab8a3203419ca4d71bdf49152", "parents": [ "3d44cc3e01ee1b40317f79ed54324e25c4f848df", "1ccedb7cdba6886939dd8b4c8f965a826f696e56", "34945ede31071ac7d72270cc6c1893323f392b3f", "d4377974062122d6d9be0bbd8a910a0954714194", "c415b3dce30dfb41234e118662e8720f47343a4f", "beeb4195cbc80b7489631361b7ed38b7518af433", "f269b07e862c395d6981ab2c05d6bc34b0249e90", "4e42ebd57b2e727b28bf5f6068e95cd19b0e807b", "e1286f2c686f5976e0424bb6195ece25e7a17607", "878719e831d9e076961aa15d4049a57a6668c67a", "fd28a5b58dddf5cb5df162ae5c8797a63171c31d", "adf77bac052bb5bf0722b2ce2af9fefc5b2d2a71", "8f2466f45f75e3cbe3aa2b69d33fd9d6e343b9cc", "93093d099e5dd0c258fd530c12668e828c20df41", "bb5574608a8375026510b4f983ffbb06ece33fe2", "f34a10bd9f8cc95ebdc69a079db195636b2e22e0", "b6fd6f26733e864fba2ea3eb1d716e23d2e66f3a", "30604bb410b53efa9c93ee8f03d7aa7494094faa", "5b9a0e14eb4bf40a7cb780af4723560e06753f2d", "67bac792cd0c05b4b6e0393c32605b028b8dd533", "7a9787e1eba95a166265e6a260cf30af04ef0a99", "f4166c54bfe04f64603974058e44fbd7cfef0ccc", "69b88afa8d114a43a3c0431722b79e31d9920692", "8daa19051e1c7369c89ace7b18e74fe1f55dfa29", "3e1e9002aa8b32bd4c95ac6c8fad376b7a8127fb", "8403295e0fa460f6240e2d781e25dc29189f33c7", "4db646b1af8fdcf01d690d29eeae44cd937edb0d", "205516c12dbba003c26b42cfb41e598631300106", "c8182f0016fb65a721c4fbe487909a2d56178135", "ecbf29cdb3990c83d90d0c4187c89fb2ce423367" ], "author": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Tue Dec 23 16:27:23 2008 +0100" }, "committer": { "name": "Ingo Molnar", "email": "mingo@elte.hu", "time": "Tue Dec 23 16:27:23 2008 +0100" }, "message": "Merge branches \u0027x86/apic\u0027, \u0027x86/cleanups\u0027, \u0027x86/cpufeature\u0027, \u0027x86/crashdump\u0027, \u0027x86/debug\u0027, \u0027x86/defconfig\u0027, \u0027x86/detect-hyper\u0027, \u0027x86/doc\u0027, \u0027x86/dumpstack\u0027, \u0027x86/early-printk\u0027, \u0027x86/fpu\u0027, \u0027x86/idle\u0027, \u0027x86/io\u0027, \u0027x86/memory-corruption-check\u0027, \u0027x86/microcode\u0027, \u0027x86/mm\u0027, \u0027x86/mtrr\u0027, \u0027x86/nmi-watchdog\u0027, \u0027x86/pat2\u0027, \u0027x86/pci-ioapic-boot-irq-quirks\u0027, \u0027x86/ptrace\u0027, \u0027x86/quirks\u0027, \u0027x86/reboot\u0027, \u0027x86/setup-memory\u0027, \u0027x86/signal\u0027, \u0027x86/sparse-fixes\u0027, \u0027x86/time\u0027, \u0027x86/uv\u0027 and \u0027x86/xen\u0027 into x86/core\n" }, { "commit": "a7b930cdf8ec790c85f81416c87f7c066679d373", "tree": "c96fe44a2160311461b886f2e3ee941f5ba0a682", "parents": [ "bffadffd43d438c3143b8d172a463de89345b836" ], "author": { "name": "Harvey Harrison", "email": "harvey.harrison@gmail.com", "time": "Sun Nov 02 13:32:43 2008 -0800" }, "committer": { "name": "Jesse Barnes", "email": "jbarnes@virtuousgeek.org", "time": "Mon Nov 03 14:31:18 2008 -0800" }, "message": "PCI: annotate return value of pci_ioremap_bar with __iomem\n\nWas missing from the initial patch.\n\nAcked-by: Arjan van de Ven \u003carjan@linux.intel.com\u003e\nSigned-off-by: Harvey Harrison \u003charvey.harrison@gmail.com\u003e\nSigned-off-by: Jesse Barnes \u003cjbarnes@virtuousgeek.org\u003e\n" } ], "next": "7a9787e1eba95a166265e6a260cf30af04ef0a99" }