)]}' { "log": [ { "commit": "837f5f8fb98d4357d49e9631c9ee2815f3c328ca", "tree": "25c24b611fd66b0599d8145716513339d42a7bb3", "parents": [ "f351b2d638c3cb0b95adde3549b7bfaf3f991dfa" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Wed Feb 06 15:13:51 2008 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Wed Feb 06 06:59:27 2008 -0500" }, "message": "ahci: fix CAP.NP and PI handling\n\nAHCI uses CAP.NP to indicate the number of ports and PI to tell which\nports are enabled. The only requirement is that the number of ports\nindicated by CAP.NP should equal or be higher than the number of\nenabled ports in PI.\n\nCAP.NP and PI carry duplicate information and there have been some\ninteresting cases. Some early AHCI controllers didn\u0027t set PI at all\nand just implement from port 0 to CAP.NP. An ICH8 board which wired\nfour out of six available ports had 3 (4 ports) for CAP.NP and 0x33\nfor PI. While ESB2 has less bits set in PI than the value in CAP.NP.\n\nTill now, ahci driver assumed that PI is invalid if it doesn\u0027t match\nCAP.NP exactly. This violates AHCI standard and the driver ends up\naccessing unmimplemented ports on ESB2.\n\nThis patch updates CAP.NP and PI handling such that PI can have less\nnumber of bits set than indicated in CAP.NP and the highest port is\ndetermined as the maximum port of what CAP.NP and PI indicate.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nCc: Jan Beulich \u003cjbeulich@novell.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "16ad1ad9cbce153f4bfed22f9b9a6db4ae212fc7", "tree": "78dcdaa5f7effda33c6d93c8ef56fc5f0c8c0830", "parents": [ "da2fa9baf06f33a8fa7aa3f56c9f2b4070ceca0e" ], "author": { "name": "Jason Gaston", "email": "jason.d.gaston@intel.com", "time": "Mon Jan 28 17:34:14 2008 -0800" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Feb 01 11:29:48 2008 -0500" }, "message": "ahci: RAID mode SATA patch for Intel ICH10 DeviceID\u0027s\n\nThis patch adds the Intel ICH10 SATA RAID Controllers DeviceID\u0027s.\n\nSigned-off-by: Jason Gaston \u003cjason.d.gaston@intel.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "b710a1f4b34438b624e9c6c2dc8bcf54b0b0ba27", "tree": "f8bb87bd4cbc2591da8c0b9bdaf01b426902800b", "parents": [ "c729072459446885c5c200137de1db32da5db4dc" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Sat Jan 05 23:11:57 2008 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Wed Jan 23 05:24:16 2008 -0500" }, "message": "ahci: factor out AHCI enabling and enable AHCI before reading CAP\n\nFactor out AHCI enabling into ahci_enable_ahci() and enabling AHCI\nbefore reading CAP in ahci_save_initial_config() as the spec requires\nenabling AHCI mode before accessing any other registers.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "4ca4e439640cd1d3659cbcf60e7a73c2ae0450b3", "tree": "659dceb7469341dca95d7a96774e787c3b510872", "parents": [ "35a10a80daa04b7316d6bac1b1402cc347c35b1e" ], "author": { "name": "Al Viro", "email": "viro@ZenIV.linux.org.uk", "time": "Sun Dec 30 09:32:22 2007 +0000" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Wed Jan 23 05:24:15 2008 -0500" }, "message": "libata annotations and fixes\n\nSigned-off-by: Al Viro \u003cviro@zeniv.linux.org.uk\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "ff2aeb1eb64c8a4770a6304f9addbae9f9828646", "tree": "c6febbec290ec6c40bf3abc7bcdb7188f5039443", "parents": [ "f92a26365a72333f418abe82700c6030d4a1a807" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Wed Dec 05 16:43:11 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Wed Jan 23 05:24:14 2008 -0500" }, "message": "libata: convert to chained sg\n\nlibata used private sg iterator to handle padding sg. Now that sg can\nbe chained, padding can be handled using standard sg ops. Convert to\nchained sg.\n\n* s/qc-\u003e__sg/qc-\u003esg/\n\n* s/qc-\u003epad_sgent/qc-\u003eextra_sg[]/. Because chaining consumes one sg\n entry. There need to be two extra sg entries. The renaming is also\n for future addition of other extra sg entries.\n\n* Padding setup is moved into ata_sg_setup_extra() which is organized\n in a way that future addition of other extra sg entries is easy.\n\n* qc-\u003eorig_n_elem is unused and removed.\n\n* qc-\u003en_elem now contains the number of sg entries that LLDs should\n map. qc-\u003emapped_n_elem is added to carry the original number of\n mapped sgs for unmapping.\n\n* The last sg of the original sg list is used to chain to extra sg\n list. The original last sg is pointed to by qc-\u003elast_sg and the\n content is stored in qc-\u003esaved_last_sg. It\u0027s restored during\n ata_sg_clean().\n\n* All sg walking code has been updated. Unnecessary assertions and\n checks for conditions the core layer already guarantees are removed.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nCc: Jens Axboe \u003cjens.axboe@oracle.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "405e66b38797875e80669eaf72d313dbb76533c3", "tree": "a069f0bb4ae1e81a58bc8f8965a2443d25186f0d", "parents": [ "f20ded38aa54b92dd0af32578b8916d0aa2d9e05" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Tue Nov 27 19:28:53 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Wed Jan 23 05:24:10 2008 -0500" }, "message": "libata: implement protocol tests\n\nImplement protocol tests - ata_is_atapi(), ata_is_nodata(),\nata_is_pio(), ata_is_dma(), ata_is_ncq() and ata_is_data() and use\nthem to replace is_atapi_taskfile() and hard coded protocol tests.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "49f290903935612aadab3899a4aca884c1140348", "tree": "93e98e81a7d359c679ce081295d939be948c1c80", "parents": [ "51dbd490614e6228e9b2b198bd4f5f76ef961059" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Nov 19 16:03:44 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Wed Jan 23 05:24:10 2008 -0500" }, "message": "ahci: update PCS programming\n\nFor intel ones, ahci unconditionally OR\u0027d 0xf to PCS. This isn\u0027t\ncorrect for the following cases.\n\n* ich6/7m\u0027s which only implement P0 and P2 (0xf works fine tho)\n\n* ich8/9\u0027s which have six ports and needs 0x3f to enable all ports\n\nThis patch updates PCS programming such that...\n\n* port_map determined by ahci_save_initial_config() is OR\u0027d instead of 0xf\n\n* PCS is updated only if necessary (there are turned off enable bits)\n\nport_map is determined from PORTS_IMPL PCI register which is\nimplemented as write or write-once register. If the register isn\u0027t\nprogrammed, ahci automatically generates it from number of ports,\nwhich is good enough for PCS programming. ICH6/7M are probably the\nonly ones where non-contiguous enable bits are necessary \u0026\u0026 PORTS_IMPL\nisn\u0027t programmed properly but they\u0027re proven to work reliably with 0xf\nanyway.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "459ad68893a84fb0881e57919340b97edbbc3dc7", "tree": "04e7d419836214e3cb8a21f97a79697d0d9f0035", "parents": [ "c4f7792c021cda9bbf65d0bc2253a593fd652b91" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Fri Dec 07 12:46:23 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Dec 07 15:27:54 2007 -0500" }, "message": "libata: kill spurious NCQ completion detection\n\nSpurious NCQ completion detection implemented in ahci was incorrect.\nOn AHCI receving and processing FISes and raising interrupts are not\ninterlocked and spurious interrupts are expected.\n\nFor example, if an interrupt occurs while interrupt handler is running\nand the running interrupt handler handles the event the new IRQ\nindicated, after IRQ handler finishes, it will be executed again\nbecause IRQ pending bit is set by the new interrupt but there won\u0027t be\nanything to process.\n\nPlease read the following message for more information.\n\n http://article.gmane.org/gmane.linux.ide/26012\n\nThis patch...\n\n* Removes all spurious IRQ whining from ahci. Spurious NCQ completion\n detection was completely wrong. Spurious D2H Register FIS taught us\n that some early drives send spurious D2H Register FIS with I bit set\n while NCQ commands are in progress but none of recent drives does\n that and even the ones which show such behavior can do NCQ fine.\n\n* Kills all NCQ blacklist entries which were added because of spurious\n NCQ completions. I tracked down each commit and verified all\n removed ones are actually added because of spurious completions.\n\n WD740ADFD-00NLR1 wasn\u0027t deleted but moved upward because the drive\n not only had spurious NCQ completions but also is slow on sequential\n data transfers if NCQ is enabled.\n\n Maxtor 7V300F0 was added by 0e3dbc01d53940fe10e5a5cfec15ede3e929c918\n from Alan Cox. I can only find evidences that the drive only had\n troubles with spuruious completions by searching the mailing list.\n This entry needs to be verified and removed if it doesn\u0027t have other\n NCQ related problems.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nCc: Alan Cox \u003calan@lxorguk.ukuu.org.uk\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "c4f7792c021cda9bbf65d0bc2253a593fd652b91", "tree": "e0c727ba1bc934a8cbc58515c5b33e16eecde8a2", "parents": [ "d1aa690a7d1afa673c3383bfcd6e96ddb350939a" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Thu Dec 06 15:09:43 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Dec 07 15:27:54 2007 -0500" }, "message": "ahci: don\u0027t attach if ICH6 is in combined mode\n\nICH6 R/Ms share PCI ID between piix and ahci modes and we\u0027ve been\nallowing ahci to attach regardless of how BIOS configured it.\nHowever, enabling AHCI mode when the controller is in combined mode\ncan result in unexpected behavior. Don\u0027t attach if the controller is\nin combined mode.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nCc: Bill Nottingham \u003cnotting@redhat.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "994056d7aa884c742f58e2f2c17305bb01bf14e7", "tree": "41db117f56760ffb89dba6ae505799cf6ba27430", "parents": [ "2c5ea0f2d8c7d4883dd0d8ec3c7e3f3640b4f814" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Thu Dec 06 15:02:48 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Dec 07 15:27:53 2007 -0500" }, "message": "ahci: fix engine reset failed message\n\nThere isn\u0027t much point in reporting -EOPNOTSUPP as failure. Also the\nmessage was missing newline.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "6ba8695870a5a2ebf6f3d1ee3ac1e4d96d667cf6", "tree": "f272a1a157b23036751314f0ce885080a8b17677", "parents": [ "306b30f74d37f289033c696285e07ce0158a5d7b" ], "author": { "name": "peerchen", "email": "peerchen@gmail.com", "time": "Mon Dec 03 22:20:37 2007 +0800" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Tue Dec 04 14:10:14 2007 -0500" }, "message": "ahci: add the Device IDs of MCP79 AHCI controller to ahci.c\n\nAdd the device IDs of legacy mode of MCP79 AHCI controller to ahci.c\n\nSigned-off-by: Peer Chen \u003cpeerchen@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "31556594f913fa81d008cecfe46d7211c919a853", "tree": "424db37711a0805aef50f6e76b8686eb36ab5147", "parents": [ "ca77329fb713b7fea6a307068e0dd0248e7aa640" ], "author": { "name": "Kristen Carlson Accardi", "email": "kristen.c.accardi@intel.com", "time": "Thu Oct 25 01:33:26 2007 -0400" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon Oct 29 11:00:35 2007 -0400" }, "message": "[libata] AHCI: add hw link power management support\n\nThis patch will set the correct bits to turn on Aggressive\nLink Power Management (ALPM) for the ahci driver. This\nwill cause the controller and disk to negotiate a lower\npower state for the link when there is no activity (see\nthe AHCI 1.x spec for details). This feature is mutually\nexclusive with Hot Plug, so when ALPM is enabled, Hot Plug\nis disabled. ALPM will be enabled by default, but it is\nsettable via the scsi host syfs interface. Possible\nsettings for this feature are:\n\nSetting Effect\n----------------------------------------------------------\nmin_power ALPM is enabled, and link set to enter\n lowest power state (SLUMBER) when idle\n Hot plug not allowed.\n\nmax_performance ALPM is disabled, Hot Plug is allowed\n\nmedium_power ALPM is enabled, and link set to enter\n second lowest power state (PARTIAL) when\n idle. Hot plug not allowed.\n\nSigned-off-by: Kristen Carlson Accardi \u003ckristen.c.accardi@intel.com\u003e\nSigned-off-by: Jeff Garzik \u003cjgarzik@redhat.com\u003e\n" }, { "commit": "ab6fc95f609b372a19e18ea689986846ab1ba29c", "tree": "596c0139d5054bfe31b3c3ee36bcc8e6c50e8f9f", "parents": [ "360737a982b1ae09e1659e0bb27085c03f02f404" ], "author": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon Oct 29 10:43:55 2007 -0400" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon Oct 29 10:43:55 2007 -0400" }, "message": "[libata] AHCI: fix newly introduced host-reset bug\n\nThe recent fix to host reset introduced a problem, whereby AHCI-enable\nbit would be cleared upon reset, if it was not asserted prior to reset.\n\nUnconditionally enable AHCI-enable bit.\n\nSigned-off-by: Jeff Garzik \u003cjgarzik@redhat.com\u003e\n" }, { "commit": "88ff6eafbb2a1c55f0f0e2e16d72e7b10d8ae8a5", "tree": "ad6ab294a4f725540bfa24b7a451273b99fa71c1", "parents": [ "054a5fbaceb2eb3a31ea843c1cf0b8e10b91478c" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Tue Oct 16 14:21:24 2007 -0700" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon Oct 29 06:15:27 2007 -0400" }, "message": "libata: implement ata_wait_after_reset()\n\nOn certain device/controller combination, 0xff status is asserted\nafter reset and doesn\u0027t get cleared during 150ms post-reset wait. As\n0xff status is interpreted as no device (for good reasons), this can\nlead to misdetection on such cases.\n\nThis patch implements ata_wait_after_reset() which replaces the 150ms\nsleep and waits upto ATA_TMOUT_FF_WAIT if status is 0xff.\nATA_TMOUT_FF_WAIT is currently 800ms which is enough for\nHHD424020F7SV00 to get detected but not enough for Quantum GoVault\ndrive which is known to take upto 2s.\n\nWithout parallel probing, spending 2s on 0xff port would incur too\nmuch delay on ata_piix\u0027s which use 0xff to indicate empty port and\ndoesn\u0027t have SCR register, so GoVault needs to wait till parallel\nprobing.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "edc93052844c2032b2ec5910ace516da9078714d", "tree": "f99c1f1c529cdcbf93f12bf79583b287657abd49", "parents": [ "c15fcafe1c42daff212d78d4ce9619a52a74379f" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Thu Oct 25 14:59:16 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Thu Oct 25 02:06:59 2007 -0400" }, "message": "ahci: ahci: implement workaround for ASUS P5W-DH Deluxe ahci_broken_hardreset(), take #2\n\nP5W-DH Deluxe has ICH9 which doesn\u0027t have PMP support but SIMG 4726\nhardwired to the second port of AHCI controller at PCI device 1f.2.\nThe 4726 doesn\u0027t work as PMP but as a storage processor which can do\nhardware RAID on downstream ports.\n\nWhen no device is attached to the downstream port of the 4726, pseudo\nATA device for configuration appears. Unfortunately, ATA emulation on\nthe device is very lousy and causes long hang during boot.\n\nThis patch implements workaround for the board. If the mainboard is\nP5W-DH Deluxe (matched using DMI), only hardreset is used on the\nsecond port of AHCI controller @ 1f.2 and the hardreset doesn\u0027t depend\non receiving the first FIS and just proceed to IDENTIFY.\n\nThis workaround fixes bugzilla #8923.\n\n http://bugzilla.kernel.org/show_bug.cgi?id\u003d8923\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "2dcb407e61458ded17503d6bd12b8c064965368b", "tree": "6044e032197b84f9943a385b0c9dbb6656c3f97f", "parents": [ "01e7ae8c13bb06a2ce622ebace33bb7e28ef596c" ], "author": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 19 06:42:56 2007 -0400" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Tue Oct 23 20:59:42 2007 -0400" }, "message": "[libata] checkpatch-inspired cleanups\n\nTackle the relatively sane complaints of checkpatch --file.\n\nThe vast majority is indentation and whitespace changes, the rest are\n\n* #include fixes\n* printk KERN_xxx prefix addition\n* BSS/initializer cleanups\n\nSigned-off-by: Jeff Garzik \u003cjgarzik@redhat.com\u003e\n" }, { "commit": "3a4fa0a25da81600ea0bcd75692ae8ca6050d165", "tree": "a4de1662e645c029cf3cf58f0646cbb1959861dc", "parents": [ "18735dd8d2d37031b97f9e9e106acbaed01eb896" ], "author": { "name": "Robert P. J. Day", "email": "rpjday@mindspring.com", "time": "Fri Oct 19 23:10:43 2007 +0200" }, "committer": { "name": "Adrian Bunk", "email": "bunk@kernel.org", "time": "Fri Oct 19 23:10:43 2007 +0200" }, "message": "Fix misspellings of \"system\", \"controller\", \"interrupt\" and \"necessary\".\n\nFix the various misspellings of \"system\", controller\", \"interrupt\" and\n\"[un]necessary\".\n\nSigned-off-by: Robert P. J. Day \u003crpjday@mindspring.com\u003e\nSigned-off-by: Adrian Bunk \u003cbunk@kernel.org\u003e\n" }, { "commit": "b06ce3e51e3df4394a584c234f11240b1c6f8d5b", "tree": "6a6f5a1cccdc2972b236d376afeba4fd296d5400", "parents": [ "afaa5c373d2c49ee4865847031b82f1377f609d0" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Tue Oct 09 15:06:48 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:47 2007 -0400" }, "message": "libata: use ata_exec_internal() for PMP register access\n\nPMP registers used to be accessed with dedicated accessors -\u003epmp_read\nand -\u003epmp_write. During reset, those callbacks are called with the\nport frozen so they should be able to run without depending on\ninterrupt delivery. To achieve this, they were implemented polling.\n\nHowever, as resetting the host port makes the PMP to isolate fan-out\nports until SError.X is cleared, resetting fan-out ports while port is\nfrozen doesn\u0027t buy much additional safety.\n\nThis patch updates libata PMP support such that PMP registers are\naccessed using regular ata_exec_internal() mechanism and kills\n-\u003epmp_read/write() callbacks. The following changes are made.\n\n* PMP access helpers - sata_pmp_read_init_tf(), sata_pmp_read_val(),\n sata_pmp_write_init_tf() are folded into sata_pmp_read/write() which\n are now standalone PMP register access functions.\n\n* sata_pmp_read/write() returns err_mask instead of rc. This is\n consistent with other functions which issue internal commands and\n allows more detailed error reporting.\n\n* ahci interrupt handler is modified to ignore BAD_PMP and\n spurious/illegal completion IRQs while reset is in progress. These\n conditions are expected during reset.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "5f226c6bf78edab023ed1ea679531731d9df92a6", "tree": "01e0dff1224476aa52c240ee958ec7948bb85cc6", "parents": [ "1c954a4d9a9e351fa3509533fd8dd5f3821206cd" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Tue Oct 09 15:02:23 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:47 2007 -0400" }, "message": "ahci: fix notification handling\n\nAsynchronous notification on ICH9 didn\u0027t work because it didn\u0027t write\nAN FIS into the RX area - it only updates SNotification. Also,\nsnooping SDB_FIS RX area is racy against further SDB FIS receptions.\nLet sata_async_notification() determine using SNTF if it\u0027s available\nand snoop RX area iff SNTF isn\u0027t available\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nCc: Kristen Carlson Accardi \u003ckristen.c.accardi@intel.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "1c954a4d9a9e351fa3509533fd8dd5f3821206cd", "tree": "edc1571ab692de818543b9c5ddbd80e6bbbfca29", "parents": [ "75da6d2b8f518bec40546bc0b0696a2cebecf6cc" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Tue Oct 09 15:01:37 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:47 2007 -0400" }, "message": "ahci: clean up PORT_IRQ_BAD_PMP enabling\n\nNow that we have pp-\u003eintr_mask, move PORT_IRQ_BAD_PMP enabling to\nahci_pmp_attach/detach() where it belongs.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "75da6d2b8f518bec40546bc0b0696a2cebecf6cc", "tree": "2ee776da78cfc3dd9a42ebcfdc7864248982159f", "parents": [ "9073868376ed5fa1f247327ccb2e6f766d5b7eed" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Tue Oct 09 14:59:50 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:46 2007 -0400" }, "message": "ahci: kill leftover from enabling NCQ over PMP\n\nahci had problems with NCQ over PMP and NCQ used to be disabled while\nPMP was attached. After fixing the problem, the temporary NCQ\ndisabling code wasn\u0027t removed completely. Kill the remaining piece.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "7100819f5f9b99eb7c7dd5597f293388a405bf7b", "tree": "3a386aab745c01976318ada8559db7f1cb5b76d4", "parents": [ "1333e19434da116bc832e1b8925359d1565fedc9" ], "author": { "name": "Peer Chen", "email": "peerchen@gmail.com", "time": "Mon Sep 24 10:16:25 2007 +0800" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:45 2007 -0400" }, "message": "ahci: Add MCP79 support to AHCI driver\n\nSigned-off-by: Peer Chen \u003cpeerchen@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "6949b9148d3656afc13a2ccc06d13c071ec71bdc", "tree": "fc8021205536a67e7701ad413767a412449e51f7", "parents": [ "417a1a6d3d7abad4c5288135f640e6e38e7a65c5" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Sun Sep 23 13:19:55 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:44 2007 -0400" }, "message": "ahci: implement AHCI_HFLAG_NO_PMP\n\nOf course some controllers lie about PMP support. Black list them.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "417a1a6d3d7abad4c5288135f640e6e38e7a65c5", "tree": "87207680dbfb4b06f6267a49fbea68a880fba894", "parents": [ "7d50b60b5e38f910ad69f0187af00f5d6a8970d4" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Sun Sep 23 13:19:55 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:44 2007 -0400" }, "message": "ahci: move host flags over to pi.private_data\n\nPrivate pi.flags area is full and we need more private flags. Move\nhost private flags over to pi.private_data. During initialization,\nthese flags are copied to hpriv-\u003eflags.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "7d50b60b5e38f910ad69f0187af00f5d6a8970d4", "tree": "627c57902e588ad6e7f51a2df9f2b8f091e014c0", "parents": [ "238180343eff95697ed71eea137cf61ba3cea6ad" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Sun Sep 23 13:19:54 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:44 2007 -0400" }, "message": "ahci: implement PMP support\n\nImplement AHCI PMP support. ahci only supports command based\nswitching. Also, for some reason, NCQ over PMP doesn\u0027t work now.\nOther than that, everything works.\n\nTested on ICH9R, JMB360/363 + SIMG3726, 4726 and 5744.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nCc: Forrest Zhao \u003cforrest.zhao@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "3cc3eb1148e4b2dfabf7a1dcf36fd8be1331ca95", "tree": "5f987f613eb8dae6c170f97fe9acb47379902a32", "parents": [ "b90fe23bd51c6b1c298159591c833bdd24f55002" ], "author": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Wed Sep 26 00:02:41 2007 -0400" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:42 2007 -0400" }, "message": "[libata] AHCI: enable AHCI mode, before using AHCI reset\n\nAHCI spec says host-reset bit may only be set when the ahci-enable bit\nis also set.\n\nNoticed by Peer Chen \u003cpeerchen@gmail.com\u003e\n\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "7d77b247088fb360aa74bfdd9e19bce1e1987668", "tree": "add1b03309dd6fa82eb0f47e1a88766695f38f28", "parents": [ "e31e8531d668c9c4dc7883054788f89805188003" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Sun Sep 23 13:14:13 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:42 2007 -0400" }, "message": "libata-pmp-prep: implement sata_async_notification()\n\nAN serves multiple purposes. For ATAPI, it\u0027s used for media change\nnotification. For PMP, for downstream PHY status change notification.\nImplement sata_async_notification() which demultiplexes AN.\n\nTo avoid unnecessary port events, ATAPI AN is not enabled if PMP is\nattached but SNTF is not available.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nCc: Kriten Carlson Accardi \u003ckristen.c.accardi@intel.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "31cc23b34913bc173680bdc87af79e551bf8cc0d", "tree": "ec64421ead9259174f0de8b22c36449ece6d69a4", "parents": [ "fb7fd61454c8681cd2621051a710b78a00369203" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Sun Sep 23 13:14:12 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:41 2007 -0400" }, "message": "libata-pmp-prep: implement ops-\u003eqc_defer()\n\nControllers which support PMP have various restrictions on which\ncombinations of commands are allowed to what number of devices\nconcurrently. This patch implements ops-\u003eqc_defer() which determines\nwhether a qc can be issued at the moment or should be deferred.\n\nIf the function returns ATA_DEFER_LINK, the qc will be deferred until\na qc completes on the link. If ATA_DEFER_PORT, until a qc completes\non any link. The defer conditions are advisory and in general\nATA_DEFER_LINK can be considered as lower priority deferring than\nATA_DEFER_PORT.\n\nops-\u003eqc_defer() replaces fixed ata_scmd_need_defer(). For standard\nNCQ/non-NCQ exclusion, ata_std_qc_defer() is implemented. ahci and\nsata_sil24 are converted to use ata_std_qc_defer().\n\nops-\u003eqc_defer() is heavier than the original mechanism because full qc\nis prepped before determining to defer it, but various information is\nneeded to determine defer conditinos and fully translating a qc is the\nonly way to supply such information in generic manner.\n\nIMHO, this shouldn\u0027t cause any noticeable performance issues as\n\n* for most cases deferring occurs rarely (except for NCQ-aware\n cmd-switching PMP)\n* translation itself isn\u0027t that expensive\n* once deferred the command won\u0027t be repeated until another command\n completes which usually is a very long time cpu-wise.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "854c73a2f1c3bcc4aa88c25e208dc597e8efb795", "tree": "210569f3c4fa4f9413ceb0bc3fcf89648a9894b2", "parents": [ "c78968bb0f7714ceba1cdfa23714454fc98cefdf" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Sun Sep 23 13:14:11 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:40 2007 -0400" }, "message": "libata: misc updates for AN\n\nUpdate AN support in preparation of PMP support.\n\n* s/ata_id_has_AN/ata_id_has_atapi_AN/\n* add AN enabled reporting during configuration\n* add err_mask to AN configuration failure reporting\n* update LOCKING comment for ata_scsi_media_change_notify()\n* check whether ATA dev is attached to SCSI dev ata_scsi_media_change_notify()\n* set ATA_FLAG_AN in ahci and sata_sil24\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nCc: Kriten Carlson Accardi \u003ckristen.c.accardi@intel.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "d4155e6f13e931048036976d9fb47b5db53ee7a3", "tree": "cdcdc7161c2230cbf09339fc0979760bf90a02a5", "parents": [ "d7fbee050753e153622b5d41bc8bd1cb19cda9b9" ], "author": { "name": "Jason Gaston", "email": "jason.d.gaston@intel.com", "time": "Thu Sep 20 17:35:00 2007 -0400" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:39 2007 -0400" }, "message": "ahci: RAID mode SATA patch for Intel Tolapai\n\nSigned-off-by: Jason Gaston \u003cjason.d.gaston@intel.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "7a234aff3d83728fd83cf19df32d3df52566d2ac", "tree": "d991844bf7a7882eacd72a57a1465b25dc55e95d", "parents": [ "05027adccc09401a7e31d5ef51040dc75ab03c22" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Sep 03 12:44:57 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:39 2007 -0400" }, "message": "ahci: reimplement port_map handling\n\nReimplement port_map handling such that\n\n1. Non-zero PORTS_IMPL value is always examined and used if consistent\n with cap.n_ports.\n\n2. When PI and cat.n_ports are inconsistent, honor cap.n_ports and\n force port_map to be ((1 \u003c\u003c cap.n_ports) - 1).\n\n3. There were two separate places dealing with port_map. Unify them\n to one.\n\nAs all newer ahci chips seem to get PI correct and older ones usually\nhave zero PI. Controllers with holes in PI are very unlikely to screw\nup PI, so #2 makes more sense than following inconsistent PI.\n\nWithout this change, not setting ATA_FLAG_HONOR_PI when it\u0027s needed\nresults in weird detection failure. This changed logic should be able\nto handle all known cases correctly automatically.\n\nVerified on ICH6 (reports 0 PI), ICH8 (with holes in port_map), ICH9,\nJMB360 and JMB363.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "cbcdd87593a1d85c5c4b259945a3a09eee12814d", "tree": "ee03df963a12ec7f30f6c3a8742421daf2c34f50", "parents": [ "e923090ddd9fef1d4e06dc6c5295e29baced19f3" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Sat Aug 18 13:14:55 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:37 2007 -0400" }, "message": "libata: implement and use ata_port_desc() to report port configuration\n\nCurrently, port configuration reporting has the following problems.\n\n* iomapped address is reported instead of raw address\n* report contains irrelevant fields or lacks necessary fields for\n non-SFF controllers.\n* host-\u003eirq/irq2 are there just for reporting and hacky.\n\nThis patch implements and uses ata_port_desc() and\nata_port_pbar_desc(). ata_port_desc() is almost identical to\nata_ehi_push_desc() except that it takes @ap instead of @ehi, has no\nlocking requirement, can only be used during host initialization and \"\n\" is used as separator instead of \", \". ata_port_pbar_desc() is a\nhelper to ease reporting of a PCI BAR or an offsetted address into it.\n\nLLD pushes whatever description it wants using the above two\nfunctions. The accumulated description is printed on host\nregistration after \"[S/P]ATA max MAX_XFERMODE \".\n\nSFF init helpers and ata_host_activate() automatically add\ndescriptions for addresses and irq respectively, so only LLDs which\nisn\u0027t standard SFF need to add custom descriptions. In many cases,\nsuch controllers need to report different things anyway.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "ac8869d56d95a8c74403e6f7a47d74fcfcc1b988", "tree": "2f812aff4c6e559f3c093f9933960d09631375c8", "parents": [ "7d73a363dea186a864f6295bbe842da8044d42cd" ], "author": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Thu Aug 16 03:17:03 2007 -0400" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:35 2007 -0400" }, "message": "[libata] Remove -\u003eport_disable() hook\n\nIt was always set to ata_port_disable(). Removed the hook, and replaced\nthe very few ap-\u003eops-\u003eport_disable() callsites with direct calls to\nata_port_disable().\n\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "6d32d30f55020d766388df7515f771f68c973033", "tree": "ec0efe48460b5b3f177fed2698ccd04b7964359b", "parents": [ "cb94c1cf5a6beffbd8935eb91227df0dd1987644" ], "author": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Wed Aug 15 05:38:46 2007 -0400" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:34 2007 -0400" }, "message": "[libata] Remove -\u003eirq_ack() hook, and ata_dummy_irq_on()\n\n* -\u003eirq_ack() is redundant to what the irq handler already\n performs... chk-status + irq-clear. Furthermore, it is only\n called in one place, when screaming-irq-debugging is enabled,\n so we don\u0027t want to bother with a hook just for that.\n\n* ata_dummy_irq_on() is only ever used in drivers that have\n no callpath reaching -\u003eirq_on(). Remove .irq_on hook from\n those drivers, and the now-unused ata_dummy_irq_on()\n\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "a738492501eaf6e266acc53a064552b3fcc706b2", "tree": "8d24a2504530bf175279c294cfcac669ade575c8", "parents": [ "2f2949680ad89d606db838340b17c30216c0bb0f" ], "author": { "name": "Kristen Carlson Accardi", "email": "kristen.c.accardi@intel.com", "time": "Thu Aug 09 14:23:41 2007 -0700" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:33 2007 -0400" }, "message": "ahci: Store interrupt value\n\nUse a stored value for which interrupts to enable. Changing this allows\nus to selectively turn off certain interrupts later and have them\nstay off.\n\nSigned-off-by: Kristen Carlson Accardi \u003ckristen.c.accardi@intel.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "2f2949680ad89d606db838340b17c30216c0bb0f", "tree": "25d7918c7b846d151776bbdf6a111a1d241d6b05", "parents": [ "9f45cbd3f0fc597530aaf85cad7fe52cd63f1fd8" ], "author": { "name": "Kristen Carlson Accardi", "email": "kristen.c.accardi@intel.com", "time": "Wed Aug 15 04:11:25 2007 -0400" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:33 2007 -0400" }, "message": "[libata] ahci: send event when AN received\n\nWhen we get an SDB FIS with the \u0027N\u0027 bit set, we should send\nan event to user space to indicate that there has been a\nmedia change. This will be done via the scsi device.\n\nSigned-off-by: Kristen Carlson Accardi \u003ckristen.c.accardi@intel.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "0c88758b5a6325428aaadab619886242db20ceae", "tree": "bf84abbce984fa45c4ce927b65695f30a8ea3a43", "parents": [ "0260731f0187840e272bfa10d3ba0f3e417976f5" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Aug 06 18:36:23 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:31 2007 -0400" }, "message": "libata-link: make two port flags HRST_TO_RESUME and SKIP_D2H_BSY link flags\n\nHRST_TO_RESUME and SKIP_D2H_BSY are link attributes. Move them to\nata_link-\u003eflags. This will allow host and PMP links to have different\nattributes. ata_port_info-\u003elink_flags is added and used by LLDs to\nspecify these flags during initialization.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "cc0680a580b5be81a1ca321b58f8e9b80b5c1052", "tree": "57454cdfdc9890f4e8d9f532e9cd240c7361951f", "parents": [ "955e57dfde4ff75e4d7329ac7a3d645b16015309" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Aug 06 18:36:23 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:31 2007 -0400" }, "message": "libata-link: linkify reset\n\nMake reset methods and related functions deal with ata_link instead of\nata_port.\n\n* ata_do_reset()\n* ata_eh_reset()\n* all prereset/reset/postreset methods and related functions\n\nThis patch introduces no behavior change.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "936fd7328657884d5a69a55666c74a55aa83ca27", "tree": "83a78a02d2c65ce835fe33882dfe5043d3240bff", "parents": [ "f58229f8060055b08b34008ea08f31de1e2f003c" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Aug 06 18:36:23 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:30 2007 -0400" }, "message": "libata-link: linkify PHY-related functions\n\nMake the following PHY-related functions to deal with ata_link instead\nof ata_port.\n\n* sata_print_link_status()\n* sata_down_spd_limit()\n* ata_set_sata_spd_limit() and friends\n* sata_link_debounce/resume()\n* sata_scr_valid/read/write/write_flush()\n* ata_link_on/offline()\n\nThis patch introduces no behavior change.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "9af5c9c97dc9d599281778864c72b385f0c63341", "tree": "8359986bd42c4a9a5b1993078aa9ee4c7971ac3d", "parents": [ "640fdb504941fa2b9f6f274716fc9f97f2bf6bff" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Aug 06 18:36:22 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Oct 12 14:55:30 2007 -0400" }, "message": "libata-link: introduce ata_link\n\nIntroduce ata_link. It abstracts PHY and sits between ata_port and\nata_device. This new level of abstraction is necessary to support\nSATA Port Multiplier, which basically adds a bunch of links (PHYs) to\na ATA host port. Fields related to command execution, spd_limit and\nEH are per-link and thus moved to ata_link.\n\nThis patch only defines the host link. Multiple link handling will be\nadded later. Also, a lot of ap-\u003elink derefences are added but many of\nthem will be removed as each part is converted to deal directly with\nata_link instead of ata_port.\n\nThis patch introduces no behavior change.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nCc: James Bottomley \u003cJames.Bottomley@SteelEye.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "c69c0892d8dd68b01a9fced5cab8527f0698c15e", "tree": "dc8711b7893651d7157e64333f196841bf0bb89a", "parents": [ "e1cc9de8361f267101402a1181cff4d3d3225a6d" ], "author": { "name": "henry su", "email": "henry.su.ati@gmail.com", "time": "Thu Sep 20 16:07:33 2007 -0400" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Thu Sep 20 16:07:33 2007 -0400" }, "message": "[libata] ahci: add ATI SB800 PCI IDs\n\nATI/AMD SB800 shares some device IDs with SB700,\nand SB800 adds two more device IDs:0x4394,0x4395.\n\nSigned-off-by: henry su \u003chenry.su.ati@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "badc2341579511a247f5993865aa68379e283c5c", "tree": "bcdd50d27969b247d2cb459a3cfdbb686ef2e34d", "parents": [ "203ef6c456ad70e660cca67921d3d872b13aa516" ], "author": { "name": "su henry", "email": "henry.su.ati@gmail.com", "time": "Fri Jul 20 08:07:46 2007 -0400" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Jul 20 08:07:46 2007 -0400" }, "message": "The SATA controller device ID is different according to\nthe onchip SATA type set in the system BIOS:\nDevice Device ID\nSATA in IDE mode 0x4390\nSATA in AHCI mode 0x4391\nSATA in non-raid5 driver 0x4392\nSATA in raid5 driver 0x4393\n\nAlthough the device ID is different, they use the same AHCI driver\n.The attached file is the patch for adding these device\nIDs for ATI SB700.\n\nSigned-off-by: henry.su.ati@gmail.com\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "203ef6c456ad70e660cca67921d3d872b13aa516", "tree": "5dfcc194492f9a1d561966042c858ba705ad6786", "parents": [ "274c1fde5c775a53331427d454745b9ecc5c783b" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Jul 16 14:29:40 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Jul 20 08:02:11 2007 -0400" }, "message": "ahci: implement SCR_NOTIFICATION r/w\n\nMake ahci_scr_read/write() handle SCR_NOTIFICATION if the controller\nsupports it. Also, print \"sntf\" in the cap line if supported.\n\nWhile at it, convert eight space into a tab in ahci_print_info().\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "274c1fde5c775a53331427d454745b9ecc5c783b", "tree": "df39d94ac51195e25a04a7365ab88e2eb536d261", "parents": [ "da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9d" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Jul 16 14:29:40 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Jul 20 08:02:11 2007 -0400" }, "message": "ahci: make NO_NCQ handling more consistent\n\nahci_save_initial_config() is responsible for reading, screening the\nhost CAP register and storing the modified result into hpriv-\u003ecap for\nthe rest of the driver. Move ATA_FLAG_NO_NCQ handling into\nahci_save_initial_config(). It\u0027s more consistent this way and the\nrest of the driver can always refer to hpriv-\u003ecap to determine\nconfigured capability.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "da3dbb17a0e9a9ec7f5aed95f1fddadb790edc9d", "tree": "289239e1eb60168321e905c545aa2e2f3a2b5475", "parents": [ "5335b729064e03319cd2d5219770451dbb1d7f67" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Jul 16 14:29:40 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Jul 20 08:02:11 2007 -0400" }, "message": "libata: make -\u003escr_read/write callbacks return error code\n\nConvert -\u003escr_read/write callbacks to return error code to better\nindicate failure. This will help handling of SCR_NOTIFICATION.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "b64bbc39f2122a2276578e40144af69ef01decd4", "tree": "bd760da68bc785490ecd31060d892eeb7123782d", "parents": [ "975530e8a33fdeb1ad80d82fde11d56bf9ed2760" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Jul 16 14:29:39 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Jul 20 08:02:11 2007 -0400" }, "message": "libata: improve EH report formatting\n\nRequiring LLDs to format multiple error description messages properly\ndoesn\u0027t work too well. Help LLDs a bit by making ata_ehi_push_desc()\ninsert \", \" on each invocation. __ata_ehi_push_desc() is the raw\nversion without the automatic separator.\n\nWhile at it, make ehi_desc interface proper functions instead of\nmacros.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "a9cf5e858100b2f82ad61028c26a1a3de11c4839", "tree": "3edaf851bc132d6b8e7ea6cd09eb7ca80156bde0", "parents": [ "91c4a2e09267b0ddc8e59d121e3748cd18675739" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Jul 16 14:29:39 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Jul 20 08:02:10 2007 -0400" }, "message": "ahci: separate out ahci_do_softreset()\n\nSeparate out ahci_do_softreset() which takes @pmp as its last\nargument. This will be used to implement ahci_pmp_softreset().\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "91c4a2e09267b0ddc8e59d121e3748cd18675739", "tree": "6f4d6adfddaf88f60fd2c1c29ce1785fda52cc52", "parents": [ "d2e75dfffbe9e86e1d646264792ac9bcd2cc4267" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Jul 16 14:29:39 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Jul 20 08:02:10 2007 -0400" }, "message": "ahci: separate out ahci_exec_polled_cmd()\n\nSeparate out ahci_exec_polled_cmd() from ahci_softreset(). This will\nbe used to implement ahci_pmp_read/write(). ahci_exec_polled_cmd()\nperforms reset_engine before returning if the command fails (times\nout). This is to improve robustness.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "d2e75dfffbe9e86e1d646264792ac9bcd2cc4267", "tree": "be742ccdbefc5ddb0db031d9fd95717d7641b950", "parents": [ "2cbb79ebbd4be07041368da5379a64f89f8ad518" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Jul 16 14:29:39 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Jul 20 08:02:10 2007 -0400" }, "message": "ahci: separate out ahci_kick_engine()\n\nSeparate out stop_engine - CLO - start_engine sequence from\nahci_softreset() and ahci_clo() into ahci_reset_engine() and use it in\nahci_softreset() and ahci_post_internal_cmd(). The function will also\nbe used to prepare for and clean up after PMP register access\ncommands.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "2cbb79ebbd4be07041368da5379a64f89f8ad518", "tree": "239d63fca15c2c3abd9f9ef5130a43f6289d0ad1", "parents": [ "9977126c4b65c1396b665f7a0eeb8c7dede336f9" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Jul 16 14:29:38 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Jul 20 08:02:10 2007 -0400" }, "message": "ahci: use deadline instead of fixed timeout for 1st FIS for SRST\n\nUse deadline instead of fixed timeout for 1st FIS for SRST to improve\nrobustness of SRST.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "9977126c4b65c1396b665f7a0eeb8c7dede336f9", "tree": "91901f1356a57ba311bc5c95c4825504642f7d04", "parents": [ "fe36cb53cfd82f3c0796a0826e1c9caf198c8f97" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Jul 16 14:29:38 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Jul 20 08:02:10 2007 -0400" }, "message": "libata: add @is_cmd to ata_tf_to_fis()\n\nAdd @is_cmd to ata_tf_to_fis(). This controls bit 7 of the second\nbyte which tells the device whether this H2D FIS is for a command or\nnot. This cleans up ahci a bit and will be used by PMP.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "028a2596336b19a7e3713cfa9fe04d0d32e95876", "tree": "879f9f0127a7caff7857f38593a93d344b73763e", "parents": [ "3fb6589ceaf06d9c65bdf2382249d818771e913b" ], "author": { "name": "Alexey Dobriyan", "email": "adobriyan@gmail.com", "time": "Tue Jul 17 23:48:48 2007 +0400" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Jul 20 07:16:24 2007 -0400" }, "message": "ahci.c: fix CONFIG_PM\u003dn compilation\n\nCommit df69c9c5438b4e396a64d42608b2a6c48a3e7475 moved only prototype of\nout of CONFIG_PM. Move function out as well. Box seems to boot fine.\n\nSigned-off-by: Alexey Dobriyan \u003cadobriyan@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "cd70c26617f4686355263be4533ce8030242740e", "tree": "20313e5c0a996b5c95ce46ba8ed796271316ef28", "parents": [ "469248abf00dfa813356b372ffe153b85f27f4bf" ], "author": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Sun Jul 08 02:29:42 2007 -0400" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon Jul 09 12:17:35 2007 -0400" }, "message": "[libata] AHCI: Add support for Marvell AHCI-like chips (initially 6145)\n\nAdd support for the SATA portion of Marvell\u0027s AHCI-compatible chips.\nThe PATA port capability, also available via AHCI, is disabled until\nsupport is completed.\n\nNCQ and PCI MSI are disabled by default. Marvell says \"we use NCQ\" in\ntheir drivers but \"we do not use PCI MSI.\" Theoretically that implies\nwe need to fix ahci.c to work with Marvell NCQ, but one wonders why\nMarvell NCQ is any different from other AHCI chips.\n\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "469248abf00dfa813356b372ffe153b85f27f4bf", "tree": "61d81524195c35195abc68d8cc437c93bd5036bc", "parents": [ "d26fc9551a15fdad0d5de8376a78816b8af44f00" ], "author": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Sun Jul 08 01:13:16 2007 -0400" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon Jul 09 12:17:35 2007 -0400" }, "message": "[libata] Clean up driver udma_mask initializers\n\n* Use ATA_UDMA*\n* Remove FIXME notations that once served to remind us to verify\n that these were indeed the correct UDMA masks. They are.\n\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "dab632e8c483532bd84e1f3401c72612e39a7c40", "tree": "43d70da1e30389457ac3cfb4f7ded5e5429fb4cc", "parents": [ "ab2181cf390902f0371f30e4ebeb407b4aaa7314" ], "author": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon May 28 08:33:01 2007 -0400" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon Jul 09 12:17:34 2007 -0400" }, "message": "[libata] ahci: minor internal cleanups\n\nMinor cleanups, in preparation for merging Marvell PATA AHCI support in\nthe future.\n\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "df69c9c5438b4e396a64d42608b2a6c48a3e7475", "tree": "a96728fe0d1f2714b574c8319344c584895963d0", "parents": [ "2bcd866be55f8fe259ccac8eef2b8a7f7721b1d5" ], "author": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Sat May 26 20:46:51 2007 -0400" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon Jul 09 12:17:33 2007 -0400" }, "message": "[libata] ahci: minor internal cleanups\n\nFunction renaming and factorization.\n\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "2bcd866be55f8fe259ccac8eef2b8a7f7721b1d5", "tree": "de87ba6f172b49a9674bb13a73a24eb8634cd109", "parents": [ "79b0bde157e71071320e7a723c5a669cb2c822cf" ], "author": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon May 28 07:45:27 2007 -0400" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon Jul 09 12:17:33 2007 -0400" }, "message": "[libata] ahci: Factor out SATA port init into a separate function\n\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "be5d82183f1ebb022f923b008acf3b760d3a571d", "tree": "1520884587829c909d618695d6702e7d602447b3", "parents": [ "a16abc0b5ff3ef655e40cb5e6671d57f5dde513d" ], "author": { "name": "Jens Axboe", "email": "jens.axboe@oracle.com", "time": "Tue May 22 09:45:39 2007 +0200" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon Jul 09 12:17:32 2007 -0400" }, "message": "use_clustering (sht) bit set to 0 in AHCI ?\n\nahci: enable sg segment clustering\n\nThe specification states that ahci supports segments up to 4MiB in size,\nso enable clustering.\n\nSigned-off-by: Jens Axboe \u003cjens.axboe@oracle.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "a3d2cc5e742f82a87fdf9e2b730f41ff381c0a73", "tree": "96dd7ab5c98198e634b9323dc4d903c9bf8548eb", "parents": [ "3fae450c68d06b8890e1530bdd0910e938e7251d" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Tue Jun 19 18:52:56 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Wed Jun 20 19:56:21 2007 -0400" }, "message": "ahci: fix PORTS_IMPL override\n\nIf PORTS_IMPL register is zero, ahci initialize it to full mask\ncorresponding to nr_ports in the CAP register. hpriv-\u003ecap, which is\ninitialized at the end of the function, is incorrectly used as value\nof CAP causing ahci to always override PORTS_IMPL to 0x1 if it\u0027s zero.\nFix it.\n\nThis fixes a bug where early ich6 ahci can only access the first port.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "0522b2869d89b095bf417c8cc6fa404842e91903", "tree": "f093ef64e435674cc562a6b1e26343689563ded1", "parents": [ "afe3cc51ba4be6b25b721c40f178ea4157751161" ], "author": { "name": "Peer Chen", "email": "peerchen@gmail.com", "time": "Thu Jun 07 18:05:12 2007 +0800" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Sat Jun 09 22:40:28 2007 -0400" }, "message": "ahci: Add MCP73/MCP77 support to AHCI driver\n\nAdd the MCP73/MCP77 support to ahci driver.\n\nSigned-off-by: Peer Chen \u003cpeerchen@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "8bc3fc470eb25af4d70c72485cbcb130cc657691", "tree": "b79e0068f46cca29a547786e5ee2cdc739386cca", "parents": [ "a617c09f6d646b60f31efc8afd9f81b752bf21b7" ], "author": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon May 21 20:26:38 2007 -0400" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon May 21 20:26:38 2007 -0400" }, "message": "libata: bump versions\n\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "c7a42156d99bcea7f8173ba7a6034bbaa2ecb77c", "tree": "7d84ead0d69602cc900e30355ec84132800dea93", "parents": [ "55b637c6a003a8c4850b41a2c2fd6942d8a7f530" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Fri May 18 16:23:19 2007 +0200" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon May 21 20:00:25 2007 -0400" }, "message": "ahci: disable 64bit dma on sb600\n\nSB600 claims it can do 64bit DMA but it can\u0027t. Disable it.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "3cadbcc09891b8544203f211dac13f9cc4e6832a", "tree": "ac85dba0648f6e2be0d057b9afca926d97e24828", "parents": [ "6ddcd3b0201a7ad72294347636d2b4028ddbd95d" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Tue May 15 03:28:15 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Wed May 16 01:18:31 2007 -0400" }, "message": "libata-acpi: add ATA_FLAG_ACPI_SATA port flag\n\nWhether a controller needs IDE or SATA ACPI hierarchy is determined by\nthe programming interface of the controller not by whether the\ncontroller is SATA or PATA, or it supports slave device or not. This\npatch adds ATA_FLAG_ACPI_SATA port flags which tells libata-acpi that\nthe port needs SATA ACPI nodes, and sets the flag for ahci and\nsata_sil24.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "2bcfdde6767f2f07891d2753c25220012fe5e6d2", "tree": "9ca9b53583acbaae2bee14e95459c1fa04321596", "parents": [ "823777181b4c0200923dcb026efa5b37f55c0ecf" ], "author": { "name": "Henry Su", "email": "henry.su@amd.com", "time": "Thu May 10 22:48:51 2007 -0700" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri May 11 18:16:01 2007 -0400" }, "message": "add the ATI SB700 SATA controller device id to AHCI pci table\n\nAdd the device ID to AHCI pci table for ATI SB700 SATA controller, the\nsubsequent chipset of SB600.\n\nSigned-off-by: henry su\u003chenry.su@amd.com\u003e\nCc: Jeff Garzik \u003cjeff@garzik.org\u003e\nCc: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "9666f4009c22f6520ac3fb8a19c9e32ab973e828", "tree": "eaac13cd5890af6298e5576a48c29891f0890bd1", "parents": [ "0a3fd051c7036ef71b58863f8e5da7c3dabd9d3f" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Fri May 04 21:27:47 2007 +0200" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri May 11 18:01:03 2007 -0400" }, "message": "libata: reimplement suspend/resume support using sdev-\u003emanage_start_stop\n\nReimplement suspend/resume support using sdev-\u003emanage_start_stop.\n\n* Device suspend/resume is now SCSI layer\u0027s responsibility and the\n code is simplified a lot.\n\n* DPM is dropped. This also simplifies code a lot. Suspend/resume\n status is port-wide now.\n\n* ata_scsi_device_suspend/resume() and ata_dev_ready() removed.\n\n* Resume now has to wait for disk to spin up before proceeding. I\n couldn\u0027t find easy way out as libata is in EH waiting for the\n disk to be ready and sd is waiting for EH to complete to issue\n START_STOP.\n\n* sdev-\u003emanage_start_stop is set to 1 in ata_scsi_slave_config().\n This fixes spindown on shutdown and suspend-to-disk.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "9b89391cc861b8a1105551909eb66c024fe18ab2", "tree": "f0783823927ea013c8d58c1041ad1e1d884eed9e", "parents": [ "d4b2bab4f26345ea1803feb23ea92fbe3f6b77bc" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Fri Feb 02 16:50:52 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Tue May 01 07:49:54 2007 -0400" }, "message": "libata: improve 0xff status handling\n\nFor PATA, 0xff status indicates empty port. For SATA, it depends on\nhow the controller emulates status register. On some controllers,\n0xff is used to represent broken link or certain stage during reset.\n\nlibata currently deals SATA the same. This hasn\u0027t caused any problem\nbecause problematic situations usually only occur after hotplug or\nother link disruption events and libata blindly waited for the device\nto spin up and settle after hotplug giving the link and device\nwhatever time to go through those stages.\n\nlibata is going to replace unconditional spinup wait with generic\ntimed sequence of resets, so not only getting 0xff handling right for\nSATA is, well, the right thing to do, it\u0027s much more important now.\n\nThis patch makes the following changes.\n\n* Make ata_bus_softreset() return -ENODEV if any of its wait fails\n due to 0xff status.\n\n* Fail soft/hardreset if status wait returns -ENODEV indicating 0xff\n status while SStatus says the link is online. e.g. Reset fails if\n status is 0xff after reset when SStatus reports the linke is online.\n If SCR registers are not available, everything is the same as\n before.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "d4b2bab4f26345ea1803feb23ea92fbe3f6b77bc", "tree": "30a9826351e597828de2b402f1c41b9fca94cf95", "parents": [ "dc87c3985e9b442c60994308a96f887579addc39" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Fri Feb 02 16:50:52 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Tue May 01 07:49:53 2007 -0400" }, "message": "libata: add deadline support to prereset and reset methods\n\nAdd @deadline to prereset and reset methods and make them honor it.\nata_wait_ready() which directly takes @deadline is implemented to be\nused as the wait function. This patch is in preparation for EH timing\nimprovements.\n\n* ata_wait_ready() never does busy sleep. It\u0027s only used from EH and\n no wait in EH is that urgent. This function also prints \u0027be\n patient\u0027 message automatically after 5 secs of waiting if more than\n 3 secs is remaining till deadline.\n\n* ata_bus_post_reset() now fails with error code if any of its wait\n fails. This is important because earlier reset tries will have\n shorter timeout than the spec requires. If a device fails to\n respond before the short timeout, reset should be retried with\n longer timeout rather than silently ignoring the device.\n\n There are three behavior differences.\n\n 1. Timeout is applied to both devices at once, not separately. This\n is more consistent with what the spec says.\n\n 2. When a device passes devchk but fails to become ready before\n deadline. Previouly, post_reset would just succeed and let\n device classification remove the device. New code fails the\n reset thus causing reset retry. After a few times, EH will give\n up disabling the port.\n\n 3. When slave device passes devchk but fails to become accessible\n (TF-wise) after reset. Original code disables dev1 after 30s\n timeout and continues as if the device doesn\u0027t exist, while the\n patched code fails reset. When this happens, new code fails\n reset on whole port rather than proceeding with only the primary\n device.\n\n If the failing device is suffering transient problems, new code\n retries reset which is a better behavior. If the failing device is\n actually broken, the net effect is identical to it, but not to the\n other device sharing the channel. In the previous code, reset would\n have succeeded after 30s thus detecting the working one. In the new\n code, reset fails and whole port gets disabled. IMO, it\u0027s a\n pathological case anyway (broken device sharing bus with working\n one) and doesn\u0027t really matter.\n\n* ata_bus_softreset() is changed to return error code from\n ata_bus_post_reset(). It used to return 0 unconditionally.\n\n* Spin up waiting is to be removed and not converted to honor\n deadline.\n\n* To be on the safe side, deadline is set to 40s for the time being.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "1188c0d83ca010c3799711e85e63dbde122e6a90", "tree": "dbb0705488eef68b0cce96af19ca4e6ff4aed87b", "parents": [ "4f701d1e9a796a3d6657e1129bee0566d7cda916" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Apr 23 02:41:05 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Sat Apr 28 14:51:33 2007 -0400" }, "message": "ahci: consolidate common port flags\n\nConsolidate common port flags into AHCI_FLAG_COMMON.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "4447d35156169cf136e829eb6b5cac2d6370f2d9", "tree": "20be4c582ea4ce1cce1b0f8dbea949a410a72e3c", "parents": [ "9a829ccfc833269bdb85751f5048288ab93678ac" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Tue Apr 17 23:44:08 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Sat Apr 28 14:16:06 2007 -0400" }, "message": "libata: convert the remaining SATA drivers to new init model\n\nConvert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,\nsata_sx4, sata_vsc and sata_inic162x to new init model.\n\nNow that host and ap are available during intialization, functions are\nconverted to take either host or ap instead of low level parameters\nwhich were inevitable for functions shared between init and other\npaths. This simplifies code quite a bit.\n\n* init_one()\u0027s now follow more consistent init order\n\n* ahci_setup_port() and ahci_host_init() collapsed into\n ahci_init_one() for init order consistency\n\n* sata_vsc uses port_info instead of setting fields manually\n\n* in sata_svw, k2_board_info converted to port_info (info is now in\n port flags). port number is honored now.\n\nTested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "bf33554290bb6a6b2bd8827076f89fb17fb19e3d", "tree": "7c6f2236daad79d2232c7ef309459ed4d02465bb", "parents": [ "03ec52dea0f3c615b1b502672c189f296842f7dd" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Wed Apr 11 17:27:14 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Sat Apr 28 14:16:02 2007 -0400" }, "message": "ahci: add PCI ID for new VIA chip\n\nAdd PCI ID for new VIA chip. Original patch is from Maarten Vanraes.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nCc: Maarten Vanraes \u003cmaarten.vanraes@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "c65ec1c25dc23123040efdc4ada46071431723e3", "tree": "7c5a6e3f1f8bf3a0a9f74520eb5c1806fba4c5c7", "parents": [ "a51d644af6eb0a93bc383e5f005faa445c87f335" ], "author": { "name": "Conke Hu", "email": "conke.hu@gmail.com", "time": "Wed Apr 11 18:23:14 2007 +0800" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Sat Apr 28 14:16:02 2007 -0400" }, "message": "ahci.c: remove non-existing SB600 raid id (re-send)\n\n SB600 RAID and SB600 SATA is the same controller and share the\nsame PCI ID 0x4380. There is no such PCI ID 0x4381.\n\n Signed-off-by: Conke Hu \u003cconke.hu@gmail.com\u003e\n ---------\n\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "a51d644af6eb0a93bc383e5f005faa445c87f335", "tree": "b1392796d9766e86e7a87d57dd0f7d62e0fa0dfa", "parents": [ "55a6adeea4077521b4bba1dfe674f5835157a00b" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Tue Mar 20 15:24:11 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Sat Apr 28 14:16:02 2007 -0400" }, "message": "libata: improve AC_ERR_DEV handling for -\u003epost_internal_cmd\n\n-\u003epost_internal_cmd is simplified EH for internal commands. Its\nprimary mission is to stop the controller such that no rogue memory\naccess or other activities occur after the internal command is\nreleased. It may provide error diagnostics by setting qc-\u003eerr_mask\nbut this hasn\u0027t been a requirement.\n\nTo ignore SETXFER failure for CFA devices, libata needs to know\nwhether a command was failed by the device or for any other reason.\nie. internal command needs to get AC_ERR_DEV right.\n\nThis patch makes the following changes to AC_ERR_DEV handling and\n-\u003epost_internal_cmd semantics to accomodate this need and simplify\ncallback implementation.\n\n1. As long as the correct bits in the result TF registers are set,\n there is no need to set AC_ERR_DEV explicitly. libata EH core\n takes care of that for both normal and internal commands.\n\n2. The only requirement for -\u003epost_internal_cmd() is to put the\n controller into quiescent state. It needs not to set any err_mask.\n\n3. ata_exec_internal_sg() performs minimal error analysis such that\n AC_ERR_DEV is automatically set as long as result_tf is filled\n correctly.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "17199b187b5d9a22f2ec835c9fdb38302501b918", "tree": "ae381abed721e382c2bb031a89acd8098e4aeb15", "parents": [ "d447df140d0f07a02bd221cb42eb0b61bce16042" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Sun Mar 18 22:26:53 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Sat Apr 28 14:16:01 2007 -0400" }, "message": "ahci: move port_map handling to ahci_save_initial_config()\n\nMove cross checking between port_map and cap.n_ports into\nahci_save_initial_config(). After save_initial_config is done,\nhpriv-\u003eport_map is always setup properly.\n\nTested on JMB363, ICH7 and ICH8 (with dummy ports).\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "d447df140d0f07a02bd221cb42eb0b61bce16042", "tree": "7ce228513178cdce89db5d93cb7bd4c04be1a771", "parents": [ "ce2d3abc292c1eecd9ddc6f03391a0a46c6561dc" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Sun Mar 18 22:15:33 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Sat Apr 28 14:16:01 2007 -0400" }, "message": "ahci: implement ata_save/restore_initial_config()\n\nThere are several registers which describe how the controller is\nconfigured. These registers are sometimes implemented as r/w\nregisters which are configured by firmware and get cleared on\ncontroller reset or after suspend/resume cycle. ahci saved and\nrestored those values inside ahci_reset_controller() which is a bit\nmessy and doesn\u0027t work over suspend/resume cycle.\n\nThis patch implements ahci_save/restore_initial_config(). The save\nfunction is called during driver initialization and saves cap and\nport_map to hpriv. The restore function is called after the\ncontroller is reset to restore the initial values.\n\nSometimes the initial firmware values are inconsistent and need to be\nfixed up. This is handled by ahci_save_initial_config(). For this,\nthere are two versions of saved registers. One to write back to the\nhardware register, the other to use during driver operation. This is\nnecessary to keep ahci\u0027s behavior unchanged (write back fixed up\nport_map while keeping cap as-is).\n\nThis patch makes ahci save the register values once before the first\ncontroller reset, not after it\u0027s been reset. Also, the same stored\nvalues are used written back after each reset, so the register values\nare properly recovered after suspend/resume cycle.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "55a61604cd1354e1783364e1c901034f2f474b7d", "tree": "28c9a083fa426403f8a6fe852543ce04a6482618", "parents": [ "d7d0dad62a641c156386288a747c1a2f6bb2e42d" ], "author": { "name": "Conke Hu", "email": "conke.hu@gmail.com", "time": "Tue Mar 27 18:33:05 2007 +0800" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Wed Mar 28 02:04:27 2007 -0400" }, "message": "ahci.c: walkaround for SB600 SATA internal error issue\n\n There is a HW issue in ATI SB600 SATA that PxSERR.E should not be\nset on some conditions, for example, when there is no media in SATA\nCD/DVD drive or media is not ready, AHCI controller fails to execute\nATAPI commands and reports PORT_IRQ_TF_ERR, but ATI SB600 SATA\ncontroller sets PxSERR.E at the\nsame time, which is not necessary.\n This patch is just to ignore the INTERNAL ERROR in such case.\nWithout this patch, ahci error handler will report many errors as\nbelow:\n ----------- cut from dmesg -----------\nata9: soft resetting port\nata9: SATA link up 1.5 Gbps (SStatus 113 SControl 300)\nata9.00: configured for UDMA/33\nata9: EH complete\nata9.00: exception Emask 0x40 SAct 0x0 SErr 0x800 action 0x2\nata9.00: (irq_stat 0x40000001)\nata9.00: cmd a0/00:00:00:00:20/00:00:00:00:00/a0 tag 0 cdb 0x0 data 0\n res 51/24:03:00:00:20/00:00:00:00:00/a0 Emask 0x40 (internal error)\nata9: soft resetting port\nata9: SATA link up 1.5 Gbps (SStatus 113 SControl 300)\nata9.00: configured for UDMA/33\nata9: EH complete\nata9.00: exception Emask 0x40 SAct 0x0 SErr 0x800 action 0x2\nata9.00: (irq_stat 0x40000001)\nata9.00: cmd a0/01:00:00:00:00/00:00:00:00:00/a0 tag 0 cdb 0x43 data 12 in\n res 51/24:03:00:00:00/00:00:00:00:00/a0 Emask 0x40 (internal error)\n -------- end cut ---------\n\nSigned-off-by: Conke Hu \u003cconke.hu@amd.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "8af12cdb7c4aa9ed278ed71a8b5b130f2d8c8920", "tree": "9fbaacfba50d267908293d8a18d6a0cb7dd0b807", "parents": [ "c3442e296517aee733d62fc3fe03211598902c7d" ], "author": { "name": "Jason Gaston", "email": "jason.d.gaston@intel.com", "time": "Fri Mar 02 17:39:46 2007 -0800" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Tue Mar 06 04:04:30 2007 -0500" }, "message": "ahci: RAID mode SATA patch for Intel ICH9M\n\nThis patch adds the Intel ICH9M RAID controller DID for SATA support.\n\nSigned-off-by: Jason Gaston \u003cjason.d.gaston@intel.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "438ac6d5e3f8106a6bd1a5682c508d660294a85d", "tree": "759aad55bb9850fe21709e12ca79cbdb3bf881f2", "parents": [ "b23ff24436c97fb26428f3a337faf189292cc307" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Fri Mar 02 17:31:26 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Mar 02 18:30:35 2007 -0500" }, "message": "libata: add missing CONFIG_PM in LLDs\n\nAdd missing #ifdef CONFIG_PM conditionals around all PM related parts\nin libata LLDs.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "afb2d552bc4c241c009f5947311a95de426a75d9", "tree": "c6dc4115ca8bb7e64431af86d553328f13d289fc", "parents": [ "e34bb370dec4919b7e8b769d51ad2bc2535b6982" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Tue Feb 27 13:24:19 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Thu Mar 01 20:19:45 2007 -0500" }, "message": "ahci: improve spurious SDB FIS handling\n\nSpurious SDB FIS during NCQ might not contain spurious completions.\nIt could be spurious TF update or invalid async notification. Treat\nas HSM violation iff a spurious SDB FIS contains spurious completions;\notherwise, just whine once about it.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "e34bb370dec4919b7e8b769d51ad2bc2535b6982", "tree": "3fa5c0a00bfdb56a0bdf5974c0b3b61bf2ffa82c", "parents": [ "5ee2ae7fb2079c5775d8802cd282140d71632a2d" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Feb 26 20:24:03 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Thu Mar 01 20:19:45 2007 -0500" }, "message": "ahci/pata_jmicron: match class not function number\n\nMake jmiron_ata quirk update pdev-\u003eclass after programming the device\nand update ahci and pata_jmicron such that they match class code\ninstead of checking function number manually. For ahci, it matches\nfor vendor and class. For pata_jmicron, it matches vendor, device and\nclass as IDE class isn\u0027t as well defined as AHCI class.\n\nThis makes jmicron device matching more conventional and script\nfriendly.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "cb48cab7f363014e0a5dc21f7b4892c15d626d41", "tree": "13ac3a9a150900c1ba5cb40fce4ba4f169f00228", "parents": [ "a84471fe269c38ea3725345c43ad64e5f489bea2" ], "author": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon Feb 26 06:04:24 2007 -0500" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Mon Feb 26 06:04:24 2007 -0500" }, "message": "[libata] bump versions\n\nBump versions based on changes submitted during 2.6.21 merge window.\n\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "a2bbd0c923708a23c6fcc6bbc492f2eecadc676f", "tree": "3a425c8a8268ce1ca6ccf5fd31fb8af494596456", "parents": [ "16728da99861bdb6e44f066d536287990e752d7b" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Wed Feb 21 16:34:25 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Feb 23 05:37:10 2007 -0500" }, "message": "ahci: consider SDB FIS containing spurious NCQ completions HSM violation (regenerated)\n\nSDB FIS containing spurious NCQ completions is a clear protocol\nviolation. Currently, only some Maxtors with early firmware revisions\nare showing this problem. Those firmwares have other NCQ related\nproblems including buggy NCQ error reporting and occasional lock up\nafter NCQ errors.\n\nConsider spurious NCQ completions HSM violation and freeze the port\nafter it. EH will turn off NCQ after this happens several times.\nEventually drives which show this behavior should be blacklisted for\nNCQ.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "cd354f1ae75e6466a7e31b727faede57a1f89ca5", "tree": "09a2da1672465fefbc7fe06ff4e6084f1dd14c6b", "parents": [ "3fc605a2aa38899c12180ca311f1eeb61a6d867e" ], "author": { "name": "Tim Schmielau", "email": "tim@physik3.uni-rostock.de", "time": "Wed Feb 14 00:33:14 2007 -0800" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Wed Feb 14 08:09:54 2007 -0800" }, "message": "[PATCH] remove many unneeded #includes of sched.h\n\nAfter Al Viro (finally) succeeded in removing the sched.h #include in module.h\nrecently, it makes sense again to remove other superfluous sched.h includes.\nThere are quite a lot of files which include it but don\u0027t actually need\nanything defined in there. Presumably these includes were once needed for\nmacros that used to live in sched.h, but moved to other header files in the\ncourse of cleaning it up.\n\nTo ease the pain, this time I did not fiddle with any header files and only\nremoved #includes from .c-files, which tend to cause less trouble.\n\nCompile tested against 2.6.20-rc2 and 2.6.20-rc2-mm2 (with offsets) on alpha,\narm, i386, ia64, mips, powerpc, and x86_64 with allnoconfig, defconfig,\nallmodconfig, and allyesconfig as well as a few randconfigs on x86_64 and all\nconfigs in arch/arm/configs on arm. I also checked that no new warnings were\nintroduced by the patch (actually, some warnings are removed that were emitted\nby unnecessarily included header files).\n\nSigned-off-by: Tim Schmielau \u003ctim@physik3.uni-rostock.de\u003e\nAcked-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "246ce3b675843e0369643cceb4faeb6cf6d19a30", "tree": "b904fe7561e5eacd260d3f175a8f0c3b257598f2", "parents": [ "836250069fc0eeebe8b6aed772281535cc6e34f9" ], "author": { "name": "Akira Iguchi", "email": "akira2.iguchi@toshiba.co.jp", "time": "Fri Jan 26 16:27:58 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Feb 09 17:39:38 2007 -0500" }, "message": "libata: add another IRQ calls (libata drivers)\n\nThis patch is against each libata driver.\n\nTwo IRQ calls are added in ata_port_operations.\n- irq_on() is used to enable interrupts.\n- irq_ack() is used to acknowledge a device interrupt.\n\nIn most drivers, ata_irq_on() and ata_irq_ack() are used for\nirq_on and irq_ack respectively.\n\nIn some drivers (ex: ahci, sata_sil24) which cannot use them\nas is, ata_dummy_irq_on() and ata_dummy_irq_ack() are used.\n\nSigned-off-by: Kou Ishizaki \u003ckou.ishizaki@toshiba.co.jp\u003e\nSigned-off-by: Akira Iguchi \u003cakira2.iguchi@toshiba.co.jp\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "0d5ff566779f894ca9937231a181eb31e4adff0e", "tree": "d1c7495c932581c1d41aa7f0fdb303348da49106", "parents": [ "1a68ff13c8a9b517de3fd4187dc525412a6eba1b" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Thu Feb 01 15:06:36 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Feb 09 17:39:38 2007 -0500" }, "message": "libata: convert to iomap\n\nConvert libata core layer and LLDs to use iomap.\n\n* managed iomap is used. Pointer to pcim_iomap_table() is cached at\n host-\u003eiomap and used through out LLDs. This basically replaces\n host-\u003emmio_base.\n\n* if possible, pcim_iomap_regions() is used\n\nMost iomap operation conversions are taken from Jeff Garzik\n\u003cjgarzik@pobox.com\u003e\u0027s iomap branch.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "24dc5f33ea4b504cfbd23fa159a4cacba8e4d800", "tree": "d76de456157f555c9a65b83f426fd805fee1e846", "parents": [ "f0d36efdc624beb3d9e29b9ab9e9537bf0f25d5b" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Sat Jan 20 16:00:28 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Feb 09 17:39:37 2007 -0500" }, "message": "libata: update libata LLDs to use devres\n\nUpdate libata LLDs to use devres. Core layer is already converted to\nsupport managed LLDs. This patch simplifies initialization and fixes\nmany resource related bugs in init failure and detach path. For\nexample, all converted drivers now handle ata_device_add() failure\ngracefully without excessive resource rollback code.\n\nAs most resources are released automatically on driver detach, many\ndrivers don\u0027t need or can do with much simpler -\u003e{port|host}_stop().\nIn general, stop callbacks are need iff port or host needs to be given\ncommands to shut it down. Note that freezing is enough in many cases\nand ports are automatically frozen before being detached.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "f0d36efdc624beb3d9e29b9ab9e9537bf0f25d5b", "tree": "eac4efb465aa682d6eaac61f76b3174ffd9fd8cd", "parents": [ "0529c159dbdd79794796c1b50b39442d72efbe97" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Sat Jan 20 16:00:28 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Feb 09 17:39:37 2007 -0500" }, "message": "libata: update libata core layer to use devres\n\nUpdate libata core layer to use devres.\n\n* ata_device_add() acquires all resources in managed mode.\n\n* ata_host is allocated as devres associated with ata_host_release.\n\n* Port attached status is handled as devres associated with\n ata_host_attach_release().\n\n* Initialization failure and host removal is handedl by releasing\n devres group.\n\n* Except for ata_scsi_release() removal, LLD interface remains the\n same. Some functions use hacky is_managed test to support both\n managed and unmanaged devices. These will go away once all LLDs are\n updated to use devres.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "0529c159dbdd79794796c1b50b39442d72efbe97", "tree": "417e2285c048ca582ba6e1f40119930c460250ad", "parents": [ "9ac7849e35f705830f7b016ff272b0ff1f7ff759" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Sat Jan 20 16:00:26 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Feb 09 17:39:37 2007 -0500" }, "message": "libata: implement ata_host_detach()\n\nImplement ata_host_detach() which calls ata_port_detach() for each\nport in the host and export it. ata_port_detach() is now internal and\nthus un-exported. ata_host_detach() will be used as the \u0027deregister\nfrom libata layer\u0027 function after devres conversion.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "553c4aa630af7bc885e056d0436e4eb7f238579b", "tree": "5a6cf3b15e05309fcfbdb5f68471e2a20b235613", "parents": [ "8bfa79fcb81d2bdb043f60ab4171704467808b55" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Tue Dec 26 19:39:50 2006 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Feb 09 17:39:30 2007 -0500" }, "message": "libata: handle pci_enable_device() failure while resuming\n\nHandle pci_enable_device() failure while resuming. This patch kills\nthe \"ignoring return value of \u0027pci_enable_device\u0027\" warning message and\npropagates __must_check through ata_pci_device_do_resume().\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "904dbd1307100edc12e2f98dd12b2338f1914f5b", "tree": "ee76372ee2541c1cb739f1043793e2015184c287", "parents": [ "4112e16a7c606a80810d22d55bfc742eaa61fecb" ], "author": { "name": "Alan", "email": "alan@lxorguk.ukuu.org.uk", "time": "Mon Jan 08 12:07:25 2007 +0000" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Feb 09 17:39:30 2007 -0500" }, "message": "ahci: Remove jmicron fixup\n\nThe AHCI set up is handled properly along with the other bits in the\nJMICRON quirk. Remove the code whacking it in ahci.c as its un-needed and\nalso blindly fiddles with bits it doesn\u0027t own.\n\nSigned-off-by: Alan Cox \u003calan@redhat.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "c9f89475a5b184e9a6077b995ce340e6804c1b1a", "tree": "de0b8eb7c7d514cbc14339705ef278bdb72ac90f", "parents": [ "95006188cb1399f1358330503906e5891c129a10" ], "author": { "name": "Conke Hu", "email": "conke.hu@amd.com", "time": "Tue Jan 09 05:32:51 2007 -0500" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Feb 09 17:39:29 2007 -0500" }, "message": "Add pci class code for SATA \u0026 AHCI, and replace some magic numbers.\n\nSigned-off-by: Conke Hu \u003cconke.hu@amd.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "04d4f7a1143e4fb291cd1584c9ac8de4ba584d34", "tree": "396b6f77b84355243b8d4b48be9925fb3986fa52", "parents": [ "92ccc5f7558f24edf7129a24a8e2ce338009b0dd" ], "author": { "name": "Al Viro", "email": "viro@ftp.linux.org.uk", "time": "Fri Feb 09 16:39:30 2007 +0000" }, "committer": { "name": "Linus Torvalds", "email": "torvalds@woody.linux-foundation.org", "time": "Fri Feb 09 09:14:07 2007 -0800" }, "message": "[PATCH] ahci: trivial endianness annotations\n\nSigned-off-by: Al Viro \u003cviro@zeniv.linux.org.uk\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n" }, { "commit": "a718728f9e40ec79c0879ec6509a54fee214f5b2", "tree": "547885a7f46380d10c6ebdcf16cac96d36d6991d", "parents": [ "7d620a4e531ae4d432d3c88f7d4b75327d881a87" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Sat Jan 27 11:04:26 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Sat Jan 27 02:50:36 2007 -0500" }, "message": "ahci: port_no should be used when clearing IRQ in ahci_thaw()\n\nap-\u003eid is logcial port ID which is unique among all ATA ports and\ndoesn\u0027t have anything to do with hardware port index. ap-\u003eport_no is\nthe hardware port index and thus should be used when clearing IRQ mask\nin ahci_thaw().\n\nThis problem has been spotted by Jeff Garzik \u003cjgarzik@pobox.com\u003e.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "dfd7a3db3898e299bdc25f0c77081a8632b3a73c", "tree": "d8e10936d9a40e8b5d0ac86461b0b760e98c6367", "parents": [ "d02598721706ab62a574823479b1f6c26c8980d2" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Fri Jan 26 15:37:20 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Jan 26 17:24:07 2007 -0500" }, "message": "ahci: use 0x80 as wait stat value instead of 0xff\n\nBefore hardreset, ahci initialized stat part of received FIS area to\n0xff to wait for the first D2H Reg FIS which would change the value to\ndevice ready state. This used to work but now libata considers status\nvalue of 0xff as device not present making this wait prone to failure.\n\nThis patch makes ahci use 0x80 for the wait stat value instead of\n0xff to fix the above problem.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\n\n drivers/ata/ahci.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "6096b63e2584796341baf7e7735f98d387f489f2", "tree": "b8595dbc564b166b9594c0082682b1ca27f4e828", "parents": [ "61dd08c6c8d2b4ede530e43c01fa72f789ef65b1" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Fri Jan 26 14:47:38 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Fri Jan 26 17:24:07 2007 -0500" }, "message": "ahci: fix endianness in spurious interrupt message\n\nFix endianness in spurious interrupt message.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "0291f95fdb5fcd91cc077aafabea2c5b109fa8a8", "tree": "c7d92de1788b8939fd8a810d5e96d5954d28a562", "parents": [ "17234246eb82898cf98e3c29e81d941c738e0587" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Thu Jan 25 19:16:28 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Thu Jan 25 17:22:47 2007 -0500" }, "message": "ahci: improve and limit spurious interrupt messages, take#3\n\nWe\u0027re still seeing a lot of issues with NCQ implementation in drive\nfirmwares. Sprious FISes during NCQ command phase occur on many\ndrives and some of them seem potentially dangerous (at least to me).\nUntil we find the solution, spurious messages can give us more info.\nImprove and limit them such that more info can be reported while not\ndisturbing users too much.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "07c53dac4904206a50dd7c87adabbb1acff903fb", "tree": "09fb7d1b53b4e6b5aabf05139ca8fff866e7e8d0", "parents": [ "f740d1689d91415cfc749d17138a11ed03b7d38b" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Sun Jan 21 02:10:11 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Wed Jan 24 02:03:45 2007 -0500" }, "message": "ahci: don\u0027t enter slumber on power down\n\nSome ATA/ATAPI devices act weirdly after the link is put into slumber\nmode. Some hang completely requiring physical power removal while\nothers fail to wake up till the link is hardreset a couple of times.\n\nThe addition of slumber on power down was never driven by real need.\nIt just followed what ahci spec said literally. The spec itself seems\nfaulty in that it doesn\u0027t consider devices (not controllers) which\ndon\u0027t support link powersaving mode.\n\nTheory never matches reality when it comes to dark allys of cheap\nATA/ATAPI world. It\u0027s just unrealistic to expect vendors to test\nrarely used link powersaving feature rigorously. This patch makes\nahci more friendly to the coldness of reality.\n\nThis shouldn\u0027t have any negative effect - when suspend operation\nsucceeds, we power off the whole machine; otherwise, we wake up\neverything. I can\u0027t see any reason to be so elaborate with powering\ndown the link in the first place.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "82490c0937cb455e7e4150455ff52e89a9fc5ab8", "tree": "91b5ed3c9d10a08764bd221b58acd059ec1aa034", "parents": [ "419dd8378dfa32985672ab7927b4bc827f33b332" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Tue Jan 23 15:13:39 2007 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Wed Jan 24 01:57:30 2007 -0500" }, "message": "ahci: make ULi M5288 ignore interface fatal error bit\n\nAs with JMicron controllers, ULi M5288 sets interface fatal error bit\non device error including ATAPI CC. This makes libata hardreset the\nport on ATAPI CC thus making it impossible to use. Ignore interface\nfatal error bit on ULi M5288. This fixes bugzilla bug #7837.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "6fbf5ba461f5bd36e921627568aca20abc0e2abe", "tree": "cc2facc5ca1d96f1961bed551cbda434d6fd25d8", "parents": [ "73720861d211e2b23c3026c6adea6f758676c46f" ], "author": { "name": "Peer Chen", "email": "pchen@nvidia.com", "time": "Wed Dec 20 14:18:00 2006 -0500" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Wed Dec 20 14:18:00 2006 -0500" }, "message": "[libata] Move some PCI IDs from sata_nv to ahci\n\nThe content of memory map io of BAR5 have been change from MCP65 then\nsata_nv can\u0027t work fine on the platform based on MCP65 and MCP67, so move\ntheir IDs from sata_nv.c to ahci.c.\n\nSigned-off-by: Peer Chen \u003cpchen@nvidia.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "551c012d7eea3dc5ec063c7ff9c718d39e77634f", "tree": "244c89c1e0d6878a036fde806f080bf8885c661b", "parents": [ "33480a0ede8dcc7e6483054279008f972bd56fd3" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Tue Dec 12 20:17:32 2006 +0900" }, "committer": { "name": "Jeff Garzik", "email": "jeff@garzik.org", "time": "Sat Dec 16 10:13:29 2006 -0500" }, "message": "[PATCH] ahci: do not mangle saved HOST_CAP while resetting controller\n\nDo not mangle with HOST_CAP while resetting controller. The code is\nthere for a historical reason. The mangling breaks controller feature\ndetection and 0 PORTS_IMPL workaround code.\n\nThis problem was spotted by Manoj Kasichainula.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\nCc: Manoj Kasichainula \u003cmanoj@io.com\u003e\nSigned-off-by: Jeff Garzik \u003cjeff@garzik.org\u003e\n" }, { "commit": "8e16f941226f15622fbbc416a1f3d8705001a191", "tree": "97bf87ebff9e3e69caa0a0ebdd9ee9291c5dfac5", "parents": [ "70e6ad0c6d1e6cb9ee3c036a85ca2561eb1fd766" ], "author": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Mon Nov 20 15:42:36 2006 +0900" }, "committer": { "name": "Tejun Heo", "email": "htejun@gmail.com", "time": "Sun Dec 03 17:56:29 2006 +0900" }, "message": "[PATCH] ahci: do not powerdown during initialization\n\nahci_init_controller() calls ahci_deinit_port() to make sure the\ncontroller is stopped before initializing the controller. In turn,\nahci_deinit_port() invokes ahci_power_down() to power down the port.\nIf the controller supports slumber mode, the link is put into it.\n\nUnfortunately, some devices don\u0027t implement link powersaving mode\nproperly and show erratic behavior after link is put into slumber\nmode. For example, HL-DT-ST DVD-RAM GSA-H30N completely locks up on\nslumber transition and can only be recovered with the *REAL* hard\nreset - power removal and reapply.\n\nNote that this makes the first probing reset different from all\nothers. If the above dvd-ram is hotplugged after ahci is initialized,\nno problem occurs because ahci is already fully initialized with phy\npowered up. So, this might also be the reason for other weird AHCI\ninitial probing abnormalities.\n\nThis patch moves power up/down out of port init/deinit and call them\nonly when needed.\n\nPower down is now called only when suspending. As system suspend\nusually involves powering down 12v for storage devices, this shouldn\u0027t\ncause problem even if the attached device doesn\u0027t support slumber\nmode. However, in partial power management and suspend failure cases,\ndevices might lock up after suspend attempt. I thought about removing\ntransition to slumber mode altogether but ahci spec mandates it before\nHBA D3 state transition. Blacklisting such devices might be the\nsolution.\n\nSigned-off-by: Tejun Heo \u003chtejun@gmail.com\u003e\n" } ], "next": "648a88be4a016d2637ace3ae74b85a0512255ee8" }