)]}'
{
  "log": [
    {
      "commit": "47437b2c9a64315efeb3d84e97ffefd6c3c67ef1",
      "tree": "e0dec7b29bebb0a2113f143576d940c571869aa0",
      "parents": [
        "d4c56f97ff21df405d0cebe11f49e3c3c79662b5"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sat Feb 02 19:49:59 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Feb 06 10:12:18 2008 -0700"
      },
      "message": "async_tx: allow architecture specific async_tx_find_channel implementations\n\nThe source and destination addresses are included to allow channel\nselection based on address alignment.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nReviewed-by: Haavard Skinnemoen \u003chskinnemoen@atmel.com\u003e\n"
    },
    {
      "commit": "d4c56f97ff21df405d0cebe11f49e3c3c79662b5",
      "tree": "e6b0de433d7c985982ac12815998242a786d87b2",
      "parents": [
        "0036731c88fdb5bf4f04a796a30b5e445fc57f54"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sat Feb 02 19:49:58 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Feb 06 10:12:18 2008 -0700"
      },
      "message": "async_tx: replace \u0027int_en\u0027 with operation preparation flags\n\nPass a full set of flags to drivers\u0027 per-operation \u0027prep\u0027 routines.\nCurrently the only flag passed is DMA_PREP_INTERRUPT.  The expectation is\nthat arch-specific async_tx_find_channel() implementations can exploit this\ncapability to find the best channel for an operation.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nAcked-by: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\nReviewed-by: Haavard Skinnemoen \u003chskinnemoen@atmel.com\u003e\n"
    },
    {
      "commit": "0036731c88fdb5bf4f04a796a30b5e445fc57f54",
      "tree": "66982e4a9fdb92fedadca35c0ccaa0b9a75e9d2e",
      "parents": [
        "d909b347591a23c5a2c324fbccd4c9c966f31c67"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sat Feb 02 19:49:57 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Feb 06 10:12:17 2008 -0700"
      },
      "message": "async_tx: kill tx_set_src and tx_set_dest methods\n\nThe tx_set_src and tx_set_dest methods were originally implemented to allow\nan array of addresses to be passed down from async_xor to the dmaengine\ndriver while minimizing stack overhead.  Removing these methods allows\ndrivers to have all transaction parameters available at \u0027prep\u0027 time, saves\ntwo function pointers in struct dma_async_tx_descriptor, and reduces the\nnumber of indirect branches..\n\nA consequence of moving this data to the \u0027prep\u0027 routine is that\nmulti-source routines like async_xor need temporary storage to convert an\narray of linear addresses into an array of dma addresses.  In order to keep\nthe same stack footprint of the previous implementation the input array is\nreused as storage for the dma addresses.  This requires that\nsizeof(dma_addr_t) be less than or equal to sizeof(void *).  As a\nconsequence CONFIG_DMADEVICES now depends on !CONFIG_HIGHMEM64G.  It also\nrequires that drivers be able to make descriptor resources available when\nthe \u0027prep\u0027 routine is polled.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nAcked-by: Shannon Nelson \u003cshannon.nelson@intel.com\u003e\n"
    },
    {
      "commit": "d909b347591a23c5a2c324fbccd4c9c966f31c67",
      "tree": "1092bfdc2722eed041a29752a62836366855c30a",
      "parents": [
        "e73ef9acfd30f36bf7c60237ecffe7bbca8068d6"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sat Feb 02 19:30:14 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Feb 06 10:12:17 2008 -0700"
      },
      "message": "async_tx: kill ASYNC_TX_ASSUME_COHERENT\n\nRemove the unused ASYNC_TX_ASSUME_COHERENT flag.  Async_tx is\nmeant to hide the difference between asynchronous hardware and synchronous\nsoftware operations, this flag requires clients to understand cache\ncoherency consequences of the async path.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nReviewed-by: Haavard Skinnemoen \u003chskinnemoen@atmel.com\u003e\n"
    },
    {
      "commit": "cf8f68aa76e8e12f9dcbba3ffe61fb9f2a3a0c2b",
      "tree": "f53fa3040cfd8fcc47eb8aaed60a0a79181cd9b2",
      "parents": [
        "1367a3d310afc1ce758c8b94a0dc77834b4494a0"
      ],
      "author": {
        "name": "Denis Cheng",
        "email": "crquan@gmail.com",
        "time": "Sat Feb 02 19:29:58 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Feb 06 10:12:17 2008 -0700"
      },
      "message": "async_tx: use LIST_HEAD instead of LIST_HEAD_INIT\n\nsingle list_head variable initialized with LIST_HEAD_INIT could almost\nalways can be replaced with LIST_HEAD declaration, this shrinks the code\nand looks better.\n\nSigned-off-by: Denis Cheng \u003ccrquan@gmail.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "1367a3d310afc1ce758c8b94a0dc77834b4494a0",
      "tree": "cf6938c1662074f26ee16ff02d3c38332bc010ef",
      "parents": [
        "551e4fb2465b87de9d4aa1669b27d624435443bb"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Sat Feb 02 18:46:43 2008 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Wed Feb 06 10:12:17 2008 -0700"
      },
      "message": "async_tx: fix compile breakage, mark do_async_xor __always_inline\n\ndo_async_xor must be compiled away on !HAS_DMA archs.\n\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nAcked-by: Cornelia Huck \u003ccornelia.huck@de.ibm.com\u003e\n"
    },
    {
      "commit": "6247cdc2cd334dad0ea5428245a7d8f4b075f21e",
      "tree": "275bfcdb142a92ea347d264b6b37b17c98d41733",
      "parents": [
        "c5d2b9f444b8d9f5ad7c5e583686c119ba3a9ba7"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Fri Sep 21 13:27:04 2007 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Mon Sep 24 10:26:26 2007 -0700"
      },
      "message": "async_tx: fix dma_wait_for_async_tx\n\nFix dma_wait_for_async_tx to not loop forever in the case where a\ndependency chain is longer than two entries.  This condition will not\nhappen with current in-kernel drivers, but fix it for future drivers.\n\nFound-by: Saeed Bishara \u003csaeed.bishara@gmail.com\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n"
    },
    {
      "commit": "eb0645a8b1f14da300f40bb9f424640cd1181fbf",
      "tree": "462789626fcd1775bec80d74d19bcd68797589c8",
      "parents": [
        "7c6129c68fe90a61166800b40217a850b8faee98"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Fri Jul 20 00:31:46 2007 -0700"
      },
      "committer": {
        "name": "Linus Torvalds",
        "email": "torvalds@woody.linux-foundation.org",
        "time": "Fri Jul 20 08:44:19 2007 -0700"
      },
      "message": "async_tx: fix kmap_atomic usage in async_memcpy\n\nAndrew Morton:\n\t[async_memcpy] is very wrong if both ASYNC_TX_KMAP_DST and\n\tASYNC_TX_KMAP_SRC can ever be set.  We\u0027ll end up using the same kmap\n\tslot for both src add dest and we get either corrupted data or a BUG.\n\nEvgeniy Polyakov:\n\tBtw, shouldn\u0027t it always be kmap_atomic() even if flag is not set.\n\tThat pages are usual one returned by alloc_page().\n\nSo fix the usage of kmap_atomic and kill the ASYNC_TX_KMAP_DST and\nASYNC_TX_KMAP_SRC flags.\n\nCc: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nCc: Evgeniy Polyakov \u003cjohnpol@2ka.mipt.ru\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\n"
    },
    {
      "commit": "9bc89cd82d6f88fb0ca39b30445c329a430fd66b",
      "tree": "7bd0e856abd359f84edea1bacfd1dd32edd93fbb",
      "parents": [
        "685784aaf3cd0e3ff5e36c7ecf6f441cdbf57f73"
      ],
      "author": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Tue Jan 02 11:10:44 2007 -0700"
      },
      "committer": {
        "name": "Dan Williams",
        "email": "dan.j.williams@intel.com",
        "time": "Fri Jul 13 08:06:14 2007 -0700"
      },
      "message": "async_tx: add the async_tx api\n\nThe async_tx api provides methods for describing a chain of asynchronous\nbulk memory transfers/transforms with support for inter-transactional\ndependencies.  It is implemented as a dmaengine client that smooths over\nthe details of different hardware offload engine implementations.  Code\nthat is written to the api can optimize for asynchronous operation and the\napi will fit the chain of operations to the available offload resources. \n \n\tI imagine that any piece of ADMA hardware would register with the\n\t\u0027async_*\u0027 subsystem, and a call to async_X would be routed as\n\tappropriate, or be run in-line. - Neil Brown\n\nasync_tx exploits the capabilities of struct dma_async_tx_descriptor to\nprovide an api of the following general format:\n\nstruct dma_async_tx_descriptor *\nasync_\u003coperation\u003e(..., struct dma_async_tx_descriptor *depend_tx,\n\t\t\tdma_async_tx_callback cb_fn, void *cb_param)\n{\n\tstruct dma_chan *chan \u003d async_tx_find_channel(depend_tx, \u003coperation\u003e);\n\tstruct dma_device *device \u003d chan ? chan-\u003edevice : NULL;\n\tint int_en \u003d cb_fn ? 1 : 0;\n\tstruct dma_async_tx_descriptor *tx \u003d device ?\n\t\tdevice-\u003edevice_prep_dma_\u003coperation\u003e(chan, len, int_en) : NULL;\n\n\tif (tx) { /* run \u003coperation\u003e asynchronously */\n\t\t...\n\t\ttx-\u003etx_set_dest(addr, tx, index);\n\t\t...\n\t\ttx-\u003etx_set_src(addr, tx, index);\n\t\t...\n\t\tasync_tx_submit(chan, tx, flags, depend_tx, cb_fn, cb_param);\n\t} else { /* run \u003coperation\u003e synchronously */\n\t\t...\n\t\t\u003coperation\u003e\n\t\t...\n\t\tasync_tx_sync_epilog(flags, depend_tx, cb_fn, cb_param);\n\t}\n\n\treturn tx;\n}\n\nasync_tx_find_channel() returns a capable channel from its pool.  The\nchannel pool is organized as a per-cpu array of channel pointers.  The\nasync_tx_rebalance() routine is tasked with managing these arrays.  In the\nuniprocessor case async_tx_rebalance() tries to spread responsibility\nevenly over channels of similar capabilities.  For example if there are two\ncopy+xor channels, one will handle copy operations and the other will\nhandle xor.  In the SMP case async_tx_rebalance() attempts to spread the\noperations evenly over the cpus, e.g. cpu0 gets copy channel0 and xor\nchannel0 while cpu1 gets copy channel 1 and xor channel 1.  When a\ndependency is specified async_tx_find_channel defaults to keeping the\noperation on the same channel.  A xor-\u003ecopy-\u003exor chain will stay on one\nchannel if it supports both operation types, otherwise the transaction will\ntransition between a copy and a xor resource.\n\nCurrently the raid5 implementation in the MD raid456 driver has been\nconverted to the async_tx api.  A driver for the offload engines on the\nIntel Xscale series of I/O processors, iop-adma, is provided in a later\ncommit.  With the iop-adma driver and async_tx, raid456 is able to offload\ncopy, xor, and xor-zero-sum operations to hardware engines.\n \nOn iop342 tiobench showed higher throughput for sequential writes (20 - 30%\nimprovement) and sequential reads to a degraded array (40 - 55%\nimprovement).  For the other cases performance was roughly equal, +/- a few\npercentage points.  On a x86-smp platform the performance of the async_tx\nimplementation (in synchronous mode) was also +/- a few percentage points\nof the original implementation.  According to \u0027top\u0027 on iop342 CPU\nutilization drops from ~50% to ~15% during a \u0027resync\u0027 while the speed\naccording to /proc/mdstat doubles from ~25 MB/s to ~50 MB/s.\n \nThe tiobench command line used for testing was: tiobench --size 2048\n--block 4096 --block 131072 --dir /mnt/raid --numruns 5\n* iop342 had 1GB of memory available\n\nDetails:\n* if CONFIG_DMA_ENGINE\u003dn the asynchronous path is compiled away by making\n  async_tx_find_channel a static inline routine that always returns NULL\n* when a callback is specified for a given transaction an interrupt will\n  fire at operation completion time and the callback will occur in a\n  tasklet.  if the the channel does not support interrupts then a live\n  polling wait will be performed\n* the api is written as a dmaengine client that requests all available\n  channels\n* In support of dependencies the api implicitly schedules channel-switch\n  interrupts.  The interrupt triggers the cleanup tasklet which causes\n  pending operations to be scheduled on the next channel\n* Xor engines treat an xor destination address differently than a software\n  xor routine.  To the software routine the destination address is an implied\n  source, whereas engines treat it as a write-only destination.  This patch\n  modifies the xor_blocks routine to take a an explicit destination address\n  to mirror the hardware.\n\nChangelog:\n* fixed a leftover debug print\n* don\u0027t allow callbacks in async_interrupt_cond\n* fixed xor_block changes\n* fixed usage of ASYNC_TX_XOR_DROP_DEST\n* drop dma mapping methods, suggested by Chris Leech\n* printk warning fixups from Andrew Morton\n* don\u0027t use inline in C files, Adrian Bunk\n* select the API when MD is enabled\n* BUG_ON xor source counts \u003c\u003d 1\n* implicitly handle hardware concerns like channel switching and\n  interrupts, Neil Brown\n* remove the per operation type list, and distribute operation capabilities\n  evenly amongst the available channels\n* simplify async_tx_find_channel to optimize the fast path\n* introduce the channel_table_initialized flag to prevent early calls to\n  the api\n* reorganize the code to mimic crypto\n* include mm.h as not all archs include it in dma-mapping.h\n* make the Kconfig options non-user visible, Adrian Bunk\n* move async_tx under crypto since it is meant as \u0027core\u0027 functionality, and\n  the two may share algorithms in the future\n* move large inline functions into c files\n* checkpatch.pl fixes\n* gpl v2 only correction\n\nCc: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\nAcked-By: NeilBrown \u003cneilb@suse.de\u003e\n"
    }
  ]
}