)]}'
{
  "log": [
    {
      "commit": "17099b1142f6c0359fca60a3464dea8fb30badea",
      "tree": "26b9f3955dca84ccab594a76680c2a71e166768a",
      "parents": [
        "ed203dadcd1373e80e95b04075e1eefc554a914b"
      ],
      "author": {
        "name": "Ralf Baechle",
        "email": "ralf@linux-mips.org",
        "time": "Sat Jul 14 13:24:05 2007 +0100"
      },
      "committer": {
        "name": "Ralf Baechle",
        "email": "ralf@linux-mips.org",
        "time": "Fri Jul 20 18:57:39 2007 +0100"
      },
      "message": "[MIPS] Make support for weakly ordered LL/SC a config option.\n\nNone of weakly ordered processor supported in tree need this but it seems\nlike this could change ...\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n"
    },
    {
      "commit": "0004a9dfeaa709a7f853487aba19932c9b1a87c8",
      "tree": "e9f1f4b1ca897e57f46778cef283617ba83fc855",
      "parents": [
        "08f57f7ffe5819e537301b1f1109fa4fc670bfff"
      ],
      "author": {
        "name": "Ralf Baechle",
        "email": "ralf@linux-mips.org",
        "time": "Tue Oct 31 03:45:07 2006 +0000"
      },
      "committer": {
        "name": "Ralf Baechle",
        "email": "ralf@linux-mips.org",
        "time": "Mon Dec 04 22:43:14 2006 +0000"
      },
      "message": "[MIPS] Cleanup memory barriers for weakly ordered systems.\n\nAlso the R4000 / R4600 LL/SC instructions imply a sync so no explicit sync\nneeded.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n"
    }
  ]
}